Re: [casper] 1-2 GHz sampler

Hi Ryan, We'd be interested in learning more about your interleave-fixing technique as well. If JPL will let you tell us about it that would be great. If you can't release detailed code/etc, even a high-level description of the approach would be nice. Cheers, Paul On Mon, 28 May 2012,

Re: [casper] 1-2 GHz sampler

For the ASIAA designed 8-bit ADC using e2v EV8AQ160 at 5GS/s we at CfA (chiefly Bob Wilson, Nimesh Patel and Rurik Primiani) have done a fair amount of testing using both swept sine waves and wideband noise as input. There are measurements of frequency response, SFDR, THD, noise power ratio,

Re: [casper] 1-2 GHz sampler

For the ASIAA designed 8-bit ADC using e2v EV8AQ160 at 5GS/s we at CfA (chiefly Bob Wilson, Nimesh Patel and Rurik Primiani) have done a fair amount of testing using both swept sine waves and wideband noise as input. There are measurements of frequency response, SFDR, THD, noise power ratio,

Re: [casper] 1-2 GHz sampler

Ryan, As Jonathan said, we have been testing the adc1x5000-8. I would also like to hear about your approach. We don't see such large core-to-core differences as you suggest and the improvements I have been able to achieve have been minimal from the point of view of a radio astronomy correlator.

Re: [casper] 1-2 GHz sampler

I wouldn't be surprised if Ryan has a more clever way to do it, but one option is to use an extension of the method that Matt Morgan and Rick Fisher (i.e. http://www.gb.nrao.edu/electronics/edir/edir320.pdf) developed for I/Q imbalance compensation. Basically you make a filterbank with each of the

Re: [casper] 1-2 GHz sampler

Thanks for the references. I have been planning to implement a compass search when we have more ADCs and I get back to evaluating them. Since our 4 cores are all on the same chip, the cores were more matched and I had a much smaller improvement in SFDR. Bob On Tue, May 29, 2012 at 1:50 PM,

[casper] ten_gbe tx overflow at 28MHz (156.25MHz)

Hey guys, I've got several designs where I consistently clock 512 64-bit samples into the ten gbe0 (v2 block) at a rate of ~14MHz. The fpga clock is running at 200. It's my understanding that I still should have some room to get faster data off. I went up by a factor of 2 (the only change in

Re: [casper] ten_gbe tx overflow at 28MHz (156.25MHz)

On Tue, May 29, 2012 at 4:45 PM, Laura Vertatschitsch verta...@gmail.com wrote: Hey guys, I've got several designs where I consistently clock 512 64-bit samples into the ten gbe0 (v2 block) at a rate of ~14MHz.  The fpga clock is running at 200.  It's my understanding that I still should have

[casper] casper website down?

Hi CASPER, It looks like the website (casper.berkeley.edu) is down? I was trying to read some documentation. Regards, Melissa

Re: [casper] casper website down?

Hi Melissa, CC all, Space Science Lab is having a power outage for the next 2 days so the website will be down. Sorry for the late notice. Mark On May 29, 2012 5:00 PM, Soriano, Melissa (335J) melissa.a.sori...@jpl.nasa.gov wrote: Hi CASPER, It looks like the website

Re: [casper] tap-start

Hi CASPER, We are having trouble running tap-start. We are running corr-0.6.9. It has been awhile since I have run tap-start and the arguments have changed (tap_dev was added). Based on the source code, the arguments appear to be: def tap_start(self, tap_dev, device, mac, ip, port) Can you