Hi all,
I have a strange error that arises after a small change to a design:
I have used the sync pulse to reset a counter, that in turn (together with
a comparator coupled to a register) produces a higher frequency pulse for
use in snap blocks i.e. to write the snap block data more frequently
Hi.
Maybe a boolean check box needs checked somewhere in your new logic?
John
Hi all,
I have a strange error that arises after a small change to a design:
I have used the sync pulse to reset a counter, that in turn (together with
a comparator coupled to a register) produces a higher
Hi Matt,
The qdr_cal routine calibrates the relationship of clock and data signals
in the link between the FPGA and QDR signals. Basically it writes test
patterns and reads them back looking for glitches. It then changes the
delay of IODELAY blocks so that data read from the QDR is captured
Hi, Charles,
Is it when you click OK on a block's mask dialog or when you run update
diagram or ???
Maybe you can find additional details in the model_sysgen.log or
model_sysgen_warning.log or model_sysgen_error.log files? It would
really help to know which block or file is causing this
4 matches
Mail list logo