Hi Matt,
See the commit trail at
https://github.com/jack-h/mlib_devel/commits/ami-devel/xps_base/XPS_ROACH2_base/pcores/qdr_controller_v1_00_a/hdl/verilog/qdrc_infrastructure.v
and in particular commits 06fa83a and 73cd65b.
In the first case, I basically played with the balancing of registering
Hi Casperites,
I'm trying to program an fpg file onto the Roach2, but I can't seem to get
it to program the fpga.
I keep getting this error:
?progdev qdr_err_check_2015_Mar_16_1247.fpg
#log info 957575770765 raw
attempting\_to\_program\_qdr_err_check_2015_Mar_16_1247.fpg
#log error 957575770765
Jack,
When you were having problems calibrating the qdr at high clock rate, how
did you go about removing half a clock cycle latency from the interface?
Thanks,
Matt
On Wed, Mar 11, 2015 at 12:27 PM, Matt Strader mstra...@physics.ucsb.edu
wrote:
I have my own fork of mlib_devel
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