Hi Michael,
As one of the Xilinx timing closure documents helpfully articulates, it's
very difficult to give specific recipes for solving timing problems, other
than reading the timing report, looking at things in PlanAhead/FPGA Editor,
iterating compiles and developing some intuition.
That
Hi everyone,
I'm having quite a lot of problems getting a particular design to compile, XPS
consistently reporting timing errors. The design is a wideband spectrometer,
somewhat similar to the tutorial 3 design. I'm running an iADC at 1024 MHz, and
the FPGA at 256 MHz. It is a two-polarisation
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