Hi Sharat,
To give some context:
The adc5g has four cores, each of which has 8 parallel output lanes for the
8 bits of data. The software puts the adc in test mode, so that all cores
output a sample of 0xff, followed by 7 samples of 0x00. The delays of the
data lines relative to the clock are
Hi, Sharat,
On Sep 6, 2015, at 11:02 PM, Jack Hickish wrote:
> As the code suggests, the error comes because bit 1 of core 3 appears to
> never be glitch free, no matter what the delay setting. It's not obvious to
> me what could cause this.
Just to expand on what Jack said, here are a few
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