Hello ,
I am designing a Wide-band spectro polarimeter for Low frequency solar
Observations modified (Tutorial 3 based ) and after modifying with some
additional functionalities (Increasing number of bits without quantizing
for the higher Dynamic Range ), I am getting this error. Can any one guide
me on how to handle these timing constraints. These timing constraints
mainly inside the FFT wideband block, XAUI block, and adc_clk_dcm
The number errors reduced after inserting delay unit blocks after ADC output
and several places.
The timing error report generated after loading the ncd file using
timingan application is bellow.
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--------------------------------------------------------------------------------
14.7
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Design file: system_map.ncd
Physical constraint file: system.pcf
Device,package,speed: xc5vsx95t,ff1136,-1 (PRODUCTION 1.73 2013-10-13,
STEPPING level 0)
Report level: verbose report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3284 - This timing report was generated using estimated delay
information. For accurate numbers, please refer to the post Place and Route
timing report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
================================================================================
Timing constraint: NET "epb_cs_n_IBUF" MAXDELAY = 4 ns;
1 net analyzed, 0 failing nets detected.
0 timing errors detected.
Maximum net delay is 1.758ns.
--------------------------------------------------------------------------------
Slack: 2.242ns epb_cs_n_IBUF
Report: 1.758ns delay meets 4.000ns timing constraint by 2.242ns
From To Delay(ns)
K13.I K12.T e 1.278
K13.I ILOGIC_X1Y181.D e 0.000
K13.I SLICE_X63Y98.SR e 1.758
--------------------------------------------------------------------------------
================================================================================
Timing constraint: NET
"graspx8_eth_2ch_36p18_adc/graspx8_eth_2ch_36p18_adc/adc_clk_buf" PERIOD =
5 ns HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide
(UG612).
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 component switching limit errors)
Minimum period is 3.600ns.
--------------------------------------------------------------------------------
Component Switching Limit Checks: NET "graspx8_eth_2ch_36p18_adc/graspx8_eth_2ch_36p18_adc/adc_clk_buf" PERIOD =
5 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 1.400ns (period - (min low pulse limit / (low pulse / period)))
Period: 5.000ns
Low pulse: 2.500ns
Low pulse limit: 1.800ns (Tdcmpw_CLKIN_200_250)
Physical resource:
graspx8_eth_2ch_36p18_adc/graspx8_eth_2ch_36p18_adc/CLKSHIFT_DCM/CLKIN
Logical resource:
graspx8_eth_2ch_36p18_adc/graspx8_eth_2ch_36p18_adc/CLKSHIFT_DCM/CLKIN
Location pin: DCM_ADV_X0Y10.CLKIN
Clock network:
graspx8_eth_2ch_36p18_adc/graspx8_eth_2ch_36p18_adc/adc_clk_buf
--------------------------------------------------------------------------------
Slack: 1.400ns (period - (min high pulse limit / (high pulse / period)))
Period: 5.000ns
High pulse: 2.500ns
High pulse limit: 1.800ns (Tdcmpw_CLKIN_200_250)
Physical resource:
graspx8_eth_2ch_36p18_adc/graspx8_eth_2ch_36p18_adc/CLKSHIFT_DCM/CLKIN
Logical resource:
graspx8_eth_2ch_36p18_adc/graspx8_eth_2ch_36p18_adc/CLKSHIFT_DCM/CLKIN
Location pin: DCM_ADV_X0Y10.CLKIN
Clock network:
graspx8_eth_2ch_36p18_adc/graspx8_eth_2ch_36p18_adc/adc_clk_buf
--------------------------------------------------------------------------------
Slack: 2.779ns (period - min period limit)
Period: 5.000ns
Min period limit: 2.221ns (450.248MHz) (Tdcmpc)
Physical resource:
graspx8_eth_2ch_36p18_adc/graspx8_eth_2ch_36p18_adc/CLKSHIFT_DCM/CLKIN
Logical resource:
graspx8_eth_2ch_36p18_adc/graspx8_eth_2ch_36p18_adc/CLKSHIFT_DCM/CLKIN
Location pin: DCM_ADV_X0Y10.CLKIN
Clock network:
graspx8_eth_2ch_36p18_adc/graspx8_eth_2ch_36p18_adc/adc_clk_buf
--------------------------------------------------------------------------------
================================================================================
Timing constraint: PERIOD analysis for net
"graspx8_eth_2ch_36p18_adc/graspx8_eth_2ch_36p18_adc/adc_clk_dcm" derived from NET
"graspx8_eth_2ch_36p18_adc/graspx8_eth_2ch_36p18_adc/adc_clk_buf" PERIOD = 5 ns
HIGH 50%; duty cycle corrected to 5 nS HIGH 2.500 nS
For more information, see Period Analysis in the Timing Closure User Guide
(UG612).
850490 paths analyzed, 127983 endpoints analyzed, 83 failing endpoints
83 timing errors detected. (0 setup errors, 83 hold errors, 0 component
switching limit errors)
Minimum period is 4.974ns.
--------------------------------------------------------------------------------
Slack (setup path): 0.026ns (requirement - (data path - clock path skew +
uncertainty))
Source:
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/packet_arranger_83c28b0df0/delay3/op_mem_20_24_1279_61
(FF)
Destination:
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/packet_arranger_83c28b0df0/mux1/Mshreg_pipe_26_22_2_61
(FF)
Requirement: 5.000ns
Data Path Delay: 4.879ns (Levels of Logic = 2)
Clock Path Skew: 0.000ns
Source Clock: adc0_clk rising at 0.000ns
Destination Clock: adc0_clk rising at 5.000ns
Clock Uncertainty: 0.095ns
Clock Uncertainty: 0.095ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.120ns
Phase Error (PE): 0.000ns
Maximum Data Path: graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/packet_arranger_83c28b0df0/delay3/op_mem_20_24_1279_61 to graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/packet_arranger_83c28b0df0/mux1/Mshreg_pipe_26_22_2_61
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X62Y79.AQ Tcko 0.471
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/packet_arranger_83c28b0df0/delay3/op_mem_20_24_1279_61
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/packet_arranger_83c28b0df0/delay3/op_mem_20_24_1279_61
SLICE_X57Y59.B2 net (fanout=2) e 1.841
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/packet_arranger_83c28b0df0/delay3/op_mem_20_24_1279_61
SLICE_X57Y59.B Tilo 0.094
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/pfb_fir_real1_2ec6b048ca/adder_1_1_b56c874848/addr2/op_mem_91_20_1_12
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/packet_arranger_83c28b0df0/mux1/Mmux_unregy_join_6_1295_G
SLICE_X57Y59.C4 net (fanout=1) e 0.650
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/N547
SLICE_X57Y59.CMUX Tilo 0.392
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/pfb_fir_real1_2ec6b048ca/adder_1_1_b56c874848/addr2/op_mem_91_20_1_12
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/N547_rt
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/packet_arranger_83c28b0df0/mux1/Mmux_unregy_join_6_1295
SLICE_X32Y59.AI net (fanout=1) e 1.096
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/packet_arranger_83c28b0df0/mux1/unregy_join_6_1(61)
SLICE_X32Y59.CLK Tds 0.335
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/fft_wideband_real1_c803bf39a8/fft_biplex_real_4x_2b89c26b6b/biplex_core_2a5930e356/fft_stage_6_dc5ad252fc/butterfly_direct_e8c77471d9/bus_convert_a0c8cb0500/conv2_499ce746c0/convert_9e5b56a1eb/adder/core_s(10)
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/packet_arranger_83c28b0df0/mux1/Mshreg_pipe_26_22_2_61
-------------------------------------------------
---------------------------
Total 4.879ns (1.292ns logic, 3.587ns
route)
(26.5% logic, 73.5%
route)
--------------------------------------------------------------------------------
Slack (setup path): 0.079ns (requirement - (data path - clock path skew +
uncertainty))
Source:
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/pfb_fir_real1_2ec6b048ca/adder_1_4_d243d24e4e/addr2/op_mem_91_20_1_23
(FF)
Destination:
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/pfb_fir_real1_2ec6b048ca/adder_1_4_d243d24e4e/addr3/comp12.core_instance12/blk00000001/blk00000004
(DSP)
Requirement: 5.000ns
Data Path Delay: 4.826ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: adc0_clk rising at 0.000ns
Destination Clock: adc0_clk rising at 5.000ns
Clock Uncertainty: 0.095ns
Clock Uncertainty: 0.095ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.120ns
Phase Error (PE): 0.000ns
Maximum Data Path: graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/pfb_fir_real1_2ec6b048ca/adder_1_4_d243d24e4e/addr2/op_mem_91_20_1_23 to graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/pfb_fir_real1_2ec6b048ca/adder_1_4_d243d24e4e/addr3/comp12.core_instance12/blk00000001/blk00000004
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X3Y7.AQ Tcko 0.450
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/pfb_fir_real1_2ec6b048ca/adder_1_4_d243d24e4e/addr2/op_mem_91_20_1_20
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/pfb_fir_real1_2ec6b048ca/adder_1_4_d243d24e4e/addr2/op_mem_91_20_1_23
DSP48_X6Y7.A5 net (fanout=1) e 2.548
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/pfb_fir_real1_2ec6b048ca/adder_1_4_d243d24e4e/addr2/op_mem_91_20_1_23
DSP48_X6Y7.CLK Tdspdck_AP_NM 1.828
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/pfb_fir_real1_2ec6b048ca/adder_1_4_d243d24e4e/addr3/comp12.core_instance12/blk00000001/blk00000004
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/pfb_fir_real1_2ec6b048ca/adder_1_4_d243d24e4e/addr3/comp12.core_instance12/blk00000001/blk00000004
-------------------------------------------------
---------------------------
Total 4.826ns (2.278ns logic, 2.548ns
route)
(47.2% logic, 52.8%
route)
--------------------------------------------------------------------------------
Slack (setup path): 0.096ns (requirement - (data path - clock path skew +
uncertainty))
Source:
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/pfb_fir_real1_2ec6b048ca/adder_1_4_d243d24e4e/addr2/op_mem_91_20_1_22
(FF)
Destination:
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/pfb_fir_real1_2ec6b048ca/adder_1_4_d243d24e4e/addr3/comp12.core_instance12/blk00000001/blk00000004
(DSP)
Requirement: 5.000ns
Data Path Delay: 4.809ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: adc0_clk rising at 0.000ns
Destination Clock: adc0_clk rising at 5.000ns
Clock Uncertainty: 0.095ns
Clock Uncertainty: 0.095ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.120ns
Phase Error (PE): 0.000ns
Maximum Data Path: graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/pfb_fir_real1_2ec6b048ca/adder_1_4_d243d24e4e/addr2/op_mem_91_20_1_22 to graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/pfb_fir_real1_2ec6b048ca/adder_1_4_d243d24e4e/addr3/comp12.core_instance12/blk00000001/blk00000004
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X3Y7.BQ Tcko 0.450
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/pfb_fir_real1_2ec6b048ca/adder_1_4_d243d24e4e/addr2/op_mem_91_20_1_20
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/pfb_fir_real1_2ec6b048ca/adder_1_4_d243d24e4e/addr2/op_mem_91_20_1_22
DSP48_X6Y7.A4 net (fanout=1) e 2.531
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/pfb_fir_real1_2ec6b048ca/adder_1_4_d243d24e4e/addr2/op_mem_91_20_1_22
DSP48_X6Y7.CLK Tdspdck_AP_NM 1.828
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/pfb_fir_real1_2ec6b048ca/adder_1_4_d243d24e4e/addr3/comp12.core_instance12/blk00000001/blk00000004
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/pfb_fir_real1_2ec6b048ca/adder_1_4_d243d24e4e/addr3/comp12.core_instance12/blk00000001/blk00000004
-------------------------------------------------
---------------------------
Total 4.809ns (2.278ns logic, 2.531ns
route)
(47.4% logic, 52.6%
route)
--------------------------------------------------------------------------------
Hold Paths: PERIOD analysis for net "graspx8_eth_2ch_36p18_adc/graspx8_eth_2ch_36p18_adc/adc_clk_dcm" derived from
NET "graspx8_eth_2ch_36p18_adc/graspx8_eth_2ch_36p18_adc/adc_clk_buf" PERIOD
= 5 ns HIGH 50%;
duty cycle corrected to 5 nS HIGH 2.500 nS
--------------------------------------------------------------------------------
Slack (hold path): -0.048ns (requirement - (clock path skew + uncertainty
- data path))
Source:
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/fft_wideband_real_cd4ba8024c/fft_direct_fdade5ca6a/butterfly0_0_0e41f7cf49/twiddle_8f231d8c7a/coeff_gen_86e851051c/feedback_osc_e6336c5b93/cmult_120386001d/imim/Mmult_mult_46_56
(DSP)
Destination:
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/fft_wideband_real_cd4ba8024c/fft_direct_fdade5ca6a/butterfly0_0_0e41f7cf49/twiddle_8f231d8c7a/coeff_gen_86e851051c/feedback_osc_e6336c5b93/cmult_120386001d/rere/Maddsub_mult_46_56
(DSP)
Requirement: 0.000ns
Data Path Delay: -0.048ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: adc0_clk rising at 5.000ns
Destination Clock: adc0_clk rising at 5.000ns
Clock Uncertainty: 0.000ns
Minimum Data Path: graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/fft_wideband_real_cd4ba8024c/fft_direct_fdade5ca6a/butterfly0_0_0e41f7cf49/twiddle_8f231d8c7a/coeff_gen_86e851051c/feedback_osc_e6336c5b93/cmult_120386001d/imim/Mmult_mult_46_56 to graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/fft_wideband_real_cd4ba8024c/fft_direct_fdade5ca6a/butterfly0_0_0e41f7cf49/twiddle_8f231d8c7a/coeff_gen_86e851051c/feedback_osc_e6336c5b93/cmult_120386001d/rere/Maddsub_mult_46_56
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
DSP48_X3Y31.P26 Tdspcko_PP 0.190
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/fft_wideband_real_cd4ba8024c/fft_direct_fdade5ca6a/butterfly0_0_0e41f7cf49/twiddle_8f231d8c7a/coeff_gen_86e851051c/feedback_osc_e6336c5b93/cmult_120386001d/imim/Mmult_mult_46_56
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/fft_wideband_real_cd4ba8024c/fft_direct_fdade5ca6a/butterfly0_0_0e41f7cf49/twiddle_8f231d8c7a/coeff_gen_86e851051c/feedback_osc_e6336c5b93/cmult_120386001d/imim/Mmult_mult_46_56
DSP48_X3Y30.C26 net (fanout=1) e 0.131
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/fft_wideband_real_cd4ba8024c/fft_direct_fdade5ca6a/butterfly0_0_0e41f7cf49/twiddle_8f231d8c7a/coeff_gen_86e851051c/feedback_osc_e6336c5b93/cmult_120386001d/imim/op_mem_65_20(1)(26)
DSP48_X3Y30.CLK Tdspckd_CC (-Th) 0.369
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/fft_wideband_real_cd4ba8024c/fft_direct_fdade5ca6a/butterfly0_0_0e41f7cf49/twiddle_8f231d8c7a/coeff_gen_86e851051c/feedback_osc_e6336c5b93/cmult_120386001d/rere/Maddsub_mult_46_56
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/fft_wideband_real_cd4ba8024c/fft_direct_fdade5ca6a/butterfly0_0_0e41f7cf49/twiddle_8f231d8c7a/coeff_gen_86e851051c/feedback_osc_e6336c5b93/cmult_120386001d/rere/Maddsub_mult_46_56
-------------------------------------------------
---------------------------
Total -0.048ns (-0.179ns logic,
0.131ns route)
(372.9% logic, -272.9%
route)
--------------------------------------------------------------------------------
Slack (hold path): -0.048ns (requirement - (clock path skew + uncertainty
- data path))
Source:
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/fft_wideband_real_cd4ba8024c/fft_direct_fdade5ca6a/butterfly0_0_0e41f7cf49/twiddle_8f231d8c7a/coeff_gen_86e851051c/feedback_osc_e6336c5b93/cmult_120386001d/imim/Mmult_mult_46_56
(DSP)
Destination:
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/fft_wideband_real_cd4ba8024c/fft_direct_fdade5ca6a/butterfly0_0_0e41f7cf49/twiddle_8f231d8c7a/coeff_gen_86e851051c/feedback_osc_e6336c5b93/cmult_120386001d/rere/Maddsub_mult_46_56
(DSP)
Requirement: 0.000ns
Data Path Delay: -0.048ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: adc0_clk rising at 5.000ns
Destination Clock: adc0_clk rising at 5.000ns
Clock Uncertainty: 0.000ns
Minimum Data Path: graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/fft_wideband_real_cd4ba8024c/fft_direct_fdade5ca6a/butterfly0_0_0e41f7cf49/twiddle_8f231d8c7a/coeff_gen_86e851051c/feedback_osc_e6336c5b93/cmult_120386001d/imim/Mmult_mult_46_56 to graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/fft_wideband_real_cd4ba8024c/fft_direct_fdade5ca6a/butterfly0_0_0e41f7cf49/twiddle_8f231d8c7a/coeff_gen_86e851051c/feedback_osc_e6336c5b93/cmult_120386001d/rere/Maddsub_mult_46_56
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
DSP48_X3Y31.P22 Tdspcko_PP 0.190
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/fft_wideband_real_cd4ba8024c/fft_direct_fdade5ca6a/butterfly0_0_0e41f7cf49/twiddle_8f231d8c7a/coeff_gen_86e851051c/feedback_osc_e6336c5b93/cmult_120386001d/imim/Mmult_mult_46_56
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/fft_wideband_real_cd4ba8024c/fft_direct_fdade5ca6a/butterfly0_0_0e41f7cf49/twiddle_8f231d8c7a/coeff_gen_86e851051c/feedback_osc_e6336c5b93/cmult_120386001d/imim/Mmult_mult_46_56
DSP48_X3Y30.C22 net (fanout=1) e 0.131
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/fft_wideband_real_cd4ba8024c/fft_direct_fdade5ca6a/butterfly0_0_0e41f7cf49/twiddle_8f231d8c7a/coeff_gen_86e851051c/feedback_osc_e6336c5b93/cmult_120386001d/imim/op_mem_65_20(1)(22)
DSP48_X3Y30.CLK Tdspckd_CC (-Th) 0.369
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/fft_wideband_real_cd4ba8024c/fft_direct_fdade5ca6a/butterfly0_0_0e41f7cf49/twiddle_8f231d8c7a/coeff_gen_86e851051c/feedback_osc_e6336c5b93/cmult_120386001d/rere/Maddsub_mult_46_56
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/fft_wideband_real_cd4ba8024c/fft_direct_fdade5ca6a/butterfly0_0_0e41f7cf49/twiddle_8f231d8c7a/coeff_gen_86e851051c/feedback_osc_e6336c5b93/cmult_120386001d/rere/Maddsub_mult_46_56
-------------------------------------------------
---------------------------
Total -0.048ns (-0.179ns logic,
0.131ns route)
(372.9% logic, -272.9%
route)
--------------------------------------------------------------------------------
Slack (hold path): -0.048ns (requirement - (clock path skew + uncertainty
- data path))
Source:
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/fft_wideband_real_cd4ba8024c/fft_direct_fdade5ca6a/butterfly0_0_0e41f7cf49/twiddle_8f231d8c7a/coeff_gen_86e851051c/feedback_osc_e6336c5b93/cmult_120386001d/imim/Mmult_mult_46_56
(DSP)
Destination:
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/fft_wideband_real_cd4ba8024c/fft_direct_fdade5ca6a/butterfly0_0_0e41f7cf49/twiddle_8f231d8c7a/coeff_gen_86e851051c/feedback_osc_e6336c5b93/cmult_120386001d/rere/Maddsub_mult_46_56
(DSP)
Requirement: 0.000ns
Data Path Delay: -0.048ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: adc0_clk rising at 5.000ns
Destination Clock: adc0_clk rising at 5.000ns
Clock Uncertainty: 0.000ns
Minimum Data Path: graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/fft_wideband_real_cd4ba8024c/fft_direct_fdade5ca6a/butterfly0_0_0e41f7cf49/twiddle_8f231d8c7a/coeff_gen_86e851051c/feedback_osc_e6336c5b93/cmult_120386001d/imim/Mmult_mult_46_56 to graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/fft_wideband_real_cd4ba8024c/fft_direct_fdade5ca6a/butterfly0_0_0e41f7cf49/twiddle_8f231d8c7a/coeff_gen_86e851051c/feedback_osc_e6336c5b93/cmult_120386001d/rere/Maddsub_mult_46_56
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
DSP48_X3Y31.P30 Tdspcko_PP 0.190
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/fft_wideband_real_cd4ba8024c/fft_direct_fdade5ca6a/butterfly0_0_0e41f7cf49/twiddle_8f231d8c7a/coeff_gen_86e851051c/feedback_osc_e6336c5b93/cmult_120386001d/imim/Mmult_mult_46_56
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/fft_wideband_real_cd4ba8024c/fft_direct_fdade5ca6a/butterfly0_0_0e41f7cf49/twiddle_8f231d8c7a/coeff_gen_86e851051c/feedback_osc_e6336c5b93/cmult_120386001d/imim/Mmult_mult_46_56
DSP48_X3Y30.C30 net (fanout=1) e 0.131
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/fft_wideband_real_cd4ba8024c/fft_direct_fdade5ca6a/butterfly0_0_0e41f7cf49/twiddle_8f231d8c7a/coeff_gen_86e851051c/feedback_osc_e6336c5b93/cmult_120386001d/imim/op_mem_65_20(1)(30)
DSP48_X3Y30.CLK Tdspckd_CC (-Th) 0.369
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/fft_wideband_real_cd4ba8024c/fft_direct_fdade5ca6a/butterfly0_0_0e41f7cf49/twiddle_8f231d8c7a/coeff_gen_86e851051c/feedback_osc_e6336c5b93/cmult_120386001d/rere/Maddsub_mult_46_56
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/fft_wideband_real_cd4ba8024c/fft_direct_fdade5ca6a/butterfly0_0_0e41f7cf49/twiddle_8f231d8c7a/coeff_gen_86e851051c/feedback_osc_e6336c5b93/cmult_120386001d/rere/Maddsub_mult_46_56
-------------------------------------------------
---------------------------
Total -0.048ns (-0.179ns logic,
0.131ns route)
(372.9% logic, -272.9%
route)
--------------------------------------------------------------------------------
Component Switching Limit Checks: PERIOD analysis for net "graspx8_eth_2ch_36p18_adc/graspx8_eth_2ch_36p18_adc/adc_clk_dcm" derived from
NET "graspx8_eth_2ch_36p18_adc/graspx8_eth_2ch_36p18_adc/adc_clk_buf" PERIOD
= 5 ns HIGH 50%;
duty cycle corrected to 5 nS HIGH 2.500 nS
--------------------------------------------------------------------------------
Slack: 2.778ns (period - min period limit)
Period: 5.000ns
Min period limit: 2.222ns (450.045MHz) (Trper_CLKA)
Physical resource:
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/subsystem3_919ba2a61f/simple_bram_vacc8_b26b51f34f/delay_bram_5afb15e97f/single_port_ram/comp0.core_instance0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_init.ram/SP.WIDE_PRIM18.SP/CLKAL
Logical resource:
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/subsystem3_919ba2a61f/simple_bram_vacc8_b26b51f34f/delay_bram_5afb15e97f/single_port_ram/comp0.core_instance0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_init.ram/SP.WIDE_PRIM18.SP/CLKAL
Location pin: RAMB36_X0Y4.CLKARDCLKL
Clock network: adc0_clk
--------------------------------------------------------------------------------
Slack: 2.778ns (period - min period limit)
Period: 5.000ns
Min period limit: 2.222ns (450.045MHz) (Trper_CLKB)
Physical resource:
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/subsystem3_919ba2a61f/simple_bram_vacc8_b26b51f34f/delay_bram_5afb15e97f/single_port_ram/comp0.core_instance0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_init.ram/SP.WIDE_PRIM18.SP/CLKBL
Logical resource:
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/subsystem3_919ba2a61f/simple_bram_vacc8_b26b51f34f/delay_bram_5afb15e97f/single_port_ram/comp0.core_instance0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_init.ram/SP.WIDE_PRIM18.SP/CLKBL
Location pin: RAMB36_X0Y4.CLKBWRCLKL
Clock network: adc0_clk
--------------------------------------------------------------------------------
Slack: 2.778ns (period - min period limit)
Period: 5.000ns
Min period limit: 2.222ns (450.045MHz) (Trper_CLKA)
Physical resource:
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/subsystem3_919ba2a61f/simple_bram_vacc8_b26b51f34f/delay_bram_5afb15e97f/single_port_ram/comp0.core_instance0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_init.ram/SP.WIDE_PRIM18.SP/REGCLKAL
Logical resource:
graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_XSG_core_config/graspx8_eth_2ch_36p18_x0/subsystem3_919ba2a61f/simple_bram_vacc8_b26b51f34f/delay_bram_5afb15e97f/single_port_ram/comp0.core_instance0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_init.ram/SP.WIDE_PRIM18.SP/REGCLKAL
Location pin: RAMB36_X0Y4.REGCLKARDRCLKL
Clock network: adc0_clk
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_sys_clk_n = PERIOD TIMEGRP "sys_clk_n" 100 MHz HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide
(UG612).
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 component switching limit errors)
Minimum period is 8.332ns.
--------------------------------------------------------------------------------
Component Switching Limit Checks: TS_sys_clk_n = PERIOD TIMEGRP "sys_clk_n" 100 MHz HIGH 50%;
--------------------------------------------------------------------------------
Slack: 1.668ns (period - min period limit)
Period: 10.000ns
Min period limit: 8.332ns (120.019MHz) (Tdcmpc)
Physical resource: infrastructure_inst/infrastructure_inst/SYS_CLK_DCM/CLKIN
Logical resource: infrastructure_inst/infrastructure_inst/SYS_CLK_DCM/CLKIN
Location pin: DCM_ADV_X0Y11.CLKIN
Clock network: infrastructure_inst/infrastructure_inst/sys_clk_int
--------------------------------------------------------------------------------
Slack: 1.668ns (period - min period limit)
Period: 10.000ns
Min period limit: 8.332ns (120.019MHz) (Tdcmpco)
Physical resource: infrastructure_inst/infrastructure_inst/SYS_CLK_DCM/CLK0
Logical resource: infrastructure_inst/infrastructure_inst/SYS_CLK_DCM/CLK0
Location pin: DCM_ADV_X0Y11.CLK0
Clock network: infrastructure_inst/infrastructure_inst/sys_clk_dcm
--------------------------------------------------------------------------------
Slack: 4.666ns (period - (min low pulse limit / (low pulse / period)))
Period: 10.000ns
Low pulse: 5.000ns
Low pulse limit: 2.667ns (Tdcmpw_CLKIN_100_150)
Physical resource: infrastructure_inst/infrastructure_inst/SYS_CLK_DCM/CLKIN
Logical resource: infrastructure_inst/infrastructure_inst/SYS_CLK_DCM/CLKIN
Location pin: DCM_ADV_X0Y11.CLKIN
Clock network: infrastructure_inst/infrastructure_inst/sys_clk_int
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_dly_clk_n = PERIOD TIMEGRP "dly_clk_n" 200 MHz HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide
(UG612).
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 component switching limit errors)
Minimum period is 2.221ns.
--------------------------------------------------------------------------------
Component Switching Limit Checks: TS_dly_clk_n = PERIOD TIMEGRP "dly_clk_n" 200 MHz HIGH 50%;
--------------------------------------------------------------------------------
Slack: 2.779ns (period - min period limit)
Period: 5.000ns
Min period limit: 2.221ns (450.248MHz) (Tbgper_I)
Physical resource: infrastructure_inst/infrastructure_inst/bufg_inst/I0
Logical resource: infrastructure_inst/infrastructure_inst/bufg_inst/I0
Location pin: BUFGCTRL_X0Y28.I0
Clock network: infrastructure_inst/infrastructure_inst/dly_clk_int
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_mgt_clk_0 = PERIOD TIMEGRP "mgt_clk_0" 156.25 MHz HIGH
50%;
For more information, see Period Analysis in the Timing Closure User Guide
(UG612).
72736 paths analyzed, 8343 endpoints analyzed, 202 failing endpoints
202 timing errors detected. (0 setup errors, 202 hold errors, 0 component
switching limit errors)
Minimum period is 6.306ns.
--------------------------------------------------------------------------------
Slack (setup path): 0.094ns (requirement - (data path - clock path skew +
uncertainty))
Source:
xaui_phy_0/xaui_phy_0/use_xilinx_xaui.xaui_inst/BU2/U0/G_RECEIVER.receiver/recoder/rxd_out_32
(FF)
Destination:
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/ten_gig_eth_mac_inst/mac_rx_inst/hardcrc.rx_crc_reg_0
(FF)
Requirement: 6.400ns
Data Path Delay: 6.232ns (Levels of Logic = 5)
Clock Path Skew: 0.000ns
Source Clock: mgt_clk_0 rising at 0.000ns
Destination Clock: mgt_clk_0 rising at 6.400ns
Clock Uncertainty: 0.074ns
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.130ns
Phase Error (PE): 0.000ns
Maximum Data Path: xaui_phy_0/xaui_phy_0/use_xilinx_xaui.xaui_inst/BU2/U0/G_RECEIVER.receiver/recoder/rxd_out_32 to graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/ten_gig_eth_mac_inst/mac_rx_inst/hardcrc.rx_crc_reg_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X88Y79.CQ Tcko 0.471 xgmii0_xgmii_rxd<32>
xaui_phy_0/xaui_phy_0/use_xilinx_xaui.xaui_inst/BU2/U0/G_RECEIVER.receiver/recoder/rxd_out_32
SLICE_X78Y7.A4 net (fanout=2) e 3.439 xgmii0_xgmii_rxd<32>
SLICE_X78Y7.A Tilo 0.094
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/ten_gig_eth_mac_inst/mac_rx_inst/rx_data_pre_crc_reg<35>
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/ten_gig_eth_mac_inst/mac_rx_inst/xgmii_rxd_align<32>1
SLICE_X81Y7.C2 net (fanout=4) e 0.748
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/ten_gig_eth_mac_inst/mac_rx_inst/xgmii_rxd_align<32>
SLICE_X81Y7.C Tilo 0.094
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/tge_tx_inst/packet_ctrl_size<11>
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/ten_gig_eth_mac_inst/mac_rx_inst/hardcrc_rx_crc_reg_mux0000<0>44_SW0
SLICE_X81Y7.B6 net (fanout=1) e 0.430
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/N267
SLICE_X81Y7.B Tilo 0.094
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/tge_tx_inst/packet_ctrl_size<11>
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/ten_gig_eth_mac_inst/mac_rx_inst/hardcrc_rx_crc_reg_mux0000<0>44
SLICE_X82Y6.B6 net (fanout=1) e 0.303
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/ten_gig_eth_mac_inst/mac_rx_inst/hardcrc_rx_crc_reg_mux0000<0>44
SLICE_X82Y6.B Tilo 0.094
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/ten_gig_eth_mac_inst/mac_rx_inst/hardcrc.rx_crc_reg_1
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/ten_gig_eth_mac_inst/mac_rx_inst/hardcrc_rx_crc_reg_mux0000<0>109_SW0
SLICE_X82Y6.A6 net (fanout=1) e 0.439
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/N197
SLICE_X82Y6.CLK Tas 0.026
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/ten_gig_eth_mac_inst/mac_rx_inst/hardcrc.rx_crc_reg_1
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/ten_gig_eth_mac_inst/mac_rx_inst/hardcrc_rx_crc_reg_mux0000<0>109
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/ten_gig_eth_mac_inst/mac_rx_inst/hardcrc.rx_crc_reg_0
-------------------------------------------------
---------------------------
Total 6.232ns (0.873ns logic, 5.359ns
route)
(14.0% logic, 86.0%
route)
--------------------------------------------------------------------------------
Slack (setup path): 0.133ns (requirement - (data path - clock path skew +
uncertainty))
Source:
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/ten_gig_eth_mac_inst/mac_rx_inst/hardcrc.rx_crc_reg_12
(FF)
Destination:
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/tge_rx_inst/mac_rx_bad_frame_z
(FF)
Requirement: 6.400ns
Data Path Delay: 6.193ns (Levels of Logic = 2)
Clock Path Skew: 0.000ns
Source Clock: mgt_clk_0 rising at 0.000ns
Destination Clock: mgt_clk_0 rising at 6.400ns
Clock Uncertainty: 0.074ns
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.130ns
Phase Error (PE): 0.000ns
Maximum Data Path: graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/ten_gig_eth_mac_inst/mac_rx_inst/hardcrc.rx_crc_reg_12 to graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/tge_rx_inst/mac_rx_bad_frame_z
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X82Y2.AQ Tcko 0.450
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/ten_gig_eth_mac_inst/mac_rx_inst/hardcrc.rx_crc_reg_13
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/ten_gig_eth_mac_inst/mac_rx_inst/hardcrc.rx_crc_reg_12
SLICE_X91Y12.A1 net (fanout=2) e 1.749
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/ten_gig_eth_mac_inst/mac_rx_inst/hardcrc.rx_crc_reg_12
SLICE_X91Y12.COUT Topcya 0.509
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/ten_gig_eth_mac_inst/mac_rx_inst/Mcompar_rx_good_frame_cmp_eq0000_cy<7>
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/ten_gig_eth_mac_inst/mac_rx_inst/Mcompar_rx_good_frame_cmp_eq0000_lut<4>
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/ten_gig_eth_mac_inst/mac_rx_inst/Mcompar_rx_good_frame_cmp_eq0000_cy<7>
SLICE_X91Y13.CIN net (fanout=1) e 0.000
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/ten_gig_eth_mac_inst/mac_rx_inst/Mcompar_rx_good_frame_cmp_eq0000_cy<7>
SLICE_X91Y13.CMUX Tcinc 0.352
xaui_phy_0/xaui_phy_0/use_xilinx_xaui.xaui_inst/BU2/U0/G_TRANSMITTER.transmitter/G_FILTER_HIGH[7].filter/txd_out<4>
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/ten_gig_eth_mac_inst/mac_rx_inst/Mcompar_rx_good_frame_cmp_eq0000_cy<10>
SLICE_X50Y29.SR net (fanout=2) e 2.586
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/ten_gig_eth_mac_inst/mac_rx_inst/rx_good_frame_cmp_eq0000
SLICE_X50Y29.CLK Tsrck 0.547
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/tge_rx_inst/mac_rx_bad_frame_z
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/tge_rx_inst/mac_rx_bad_frame_z
-------------------------------------------------
---------------------------
Total 6.193ns (1.858ns logic, 4.335ns
route)
(30.0% logic, 70.0%
route)
--------------------------------------------------------------------------------
Slack (setup path): 0.146ns (requirement - (data path - clock path skew +
uncertainty))
Source:
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/ten_gig_eth_mac_inst/mac_rx_inst/hardcrc.rx_crc_reg_15
(FF)
Destination:
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/tge_rx_inst/mac_rx_bad_frame_z
(FF)
Requirement: 6.400ns
Data Path Delay: 6.180ns (Levels of Logic = 2)
Clock Path Skew: 0.000ns
Source Clock: mgt_clk_0 rising at 0.000ns
Destination Clock: mgt_clk_0 rising at 6.400ns
Clock Uncertainty: 0.074ns
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.130ns
Phase Error (PE): 0.000ns
Maximum Data Path: graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/ten_gig_eth_mac_inst/mac_rx_inst/hardcrc.rx_crc_reg_15 to graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/tge_rx_inst/mac_rx_bad_frame_z
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X83Y2.CQ Tcko 0.450
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/ten_gig_eth_mac_inst/mac_rx_inst/hardcrc.rx_crc_reg_15
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/ten_gig_eth_mac_inst/mac_rx_inst/hardcrc.rx_crc_reg_15
SLICE_X91Y12.B1 net (fanout=2) e 1.744
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/ten_gig_eth_mac_inst/mac_rx_inst/hardcrc.rx_crc_reg_15
SLICE_X91Y12.COUT Topcyb 0.501
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/ten_gig_eth_mac_inst/mac_rx_inst/Mcompar_rx_good_frame_cmp_eq0000_cy<7>
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/ten_gig_eth_mac_inst/mac_rx_inst/Mcompar_rx_good_frame_cmp_eq0000_lut<5>
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/ten_gig_eth_mac_inst/mac_rx_inst/Mcompar_rx_good_frame_cmp_eq0000_cy<7>
SLICE_X91Y13.CIN net (fanout=1) e 0.000
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/ten_gig_eth_mac_inst/mac_rx_inst/Mcompar_rx_good_frame_cmp_eq0000_cy<7>
SLICE_X91Y13.CMUX Tcinc 0.352
xaui_phy_0/xaui_phy_0/use_xilinx_xaui.xaui_inst/BU2/U0/G_TRANSMITTER.transmitter/G_FILTER_HIGH[7].filter/txd_out<4>
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/ten_gig_eth_mac_inst/mac_rx_inst/Mcompar_rx_good_frame_cmp_eq0000_cy<10>
SLICE_X50Y29.SR net (fanout=2) e 2.586
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/ten_gig_eth_mac_inst/mac_rx_inst/rx_good_frame_cmp_eq0000
SLICE_X50Y29.CLK Tsrck 0.547
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/tge_rx_inst/mac_rx_bad_frame_z
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/tge_rx_inst/mac_rx_bad_frame_z
-------------------------------------------------
---------------------------
Total 6.180ns (1.850ns logic, 4.330ns
route)
(29.9% logic, 70.1%
route)
--------------------------------------------------------------------------------
Hold Paths: TS_mgt_clk_0 = PERIOD TIMEGRP "mgt_clk_0" 156.25 MHz HIGH 50%;
--------------------------------------------------------------------------------
Slack (hold path): -1.079ns (requirement - (clock path skew + uncertainty
- data path))
Source:
xaui_phy_0/xaui_phy_0/use_xilinx_xaui.xaui_inst/BU2/U0/G_TRANSMITTER.transmitter/recoder/txd_out_47
(FF)
Destination:
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_0/transceiver_0/gtp_dual_i
(HSIO)
Requirement: 0.000ns
Data Path Delay: -1.079ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: mgt_clk_0 rising at 6.400ns
Destination Clock: mgt_clk_0 rising at 6.400ns
Clock Uncertainty: 0.000ns
Minimum Data Path: xaui_phy_0/xaui_phy_0/use_xilinx_xaui.xaui_inst/BU2/U0/G_TRANSMITTER.transmitter/recoder/txd_out_47 to xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_0/transceiver_0/gtp_dual_i
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
----------------------------------------------------- -------------------
SLICE_X90Y23.DQ Tcko 0.414
xaui_sys0_mgt_tx_data<31>
xaui_phy_0/xaui_phy_0/use_xilinx_xaui.xaui_inst/BU2/U0/G_TRANSMITTER.transmitter/recoder/txd_out_47
GTP_DUAL_X0Y1.TXDATA115 net (fanout=1) e 0.434
xaui_sys0_mgt_tx_data<31>
GTP_DUAL_X0Y1.TXUSRCLK21 Tgtpckc_TXDATA(-Th) 1.927
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_0/transceiver_0/gtp_dual_i
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_0/transceiver_0/gtp_dual_i
-----------------------------------------------------
---------------------------
Total -1.079ns (-1.513ns logic,
0.434ns route)
(140.2% logic,
-40.2% route)
--------------------------------------------------------------------------------
Slack (hold path): -1.079ns (requirement - (clock path skew + uncertainty
- data path))
Source:
xaui_phy_0/xaui_phy_0/use_xilinx_xaui.xaui_inst/BU2/U0/G_TRANSMITTER.transmitter/recoder/txd_out_43
(FF)
Destination:
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_0/transceiver_0/gtp_dual_i
(HSIO)
Requirement: 0.000ns
Data Path Delay: -1.079ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: mgt_clk_0 rising at 6.400ns
Destination Clock: mgt_clk_0 rising at 6.400ns
Clock Uncertainty: 0.000ns
Minimum Data Path: xaui_phy_0/xaui_phy_0/use_xilinx_xaui.xaui_inst/BU2/U0/G_TRANSMITTER.transmitter/recoder/txd_out_43 to xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_0/transceiver_0/gtp_dual_i
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
----------------------------------------------------- -------------------
SLICE_X90Y22.DQ Tcko 0.414
xaui_sys0_mgt_tx_data<27>
xaui_phy_0/xaui_phy_0/use_xilinx_xaui.xaui_inst/BU2/U0/G_TRANSMITTER.transmitter/recoder/txd_out_43
GTP_DUAL_X0Y1.TXDATA111 net (fanout=1) e 0.434
xaui_sys0_mgt_tx_data<27>
GTP_DUAL_X0Y1.TXUSRCLK21 Tgtpckc_TXDATA(-Th) 1.927
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_0/transceiver_0/gtp_dual_i
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_0/transceiver_0/gtp_dual_i
-----------------------------------------------------
---------------------------
Total -1.079ns (-1.513ns logic,
0.434ns route)
(140.2% logic,
-40.2% route)
--------------------------------------------------------------------------------
Slack (hold path): -1.074ns (requirement - (clock path skew + uncertainty
- data path))
Source:
xaui_phy_0/xaui_phy_0/use_xilinx_xaui.xaui_inst/BU2/U0/G_TRANSMITTER.transmitter/recoder/txd_out_16
(FF)
Destination:
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_0/transceiver_1/gtp_dual_i
(HSIO)
Requirement: 0.000ns
Data Path Delay: -1.074ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: mgt_clk_0 rising at 6.400ns
Destination Clock: mgt_clk_0 rising at 6.400ns
Clock Uncertainty: 0.000ns
Minimum Data Path: xaui_phy_0/xaui_phy_0/use_xilinx_xaui.xaui_inst/BU2/U0/G_TRANSMITTER.transmitter/recoder/txd_out_16 to xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_0/transceiver_1/gtp_dual_i
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
----------------------------------------------------- -------------------
SLICE_X90Y19.AQ Tcko 0.414
xaui_sys0_mgt_tx_data<35>
xaui_phy_0/xaui_phy_0/use_xilinx_xaui.xaui_inst/BU2/U0/G_TRANSMITTER.transmitter/recoder/txd_out_16
GTP_DUAL_X0Y0.TXDATA00 net (fanout=1) e 0.439
xaui_sys0_mgt_tx_data<32>
GTP_DUAL_X0Y0.TXUSRCLK20 Tgtpckc_TXDATA(-Th) 1.927
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_0/transceiver_1/gtp_dual_i
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_0/transceiver_1/gtp_dual_i
-----------------------------------------------------
---------------------------
Total -1.074ns (-1.513ns logic,
0.439ns route)
(140.9% logic,
-40.9% route)
--------------------------------------------------------------------------------
Component Switching Limit Checks: TS_mgt_clk_0 = PERIOD TIMEGRP "mgt_clk_0" 156.25 MHz HIGH 50%;
--------------------------------------------------------------------------------
Slack: 4.178ns (period - min period limit)
Period: 6.400ns
Min period limit: 2.222ns (450.045MHz) (Trper_CLKB)
Physical resource:
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/tge_tx_inst/arp_cache_inst/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_init.ram/TRUE_DP.SINGLE_PRIM18.TDP/CLKBL
Logical resource:
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/tge_tx_inst/arp_cache_inst/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_init.ram/TRUE_DP.SINGLE_PRIM18.TDP/CLKBL
Location pin: RAMB36_X4Y5.CLKBWRCLKL
Clock network: mgt_clk_0
--------------------------------------------------------------------------------
Slack: 4.178ns (period - min period limit)
Period: 6.400ns
Min period limit: 2.222ns (450.045MHz) (Trper_CLKB)
Physical resource:
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/tge_tx_inst/arp_cache_inst/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_init.ram/TRUE_DP.SINGLE_PRIM18.TDP/REGCLKBL
Logical resource:
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/tge_tx_inst/arp_cache_inst/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_init.ram/TRUE_DP.SINGLE_PRIM18.TDP/REGCLKBL
Location pin: RAMB36_X4Y5.REGCLKBWRRCLKL
Clock network: mgt_clk_0
--------------------------------------------------------------------------------
Slack: 4.178ns (period - min period limit)
Period: 6.400ns
Min period limit: 2.222ns (450.045MHz) (Trper_CLKB)
Physical resource:
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/tge_tx_inst/tx_packet_fifo_inst/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP/CLKBL
Logical resource:
graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/graspx8_eth_2ch_36p18_10gbe_ten_Gbe_v2/tge_tx_inst/tx_packet_fifo_inst/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP/CLKBL
Location pin: RAMB36_X3Y4.CLKBWRCLKL
Clock network: mgt_clk_0
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_mgt_clk_mult_2_b = PERIOD TIMEGRP "mgt_clk_mult_2_b"
156.25 MHz HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide
(UG612).
18 paths analyzed, 18 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors, 0 component
switching limit errors)
Minimum period is 2.448ns.
--------------------------------------------------------------------------------
Slack (setup path): 3.952ns (requirement - (data path - clock path skew +
uncertainty))
Source:
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_1/transceiver_0/gtp_dual_i
(HSIO)
Destination:
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_1/transceiver_1/gtp_dual_i
(HSIO)
Requirement: 6.400ns
Data Path Delay: 2.381ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock:
xaui_infrastructure_inst/xaui_infrastructure_inst/mgt_clk_mult_2_b rising at
0.000ns
Destination Clock:
xaui_infrastructure_inst/xaui_infrastructure_inst/mgt_clk_mult_2_b rising at
6.400ns
Clock Uncertainty: 0.067ns
Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.114ns
Phase Error (PE): 0.000ns
Maximum Data Path: xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_1/transceiver_0/gtp_dual_i to xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_1/transceiver_1/gtp_dual_i
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------------ -------------------
GTP_DUAL_X0Y3.RXCHBONDO02 Tgtpcko_CHBONDO 1.762
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_1/transceiver_0/gtp_dual_i
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_1/transceiver_0/gtp_dual_i
GTP_DUAL_X0Y2.RXCHBONDI12 net (fanout=3) e 1.548
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_1/chbond_1_hop<2>
GTP_DUAL_X0Y2.RXUSRCLK1 Tgtpcck_CHBONDI -0.929
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_1/transceiver_1/gtp_dual_i
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_1/transceiver_1/gtp_dual_i
------------------------------------------------------
---------------------------
Total 2.381ns (0.833ns logic,
1.548ns route)
(35.0% logic,
65.0% route)
--------------------------------------------------------------------------------
Slack (setup path): 3.952ns (requirement - (data path - clock path skew +
uncertainty))
Source:
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_0/transceiver_0/gtp_dual_i
(HSIO)
Destination:
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_0/transceiver_1/gtp_dual_i
(HSIO)
Requirement: 6.400ns
Data Path Delay: 2.381ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock:
xaui_infrastructure_inst/xaui_infrastructure_inst/mgt_clk_mult_2_b rising at
0.000ns
Destination Clock:
xaui_infrastructure_inst/xaui_infrastructure_inst/mgt_clk_mult_2_b rising at
6.400ns
Clock Uncertainty: 0.067ns
Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.114ns
Phase Error (PE): 0.000ns
Maximum Data Path: xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_0/transceiver_0/gtp_dual_i to xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_0/transceiver_1/gtp_dual_i
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------------ -------------------
GTP_DUAL_X0Y1.RXCHBONDO02 Tgtpcko_CHBONDO 1.762
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_0/transceiver_0/gtp_dual_i
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_0/transceiver_0/gtp_dual_i
GTP_DUAL_X0Y0.RXCHBONDI12 net (fanout=3) e 1.548
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_0/chbond_1_hop<2>
GTP_DUAL_X0Y0.RXUSRCLK1 Tgtpcck_CHBONDI -0.929
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_0/transceiver_1/gtp_dual_i
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_0/transceiver_1/gtp_dual_i
------------------------------------------------------
---------------------------
Total 2.381ns (0.833ns logic,
1.548ns route)
(35.0% logic,
65.0% route)
--------------------------------------------------------------------------------
Slack (setup path): 4.061ns (requirement - (data path - clock path skew +
uncertainty))
Source:
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_0/transceiver_0/gtp_dual_i
(HSIO)
Destination:
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_0/transceiver_1/gtp_dual_i
(HSIO)
Requirement: 6.400ns
Data Path Delay: 2.272ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock:
xaui_infrastructure_inst/xaui_infrastructure_inst/mgt_clk_mult_2_b rising at
0.000ns
Destination Clock:
xaui_infrastructure_inst/xaui_infrastructure_inst/mgt_clk_mult_2_b rising at
6.400ns
Clock Uncertainty: 0.067ns
Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.114ns
Phase Error (PE): 0.000ns
Maximum Data Path: xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_0/transceiver_0/gtp_dual_i to xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_0/transceiver_1/gtp_dual_i
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------------ -------------------
GTP_DUAL_X0Y1.RXCHBONDO00 Tgtpcko_CHBONDO 1.762
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_0/transceiver_0/gtp_dual_i
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_0/transceiver_0/gtp_dual_i
GTP_DUAL_X0Y0.RXCHBONDI10 net (fanout=3) e 1.439
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_0/chbond_1_hop<0>
GTP_DUAL_X0Y0.RXUSRCLK1 Tgtpcck_CHBONDI -0.929
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_0/transceiver_1/gtp_dual_i
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_0/transceiver_1/gtp_dual_i
------------------------------------------------------
---------------------------
Total 2.272ns (0.833ns logic,
1.439ns route)
(36.7% logic,
63.3% route)
--------------------------------------------------------------------------------
Hold Paths: TS_mgt_clk_mult_2_b = PERIOD TIMEGRP "mgt_clk_mult_2_b" 156.25 MHz HIGH 50%;
--------------------------------------------------------------------------------
Slack (hold path): 0.267ns (requirement - (clock path skew + uncertainty
- data path))
Source:
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_0/transceiver_0/gtp_dual_i
(HSIO)
Destination:
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_0/transceiver_0/gtp_dual_i
(HSIO)
Requirement: 0.000ns
Data Path Delay: 0.267ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock:
xaui_infrastructure_inst/xaui_infrastructure_inst/mgt_clk_mult_2_b rising at
6.400ns
Destination Clock:
xaui_infrastructure_inst/xaui_infrastructure_inst/mgt_clk_mult_2_b rising at
6.400ns
Clock Uncertainty: 0.000ns
Minimum Data Path: xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_0/transceiver_0/gtp_dual_i to xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_0/transceiver_0/gtp_dual_i
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------------ -------------------
GTP_DUAL_X0Y1.RXCHBONDO00 Tgtpcko_CHBONDO 1.621
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_0/transceiver_0/gtp_dual_i
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_0/transceiver_0/gtp_dual_i
GTP_DUAL_X0Y1.RXCHBONDI10 net (fanout=3) e 0.471
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_0/chbond_1_hop<0>
GTP_DUAL_X0Y1.RXUSRCLK1 Tgtpckc_CHBONDI(-Th) 1.825
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_0/transceiver_0/gtp_dual_i
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_0/transceiver_0/gtp_dual_i
------------------------------------------------------
---------------------------
Total 0.267ns (-0.204ns logic,
0.471ns route)
(-76.4% logic,
176.4% route)
--------------------------------------------------------------------------------
Slack (hold path): 0.267ns (requirement - (clock path skew + uncertainty
- data path))
Source:
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_1/transceiver_0/gtp_dual_i
(HSIO)
Destination:
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_1/transceiver_0/gtp_dual_i
(HSIO)
Requirement: 0.000ns
Data Path Delay: 0.267ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock:
xaui_infrastructure_inst/xaui_infrastructure_inst/mgt_clk_mult_2_b rising at
6.400ns
Destination Clock:
xaui_infrastructure_inst/xaui_infrastructure_inst/mgt_clk_mult_2_b rising at
6.400ns
Clock Uncertainty: 0.000ns
Minimum Data Path: xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_1/transceiver_0/gtp_dual_i to xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_1/transceiver_0/gtp_dual_i
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------------ -------------------
GTP_DUAL_X0Y3.RXCHBONDO00 Tgtpcko_CHBONDO 1.621
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_1/transceiver_0/gtp_dual_i
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_1/transceiver_0/gtp_dual_i
GTP_DUAL_X0Y3.RXCHBONDI10 net (fanout=3) e 0.471
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_1/chbond_1_hop<0>
GTP_DUAL_X0Y3.RXUSRCLK1 Tgtpckc_CHBONDI(-Th) 1.825
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_1/transceiver_0/gtp_dual_i
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_1/transceiver_0/gtp_dual_i
------------------------------------------------------
---------------------------
Total 0.267ns (-0.204ns logic,
0.471ns route)
(-76.4% logic,
176.4% route)
--------------------------------------------------------------------------------
Slack (hold path): 0.269ns (requirement - (clock path skew + uncertainty
- data path))
Source:
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_1/transceiver_0/gtp_dual_i
(HSIO)
Destination:
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_1/transceiver_0/gtp_dual_i
(HSIO)
Requirement: 0.000ns
Data Path Delay: 0.269ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock:
xaui_infrastructure_inst/xaui_infrastructure_inst/mgt_clk_mult_2_b rising at
6.400ns
Destination Clock:
xaui_infrastructure_inst/xaui_infrastructure_inst/mgt_clk_mult_2_b rising at
6.400ns
Clock Uncertainty: 0.000ns
Minimum Data Path: xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_1/transceiver_0/gtp_dual_i to xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_1/transceiver_0/gtp_dual_i
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------------ -------------------
GTP_DUAL_X0Y3.RXCHBONDO01 Tgtpcko_CHBONDO 1.621
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_1/transceiver_0/gtp_dual_i
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_1/transceiver_0/gtp_dual_i
GTP_DUAL_X0Y3.RXCHBONDI11 net (fanout=3) e 0.473
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_1/chbond_1_hop<1>
GTP_DUAL_X0Y3.RXUSRCLK1 Tgtpckc_CHBONDI(-Th) 1.825
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_1/transceiver_0/gtp_dual_i
xaui_infrastructure_inst/xaui_infrastructure_inst/transceiver_bank_1/transceiver_0/gtp_dual_i
------------------------------------------------------
---------------------------
Total 0.269ns (-0.204ns logic,
0.473ns route)
(-75.8% logic,
175.8% route)
--------------------------------------------------------------------------------
Derived Constraint Report
Derived Constraints for
graspx8_eth_2ch_36p18_adc/graspx8_eth_2ch_36p18_adc/adc_clk_buf
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period |
Timing Errors | Paths Analyzed |
| Constraint | Requirement
|-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative |
Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|graspx8_eth_2ch_36p18_adc/grasp| 5.000ns| 3.600ns| 4.974ns|
0| 83| 0| 850490|
|x8_eth_2ch_36p18_adc/adc_clk_bu| | | |
| | | |
|f | | | |
| | | |
| graspx8_eth_2ch_36p18_adc/gras| 5.000ns| 4.974ns| N/A|
83| 0| 850490| 0|
| px8_eth_2ch_36p18_adc/adc_clk_| | | |
| | | |
| dcm | | | |
| | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
2 constraints not met.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Clock to Setup on destination clock adc0clk_n
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
adc0clk_n | 4.974| | | |
adc0clk_p | 4.974| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock adc0clk_p
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
adc0clk_n | 4.974| | | |
adc0clk_p | 4.974| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock mgt_ref_clk_bottom_n
--------------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
--------------------+---------+---------+---------+---------+
mgt_ref_clk_bottom_n| 6.306| | | |
mgt_ref_clk_bottom_p| 6.306| | | |
--------------------+---------+---------+---------+---------+
Clock to Setup on destination clock mgt_ref_clk_bottom_p
--------------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
--------------------+---------+---------+---------+---------+
mgt_ref_clk_bottom_n| 6.306| | | |
mgt_ref_clk_bottom_p| 6.306| | | |
--------------------+---------+---------+---------+---------+
Timing summary:
---------------
Timing errors: 285 Score: 88533 (Setup/Max: 0, Hold: 88533)
Constraints cover 923244 paths, 1 nets, and 134062 connections
Design statistics:
Minimum period: 8.332ns{1} (Maximum frequency: 120.019MHz)
Maximum net delay: 1.758ns
------------------------------------Footnotes-----------------------------------
1) The minimum period statistic assumes all single cycle delays.
Analysis completed Mon Feb 18 20:48:01 2019
--------------------------------------------------------------------------------
Timing Analyzer Settings:
-------------------------
Timing Analyzer Settings
analysis_name "Analysis 1"
analysis_type "design timing constraints"
analysis_speed -1
analysis_voltage 0.950000
analysis_temperature 85.000000
analyze_unconstrained_paths false
analzye_component_switching_limits true
report_datasheet true
report_timegroups false
report_constraints_interaction false
paths_per_constraint 3
Peak Memory Usage: 1886 MB
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