Folks
I have been using the ROACH2 for a few years now, and using matlab r2012b and
ISE14.6. It has always worked for me.
After moving the build system to another computer, it is now broken. I can
still compile FPGAs to make a bit file. But when simulating
with Xilinx math blocks I get:
We have been using a ROACH for several years, and I have found the CASPER
mailing lists to be useful, and the community helpful. Not sure what being a
"member" of Casper is. We do not pay any fee. We just joined the mailing list.
There are ROACH conferences once a year. I have not gone, but
You also have to enable larger packet sizes on the enet card receiving the
packets. There are some linux commands to do this, but I dont know them. ask
your IT guy.
Tim
From: Mike Movius [mi...@reutech.co.za]
Sent: Tuesday, April 18, 2017 4:20 AM
To:
Oliver
The roach1 yellow block will not work on roach2 because it uses the older
style PLLs not found on the V6 chip of R2. I made a new yellow block for mkid
4x and it works fine. It is here:
https://github.com/argonnexraydetector/RoachFirmPy/tree/master/ANLYellowBlocks
The iSE project to
ing xilinx FFT blocks. A reorder block would be necessary, and I am not
sure of all the details. it would be interesting if someone were to try this.
Tim
____
From: Madden, Timothy J.
Sent: Wednesday, December 09, 2015 8:02 AM
To: Andrew Martens
Cc: casper@lists.be
: https://github.com/ska-sa/mlib_devel.git
I git'ed this about a year ago, so it is not the newest stuff probably.
Tim
From: Andrew Martens [and...@ska.ac.za]
Sent: Wednesday, December 09, 2015 1:51 AM
To: Madden, Timothy J.
Cc: casper@lists.berkeley.edu
Subject
I am using a ROACH2, and doing 512 length FFTs.
I am seeing some wierd FFT problems as well. I found that if I had the FFT/PFB
in the design as green blocks, other logic would break it. Black boxing the FFT
helps, as it makes it work more or less.
Even after black boxing the FFT/PFB I still
Michael
It may be that your FFT is working fine. Are you using a window before the
FFT? The window can put zeros at odd bins if the input signal is just right.
You may try taking away the pfb block, and inputting random noise into the FFT
without any windowing.
if the input has samples that
I have a roach2 and am trying to use a green fft block. I make the model in
Matlab, then run casper_xps.
It runs for about 5-10min, and gives following error
XSG generation complete.
#
## Copying base system ##
#
Copying base package from:
Wow- what a quick response! Thanks Matt
Tim Madden
From: mstrade...@gmail.com [mstrade...@gmail.com] on behalf of Matt Strader
[mstra...@physics.ucsb.edu]
Sent: Friday, August 21, 2015 2:57 PM
To: Madden, Timothy J.
Cc: casper@lists.berkeley.edu
Subject: Re
Folks
In developing firmware for the ROACH2 mkid adc, I was checking the pins that
get assigned to the ADC, ZDOK interface.
I think there are two pin out errors in the file:
hw_routes_roach2rev1.mat
I am looking at the included tables for zdok1_p, and so far have found two
errors.
One pin is
Wow-
Thanks for telling me! That would be a mess.
Tim Madden
From: Primiani, Rurik [rprimi...@cfa.harvard.edu]
Sent: Wednesday, April 29, 2015 10:02 AM
To: Madden, Timothy J.
Cc: casper@lists.berkeley.edu
Subject: Re: [casper] ROACH2 FPGA Pinout Problems
Hi Tim
Folks
I generated a new yellow block for the mkid dac 4x. The one in my xps_library
would not compile, and seemed to be designed for roach1, V5 chips. The existing
block uses DCM instead of MMCM for clocking, which is illegal on Virtex 6. The
new module uses MMCM.
I can compile the thing in
To: Madden, Timothy J.
Cc: Jack Hickish; casper@lists.berkeley.edu
Subject: Re: [casper] Regarding dram: Moving from ROACH1 to ROACH2
Hi Tim,
Could you send out a link to the github page when you do post it?
Thanks,
Brad Dober
Ph.D. Candidate
Department of Physics and Astronomy
University
I will get on github soon. Argonne and Nist are sharing stuff already.
T
From: Jack Hickish [jackhick...@gmail.com]
Sent: Thursday, April 16, 2015 10:08 AM
To: Madden, Timothy J.; casper@lists.berkeley.edu
Subject: Re: [casper] Regarding dram: Moving from ROACH1
Folks
After reverse engineering the dram on ROACH2 here is what one should know.
1. The dram on roach2 is different from roach1.
On roach1, the user can read and write 144 size words to the dram with the
buss set not to 288 bits.
On roach2, the data buss is always 288 bits, regardless of
I am trying to start telnetd on a roach2 booting from the local flash.
I added
telnetd
to /etc/rc.local
When I do a ps -a, no telnet is listed...
Also I cannot telnet to it.
I can ping the roach, as I set it up with
ifconfig eth0 192.168.0.68
I connect a linux box to the PPC ethernet, and I
Folks
I am trying to use a complex fft (the green FFT block) for a spectrum analyzer
application.
I would like to use a 512 point FFT to compute on read time data. I need the
FFT to compute in less than 512 samples. I am using 4 taps in the input, and
running the FPGA at 128MHz. In this
I appreciate your response Dan.
Tim
From: dan.werthi...@gmail.com [dan.werthi...@gmail.com] on behalf of Dan
Werthimer [d...@ssl.berkeley.edu]
Sent: Friday, May 02, 2014 11:26 AM
To: Madden, Timothy J.
Cc: casper@lists.berkeley.edu
Subject: Re: [casper] FFT
...@ssl.berkeley.edu
Cc: Madden, Timothy J. tmad...@aps.anl.gov,
casper@lists.berkeley.edu casper@lists.berkeley.edu
Message-ID:
cacu45xb6mdugm2zzan-9vk_d9qtfrwimygpyo4er+sgwj+7...@mail.gmail.com
Content-Type: text/plain; charset=utf-8
Dear Tim,
You are aware that the CASPER FFTs
From: Jack Hickish [jackhick...@gmail.com]
Sent: Friday, May 02, 2014 2:15 PM
To: Madden, Timothy J.
Cc: casper@lists.berkeley.edu
Subject: Re: [casper] FFT compute time
Hi Tim,
Also, if we supply ONE and only ONE sync pulse, should the fft block compute
indefinately? My simulink seems
: Jack Hickish [jackhick...@gmail.com]
Sent: Friday, May 02, 2014 4:35 PM
To: Madden, Timothy J.
Cc: casper@lists.berkeley.edu; apars...@astron.berkeley.edu
Subject: Re: [casper] casper Digest, Vol 78, Issue 2
Hi Tim,
On 2 May 2014 14:16, Madden, Timothy J. tmad...@aps.anl.gov wrote:
Aaron
I
]
Sent: Tuesday, April 08, 2014 4:04 PM
To: Madden, Timothy J.
Cc: casper@lists.berkeley.edu
Subject: Re: [casper] Problem writing to DRAM, ROACH 1
Hi,
I think I ran into similar issues, but I don't remember it being a consistent
failure for a given size, just that large transfers were somewhat
Folks
I have a few questions on the 1GB Ethernet block:
1. I assume the block connects to one of the CX4 ports on the ROACH 1 board. Is
this true?]
2. What is the data format on the CX4 port? Is it 8b/10b encoding?
3. Can I make a simple board to simply wire the CX4 pins into a cat5 connector
Thanks for the info.
Tim madden
From: Jack Hickish [jackhick...@gmail.com]
Sent: Monday, April 07, 2014 3:32 PM
To: Madden, Timothy J.
Cc: casper@lists.berkeley.edu
Subject: Re: [casper] One GB Ethernet block
Hey Tim,
Unfortunately, the one Gb Ethernet
I am using an fft block with 4 input streams, and 4 output streams.
I am trying to bit reverse the bin order in software. Because the FFT
coefficients are spewed from 4 outputs,
I am not sure of the order of the bins.
Example:
Say we have an fft block that is ALREADY performing bin
Folks
This is probably a question asked before, but I am simulating a model and
storing data to a shared BRAM.
Is there a way to view the contents of what was written to the BRAM during the
simulation?
Tim
Folks
How does the 10GB Ethernet work on the Roach boards? In most Xilinx
applications, the 10GB ethernet is generated by Xilinx IP blocks that have an
expensive license, on the order of $22k.
I have heard nothing about licensing fees for the 10GB Roach yellow block. Any
ideas on this?
Tim
Implementing a 10GB core is no easy task, considering you must sync. many
serial transceivers together. Cool. Good job.
Tim
From: Jason Manley [jman...@ska.ac.za]
Sent: Monday, February 10, 2014 9:09 AM
To: Madden, Timothy J.
Cc: Casper Lists
Subject: Re
Roach in a balloon
Just an idea if some engineer wants alot of work to do. One could put a whole
ROACH into a tiny circuit board these days using the new Xilinx ZYNQ chips. It
is a multi-chip module w/ high end Xilinx and 2 ARM cores. It would of course
require recompiling all the ROACH
Folks
I have a feature request for the PFB block, which should be easy to implement,
as it is only a matlab gui and script change, and not a hardware change.
The feature I request is to add one more field to the PFB block GUI telling
the bandwidth of the sinc function. The sinc bandwidth
I am using the complex fft block and get this error in a pop-up window:
Binary point output width does not make sense.
I have tried many different settings, and compared to other designs that are
supposed to compile.
Any ideas?
Tim
Folks
What is the part number of the PPC chip on the ROACH boards and where do we buy
them?
Seems better to buy now, and save rather than estimate our future purchases.
Tim
___
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