Re: [casper] VDIF Packetizer

While I haven't written it yet, I plan to write one capable of 400G by August 2024. Should be trivial to operate at 100G as well. I also plan to write one for VITA49.2. Matthew Schiller On Wed, Mar 6, 2024 at 3:46 PM Kaj Wiik wrote: > Hi Mayukh and all, > > I am developing a si

RE: [casper] PL data to PS DDR4 (AXI) {External}

handling data movement in embedded (software) systems for highest performance is well complicated…. And I probably shouldn’t talk much about it… I’m an FPGA engineer not a Kernel-level Embedded software engineer.. [AB72FAB9] Matthew Schiller ngVLA Digital Backend Lead NRAO mschi...@nrao.edu

RE: [casper] PL data to PS DDR4 (AXI) {External}

The right way to do what you describe is with the axi DMA block, but as you point out that has a software interface to configure the transfer. The main data would flow over an AXI4 “full” interface that supports burst transactions (but the Xilinx-provided DMA block already does that), and the

RE: [EXTERNAL] [casper] Advice for radio astronomy components student project {External} {External}

and a streaming I/Q output, which is basically what they give you out of the box from Analog Devices. Matthew Schiller ngVLA Digital Backend Lead NRAO   mschi...@nrao.edu 315-316-2032 -Original Message- From: casper@lists.berkeley.edu On Behalf Of Glen I Langston Sent: Thursday, August 17