Dear all,Very interested in this discussion and in both the VDIF and VITA49 packet formats for RFSoCs. Open-sourcing the blocks would definitely be welcome!Best,WaelSent from my iPhoneOn Mar 6, 2024, at 1:02 PM, Matthew Schiller wrote:While I haven't written it yet, I plan to write one capable
Hi all,
This might be of interest to some of you:
https://recruitment-recrutement.nrc-cnrc.gc.ca/job/Penticton-FPGA-Digital-Design-Engineer-BC/563313417/
Deadline in 5 days.
-- Wael
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From:
Date: Mon, 22 Feb 2021 at 02:57
Subject: [Everyone] EAS 2021 Special Session SS5 ‘Data-intensive radio
astronomy: bringing astrophysics to the exabyte era’
To:
Dear
atus buffer locking and/or data buffer access functions
> or it could just be due to the net threads being very busy processing
> packets.
>
> HTH,
> Dave
>
>
> On Dec 2, 2020, at 19:06, Wael Farah wrote:
>
> Hi Folks,
>
> Hope everyone's doing well.
>
>
Hi Folks,
Hope everyone's doing well.
I have an application I am trying to develop using hashpipe, and one of the
solutions might be using multiple instances of hashpipe on a single 40 GbE
interface.
When I tried running 2 instances of hashpipe I faced a problem. The data
rate reported by the
Hi Sean,
I might be wrong, but this error is due to the fact that the
casperfpga module that you are using (when you do "pip install" and/or the
master branch of the github repo) is meant to work on python 2.x.
What I can suggest doing is the following:
Uninstall casperfpga
>> pip uninstall
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