Hi Amit,
That's correct, assuming you are operating the adc in single input mode. It
also has a dual-input mode, where the first 8 outputs are one input, and
the second 8 are the other.
Don't forget that the input clock in single input (aka interleaved) mode
should be half the total sample rate.
Hello,
We are trying to sample a signal 100 MHz to 270 MHz with fpga running at
250MHz.
To downsample by 4, I simply take every 4th output of the 16 outputs
available from the yellow block of asiaa adc5g. We do have an
anti-aliasing filter for the desired 500MHz bw.
Is this correct or am I
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