Re: [casper] Compiler merging SRLs

To finish up this thread: I unchecked 'Use behavioral HDL' in all the delays and counters (which also wanted to combine in bad ways). At least I unchecked it in any instances that weren't already assigned to a pblock. At least once, I still saw a delay with behavioral HDL turned off combine with

Re: [casper] Compiler merging SRLs

Ha, I just read my email in the thread you linked. I guess turning off behavioural hdl isn't (ever? always?) the solution. On Mon, 25 Jan 2016 5:14 pm Jack Hickish wrote: > Hi Matt, > > You can resynthesize the "main" simulink netlist, but off the top of my > head I don't

Re: [casper] Compiler merging SRLs

Hi Matt, You can resynthesize the "main" simulink netlist, but off the top of my head I don't know the exact way to go about this. I think you can dig out the netlist from the sysgen build directory and use the resynth script on that. Perhaps Dave MacMahon (who I believe wrote that script) could

Re: [casper] Compiler merging SRLs

Turning off Behavioral HDL on the relevant instances *is* the correct answer. This should not impact resource utilization significantly. If it does, that means you have a large-fanout net, and can improve timing and utilization simultaneously by doing fanout in a couple steps (ie, one step

[casper] Compiler merging SRLs

Hello Casperites (especially Jack), I've run into the problem that Jack describes in this thread: http://www.mail-archive.com/casper%40lists.berkeley.edu/msg05581.html The compiler keeps wanting to combine unrelated LUTs on opposite sides of the Virtex 6, resulting in timing errors that are 90%

Re: [casper] Compiler merging SRLs -- Timing performance

Hi Everyone, Thanks all for the advice. Based on a few experiments so far (skip to 4 for what I think is a disappointinly simple solution, that I was too stupid to see in the XST manual) -- 1. My fabric utilisation isn't that high, although digging around planAhead there are some areas with high

[casper] Compiler merging SRLs -- Timing performance

Hi all, This is something I've been fighting with for a while now, and I wonder if anyone on this maillist has any insight (because I'm pretty sure I may just be doing something wrong with the tools). The problem: I'm playing with a ROACH2 design that (sometimes) compiles at 312 MHz. However,

Re: [casper] Compiler merging SRLs -- Timing performance

Hi Jack, Not sure if this will help, but in Planahead I would try to click and drag that LUT as close as possible to each of the outputs. And if that doesn't help or makes it worse, you could also try to duplicate the logic going to each of those outputs, forcing separate LUTs to be used.

Re: [casper] Compiler merging SRLs -- Timing performance

Hi, Jack, Are the tools are optimizing for area instead of speed? Are you using Pblocks? I don't know if this is relevant to your situation, but I've run into annoyances when the tools use equivalent register removal to save a few flip-flops but end up causing fan-out/routing issues. That

Re: [casper] Compiler merging SRLs -- Timing performance

Hey Mark, Yeah, I guess I could manually force the locations of the two offending shift-regs to stop the combination, but the problem SRLs seem to be a fairly arbitrary selection of those in the design. I don't really want to have to start constraining at the LUT level if I can help it. But maybe

Re: [casper] Compiler merging SRLs -- Timing performance

Hi Jack, In Simulink if have seen similar issues when trying to add more register pipelining, to decrease routing delay's and thus increase Fmax. However, ISE just collapses all the pipelining into a single SRL, which yields the frustrations you mentioned. You can prevent this from happening, by

Re: [casper] Compiler merging SRLs -- Timing performance

I often re-run XST with: register_balancing yes optimize_primitives yes read_cores yes shreg_extract no shreg_extract prevents adjacent registers from being combined into SRL16s. Jason Manley CBF Manager SKA-SA Cell: +27 82 662 7726 Work: +27 21 506 7300 On 05 Dec 2014, at 6:27, Henno Kriel