Re: [casper] SETI

hi howard, you can help us hunt for ET by downloading the s...@home screen saver at http://seti.berkeley.edu best wishes, dan Dan Werthimer SETI Program Director University of California, Berkeley Howard Relles wrote: Sir/Madam, Can you tell me how I can help evaluate/process incoming

Re: [casper] ADC/iBOB sample clock and VSI

hi jan, the ADC time domain data in your plots looks like it might not be time ordered correctly. time is perhaps swapped in groups of four: eg: ADC outputs samples t0, t1, t2, t3, t4, t5 and you might be displaying and analysing in this order: t3,t2,t1,t0,t7,t6,t5,t4,t11,t10,t9,t8

Re: [casper] CASPER Simulink butterfly_direct query

hi andrew, i'm ccing aaron parsons on this, designer of the original fft blocks. aaron might be able to comment on your email. as far as i know, no one has ever used the overflow outputs from the FFT blocks, so you may be the first person to debug this. best wishes, dan Andrew Martens

Re: [casper] approximate cost of next gen CASPER hardware

hi jonathan, we expect roach boards will be about $2500 each, plus FPGA. you'll need to add DRAM ($50 min), ATX enclosure ($100), and ATX power supply ($50). there are several ADC boards you can use, but only two ADC board that can sample 1 Gsps currently available: a) the Atmel/E2V dual

Re: [casper] Confusion/bug in green FFT block

I did get strange results when my sync pulse was too short, but that is likely just the block resetting before the reorder finishes. as laura points out, the FFT's minimum sync pulse period is tricky: see casper memo #24 http://casper.berkeley.edu/memos/sync_memo_v1.pdf btw, many people have

[casper] adc nomenclature

dear casper collaborators, we now have five adc boards that can plug into ibob's and roach's, and there is some confusion about what to call them. we had a discussion about ADC nomenclature yesterday, and we suggest the following names: ADC2x1000-8 is the casper dual iADC: 2 inputs,

Re: [casper] Casper 10.1 library issue

wan, i strongly advising the standard bee_xps tools that everyone in the casper collaboration uses. if you use a different set of tools then people won't be able to assist you, and your design won't be able to be used by other people. best wishes, dan wan.ch...@csiro.au wrote: Hi Henry:

Re: [casper] Casper 10.1 library issue

on the modules I will use in my design if I could understand your library development process. But unfortunately, there is less documents talking about the casper library development process. I hope I could get some help at this point. Thanks Wan -Original Message- From: Dan Werthimer

Re: [casper] Casper library basic setup

hi wan, sync should be zero on every clock except it should go high for one clock every N cycles, where N is in henry chen's memo on sync pulses. for example simulink spectrometer designs and examples on how to use sync pulse, see design gallery at:

Re: [casper] Question on control software on the ROACH

hi wan, regarding your question on roach I/O: in about a month, roach will be running BORPH, a linux operating system for fpga's (the operating system we use on the BEE2). in BORPH, registers, block rams and fifo's in your simulink design appear as linux files which you can read and write.

Re: [casper] setting internal USRCLK on BEE2

G Jones wrote: Hi John, I have brought this up a few time on this and the BEE2 mailing lists (archives???). hi glenn, be careful what you say on these mailings: billy made a search-able archive of the casper mailing, and he will put it on the web site soon. dan

Re: [casper] iBob and RS232 problems

if it works with one ibob board (no chaining), i suggest buying (or asking xilinx to donate) four USB download cables. dan Rurik Primiani wrote: Hi everyone, Thanks for the replies! To clarify a little more, our system is now on the summit of Mauna Kea so physically checking jumpers and

Re: [casper] question on sync pulse

hi wan, in case you haven't seen this, there are some sync pulse guidelines in casper memo 24: Sync Pulse Usage - July 2008 (Henry Chen, et al) http://casper.berkeley.edu/wiki/Memos best wishes, dan wan.ch...@csiro.au wrote: Hi: After reading the memo of sync pulse, I still feel a little

Re: [casper] large green FFTs

hi jason zheng, as you probably know, a 2^20 point FFT won't fit on an fpga, as it requires 2^19 times 36 bits of memory. the largest single fft that we've ever used on an FPGA is 2^15 points. to implement higher resolution spectrum analyzers one needs to implement analysis in two stages

Re: [casper] large green FFTs

support multi-million point FFTs. ~Jason Zheng On Mon, Jul 27, 2009 at 9:09 AM, Dan Werthimer d...@ssl.berkeley.edu mailto:d...@ssl.berkeley.edu wrote: hi jason zheng, as you probably know, a 2^20 point FFT won't fit on an fpga, as it requires 2^19

Re: [casper] ROACH problems?

hi shilpa, glen, and casper collaborators i'm forwarding your roach questions to casper@lists.berkeley.edu (roach collaborators - please see email chain appended below - can you help shilpa and glen?) in general if anyone has hardware, software, tools, or library problems, it's best to send

Re: [casper] ROACH progress.

dear casper collaborators, can anybody please advise ron on his question appended below about problems with 32K point wideband real transforms?? ron - does your 32K wideband real FFT work correctly in simulation? we've build instruments doing 32K complex transforms, but these FFT's are

Re: [casper] ROACH progress.

the masks to find that parameter and setting it so that the value is greater than the number of stages in the transform to see if that fixes it. Glenn On Thu, Aug 27, 2009 at 5:16 PM, Dan Werthimer d...@ssl.berkeley.edu mailto:d...@ssl.berkeley.edu wrote: dear casper collaborators

[casper] sync vs async systems

to connect the actual iBOB clock signal to the SMA GPIO in the model file? Jason -- Richard Armstrong ʞn˙ɔɐ˙xo˙oɹʇ...@ƃuoɹʇsɯɹɐ˙pɹɐɥɔıɹ +44 (0) 79 0682 9979 (UK mobile) +44 (0) 1865 273597 (Office) -- Dan Werthimer Space Sciences Lab and Berkeley Wireless Research Center University

[casper] casper tool set up question from ted jaeger

hi casper collaborators, can anyone help answer ted's questions below? thanks, dan On 08/29/2009 04:45 PM, Ted Jaeger wrote: Hi Dan, Is there a tutorial anywhere on setting up the software needed for a fully functional iBOB development system. I have been following the wiki articles on

Re: [casper] guidelines

hi marco, it would be great if you and others can acknowledge the CASPER collaboration, but there are no requirements or guidelines. andrew or others - can you email marco a logo? dan Hi everyone, Is there any guideline about how to cite the CASPER, writing presentations and articles?

Re: [casper] SPDO ROACH spectrometer

hi wan, i don't know of anyone who has roach ethernet problems at 100 Mbit/sec. i'm cc'ing casper community to see if anyone has any ideas. in general, it's good to post questions to cas...@lists, so that everyone can help answer, and everyone can see the answers, and the info will be

Re: [casper] Questions on porting to ROACH

hi andrew, the information in your email below will be helpful to all instrument developers using FFT block. is there an easy way to display this information in the fft parameter selection window? eg: click here for guidance on the choice of these parameters or see fft documentation

Re: [casper] Timing error

hi john, glenn jones is working with terry filiba today on improving the speed of the corner turn in the FFT.stay tuned. dan Hi John Some pointers on improving timing generally in ROACH. Decrease the space your design occupies. Implement delays on data inputs to multiplier cores

Re: [casper] ROACH boards

mo ohady m...@digicom.org On 11/18/2009 10:46 AM, Karl Warnick wrote: Hi all, I'd like to get in touch with Mo at Digicom to see if there are any boards currently available. Could someone provide contact information (or information on available boards from the most recent run)? Thanks,

Re: [casper] fiber capacity

of this board). Best Wishes, Dan Tom Kuiper wrote: Dan Werthimer wrote: Can you transmit the RF or IF through analog fibers, and then locate the digitizers in an electronics lab, where they are easy to service, upgrade, keep cool, shield from the receivers, ...? We can, in principal

Re: [casper] ROACH + BORPH time-of-day

Hi Tom We use hardware time tagging in some of the spectrometers we've built, accurate to a few nS, described below: We've implemented time tagging in spectrometers and correlators (we can send you some spectrometer designs if you want), by running the ADC sample clock from a synthesizer

Re: [casper] DC part of FFT output

hi wan, what are the levels of this output? if they are the least significant bits, then this is likely from round off noise. best wishes, dan On 1/12/2010 6:45 PM, wan.ch...@csiro.au wrote: Hi All: I use a matlab sine wave generator to generate a sine wave as an input to PFB and FFT.

Re: [casper] DC part of FFT output

or minimize the steps on noise floor? Thanks Wan *From:* Dan Werthimer [mailto:d...@ssl.berkeley.edu] *Sent:* Wednesday, 13 January 2010 2:37 PM *To:* casper@lists.berkeley.edu *Subject:* Re: [casper] DC part of FFT output

Re: [casper] DC part of FFT output

all different rounding options, I found round +/- inf is the best, even better than round even or odd. Is this normal? For wider bit width in FFT, I remember over 18 bits could not work properly. So now it is fixed and it can work upto 25 bits? Thanks, Dan. Wan From: Dan Werthimer [mailto:d

Re: [casper] ADC bit toggle levels

hi danny, i think your numbers are about right. for a noise like signal (eg: from a radio telescope), we typically drive the adc at levels around -20 to -15 dBm. best wishes, dan On 1/14/2010 8:29 PM, Danny Price wrote: Hi all, was hoping to get some clarification on real-world ADC bit

Re: [casper] DC part of FFT output

, but it important for long FFT's. best wishes, dan On 1/17/2010 4:43 PM, Dan Werthimer wrote: hi wan, the noise floor is independent of shifter settings - the noise RMS is typically about 1 or 2 LSB's (depending on the length of the FFT), due to quantization noise and round offer errors. so you'd like

Re: [casper] ROACH-based pulsar machine?

hi tom, there's a lot of current work in the areas you asked about: terry filiba recently ported the ibob based pulsar instrumentation to roach, (peter mcmahon and she developed this for parkes pulsar work). jonathan kocz and mathew bailes are working on roach porting as well. see peter's

Re: [casper] F engine for Packetized correlator

wei-chung, jason is in the karoo deploying a new PAPER correlator so i'm not sure when he'll be able to read your email. do you have 1 pulse per second sync signal going into your iADC boards? you need to drive one of the two iADC boards on each iBOB with a 1 PPS signal so all the iBOB's

[casper] xilinx donations, please send list of chips needed

dear casper collaborators, our collaboration is growing and xilinx requested we aggregate most of our donation requests so xilinx doesn't have to process as many requests. instead of each university or organization requesting chips, xilinx proposed they would give us a bulk donation of chips,

Re: [casper] Correlating iADC SYNC Outputs to Individual Samples...

hi randy, the sync outputs from the adc yellow block are a copy of the signal that is injected into the adc's sync input SMA connector. (in your case, the 1 PPS signal).all four syncs are identical. to know which adc sample is taken on the 1 second tick, one needs to calibrate by looking

Re: [casper] Correlating iADC SYNC Outputs to Individual Samples...

i don't think there's a reason, except perhaps decorative. henry - is there a reason for four sync's? dan On 3/4/2010 11:52 AM, Paul Demorest wrote: Hi Dan, I have to ask.. if all four syncs are the same, why are there four of them? ;) -Paul On Thu, 4 Mar 2010, Dan Werthimer wrote

Re: [casper] Correlating iADC SYNC Outputs to Individual Samples...

hi jason, dave and paul, regarding syncing up one or two adc's with 1 PPS: at boot up, the iADC (also called ADC2x1000-8), yellow block software/gateware aligns two adc's that are plugged into roach or ibob. the code does this by sampling the relative phase of the two clocks that emerge

Re: [casper] FS and safe maximum drives for 1 GHz dual ADC board V1.1

hi dana, matt's emails indicates full scale input of an iADC1.1 board is -2 dBm for a 630 MHz sine wave. you also asked about maximum input voltage before damage: we haven't intentionally tried to destroy an ADC board, but we've accidently injected strong signals into these boards by

Re: [casper] multiple clock domains

hi rick, the 10GBe block incorporates multiple clock domain logic already: you can send your data into the 10Ggbe block at any fpga clock rate (since the 10Gbe block has fifo's inside) and the 10Gbe block will transmit your data using it's internal 156.25 MHz clock. you must take care

Re: [casper] Intel 10 GbE card

hi gregory, our group has only tested myricom and chelsio 10Gbe NIC's. there are a few other NIC boards that have been recommended, but intel is not on the list. if you want to test a different NIC, i suggest you try to find a NIC that features an on board processor that can process UDP

Re: [casper] ROACH pulsar spectrometer

hi laura, are you trying to clock your FGPA at 200 or 400 MHz? if you configure the ADC yellow block to input 4 samples per clock, and sampling at 1600 Msps, then you will need to clock your fpga at 400 MHz, which is pretty near impossible for virtex 5 and you'll get lots of timing errors. if

Re: [casper] Issue with Fujitsu FPD-010R008-0E + FOC-CCxxxx

hi shilpa, the early CX4 10Gbe spec didn't supply optional power through the connector, and the first revision bee2's and ibob's we built didn't have powered connectors. but the spec changed several years ago, so i would have guessed that any modern NIC board would have powered connectors.

Re: [casper] Issue with Fujitsu FPD-010R008-0E + FOC-CCxxxx

ports, and think it's a bad idea. He says buy the SFP+ NIC, which can also be used with Direct Attach copper cables, for short runs (but I don't know what that means, really). Since we are about to buy NIC and Zarlink cable, I'm now concerned they won't work together. Any thoughts? Rick Dan Werthimer

Re: [casper] Issue with Fujitsu FPD-010R008-0E + FOC-CCxxxx

chosen. dan On 05/20/2010 10:01 AM, Rick Raffanti wrote: So I reckon I'll just buy the Chelsio board N310E-CXA- it's the same price, and specifically states Active Cable Compatible. I'll buy some 5m copper cables and some of the 15m Zarlink. Any reason that won't work? Rick Dan Werthimer wrote

Re: [casper] ADC documentation

hi dean, cc casper lists here are the doc's we have on the 3Gsps board: 1) schematic 2) pcb layout 3) simulink blocks for interfacing this adc to casper dsp libraries and other instruments. 4) verilog and vhdl interface code (under the simulink block). 5) various

Re: [casper] iADC scaling

hi jon, there are a couple of possibilities that might explain the frequency response you are seeing: 1) the ADC2x1000-8 board has poor termination. (the input impedance is not 50 ohms at all frequencies). this causes reflections, which depend on cable length and frequency.

Re: [casper] 16 ports of ADC

hi homin, the 16 input FFT takes twice as many resources as an 8 input FFT. (the 16 input FFT has 16 parallel inputs so it can compute fft's at 16 times the fpga clock rate). this factor of two expansion in fpga resources is largely independent of the input data bit width, because almost

[casper] Don Backer

I'm very sad to report that Don Backer died this afternoon. Don collapsed just outside his home, probably from a heart attack. Don had a great life and was a wonderful man. We will all miss him.

Re: [casper] 10gbe switch

hi tom, if you don't need much more than 10 Mbit/sec, then your system will be a lot cheaper if you use the 1Gbit roach ports. you'll have to change your gateware and software a bit to do this, but you'll save a lot of money in 10Gbe switches, cables, and nic boards. if you want to stick

Re: [casper] FFT on ROACH

hi andrea, you might be interested in other roach based seti systems: laura spitler ported the 128 million channel bee2 seti spectrometer to roach, and terry filiba developed a roach/GPU seti spectrometer, where roach digitizes data, breaks it up into sub-bands using a polyphase filter bank,

Re: [casper] Optimum PFB / FFT settings to meet timing

hi danny, i suggest trying jason's items first (below), and then if you are still having trouble, talk to suraj gowda, who got got the PFB and FFT to work at about 375 MHz by using xilinx's plan-ahead and calling out more explicit utilization of DSP48 slices for the FFT butterflies. suraj will

Re: [casper] 10GbE speed

end. I'm using the Chelsio with 1kB packets, haven't figured out how to do jumbo packets yet (which are a maximum of something like 10kB anyway). Rick -Original Message- From: Dan Werthimer d...@ssl.berkeley.edu Sent: Sep 24, 2010 4:32 PM To: rick raffanti rik...@earthlink.net Cc

Re: [casper] 3 Gs/s adc board demo example

hi jason, we don't have a design to write 3 Gsps ADC data into DRAM, but if it's useful, suraj and billy have a roach designs that write data from a pair of 3 Gsps ADC's to block ram for subsequent readout via borph. best wishes, dan On 9/30/2010 8:10 AM, Jason Ray wrote: At 09:16 PM

Re: [casper] updated cost/port for 10 GigE switches

hi jonthan, you can purchase 48 port SFP+ switches for about $250/port. you can purchase 20 port CX4 switches for about $500/port. (eg: Fujitsu XG2000C) regarding connectors - here's what i've gleaned from switch vendors and others: a) CX4 is being phased out. b) SFP+ is what most vendors

Re: [casper] iBOB freezing

hi laura, yes, digicom has done this revision on all ibob's since we learned about the problem. dan Laura Spitler wrote: Hello, I finally went and checked my iBOB, and it appears that there are already nylon and metal washers under the CX4 screws. Did Digicom start implementing this fix in

Re: [casper] SPEAD examples?

hi John, you asked about SPEAD FPGA implementations: Jason added SPEAD to the packetized correlator. i'm appending Jason's November 26 update on correlators, which includes a section on SPEAD. also, i think a recent pocket correlator, developed by Zaki, uses SPEAD. Zaki and Aaron have also

Re: [casper] IBOB Hardware problem

to Digicom? Thanks, Dale -- Dan Werthimer Space Sciences Lab and Berkeley Wireless Research Center University of Calfornia, Berkeley

Re: [casper] wideband conversion and correlation

hi jonathan, some ideas for your correlator: 1) 300 MHz is a good target, especially for V6. suraj has shown how to achieve 375 MHz for V5 by using floor planning and auto-placing. suraj or i can send you his draft paper on this if you'd like. 2) you might want to consider FFX instead of

Re: [casper] wideband conversion and correlation

6 GHz BW demux 32 case suggested in response to Suraj still requires 400 MHz FPGA clock, thus not so practical. Can one gain a factor of 2 in demux doing quadrature sampling, and having I and Q inputs to a complex input PFB each at 1/2 the rate? Jonathan On Dec 23, 2010, at 5:24 PM, Dan

Re: [casper] wideband conversion and correlation

analog filters. Apparently they have not worried about complete spectral coverage with the multitap off-line cross correlator. I wonder if there are other solutions to this problem. Regards, Bob Wilson On Fri, 24 Dec 2010, Dan Werthimer wrote: hi jason, jonathan, regarding jason's concerns

Re: [casper] Correlating subsets of antenna inputs

hi jonathan, as you pointed out, for a phased array feed, where the correlator is used only to calibrate the beamformer coefficients, you don't need to compute all the possible cross correlations, and you don't have to do the computation it in real time. the calibration time scale requirement

Re: [casper] rephrase question 2

hi ben, i'm not sure which FFT you are using. if you are using the biplex FFT, this computes two complex FFT's at once: two complex data streams go in, each with 2^N complex points, and two 2^N complex point streams come out. (not 2^(N-1)). i think the frequency ordering of the biplex FFT

Re: [casper] 10gbe switch

hi tom, i suggest you purchase a myricom 10Gbe CX4 NIC board, rather than a chelsio board. the myricom boards work well and jason wrote a casper memo with test results on myricom nics. myricom has drivers optimized for UDP packets, and drivers that skip over kernel memory and transfer data

Re: [casper] 10gbe switch

hi tom, one more note: if you use fiber optic CX4 cables, please see the warning at http://casper.berkeley.edu/wiki/Recommended_10_GbE_Hardware not all NIC boards have built in power to support fiber optic cables. check with myricom. the ibob/bee2/roach boards have built in power. dan

Re: [casper] 10gbe switch

. Rick On 1/28/2011 5:53 PM, Dan Werthimer wrote: hi tom, one more note: if you use fiber optic CX4 cables, please see the warning at http://casper.berkeley.edu/wiki/Recommended_10_GbE_Hardware not all NIC boards have

[casper] mini-casper workshops in Taipei and Beijing

Dear Casperites, If you are interested in attending the mini-casper workshops in Taipei (March 23-25) or Beijing (March 28-30), please contact the workshop organizers listed below. We'll have talks about casper hardware, tools and libraries, discussions about correlators, beamformers,

Re: [casper] monitoring clock lock

hi tom, you could connect the TTL signal to the SMA connector on the adc board, called sync in. this is a spare digital input, 0 to 2.5 volts, 50 ohm. but it would be easier to connect your signal to a printer port on your computer, or buy an inexpensive digital input to USB board.

Re: [casper] CentOS xilinx license manager

), I'm ok with Ubuntu but with this OS I had some issues making things work, if some of you has passed for this before, I'd be happy to know how you resolve it. Regards, Daniel H. -- Dan Werthimer Space Sciences Lab and Berkeley Wireless Research Center University of Calfornia, Berkeley

Re: [casper] CentOS xilinx license manager

hi andy, it's probably fine for experts like yourself to use non-supported OS's, but i wouldn't recommend it for non experts: we have run into some strange and subtle problems that i wouldn't have guessed would be operating system related. for instance, some of the FFT's in the simulink

Re: [casper] Roach: Getting Started Enviroment 2011

hi miguel, i recommend that you only use an operating system supported by xilinx. we've encountered strange errors and found instruments that produce incorrect results when using non-supported operating systems. and xilinx won't answer any questions or provide support if you use a

Re: [casper] Valon 5007 on ROACH ATX power

hi danny, cc stuart rumley, valon technology i agree with dana - if you use a switching power supply to power a synthesizer, the phase noise and jitter will likely be terrible and you'll get spurs and degraded SNR. i suggest you check with stuart rumley, the designer of the valon

Re: [casper] Anyone designing an e2v ZDOK board?

hi david, homin jiang at ASIAA has developed an ADC board with E2V's EV8AQ160 (8 bit), but not the AQ190 (10 bit). these two ADC's are very similar, almost pin for pin compatible, so it might be possible to modify homin's design. best wishes, dan On 5/10/2011 2:26 PM, David Forbes wrote:

Re: [casper] KatADC

hi tom, regarding pushing the KatADC from 2*1.5 Gsps to 4 Gsps: it will be difficult, perhaps impossible, to move 4 Gsps 8 bit ADC data through a single zdoc connector into roach I. each of the 32 bit lvds lanes would have to operate at 1 Gbit/sec, and we've never tried that on Roach I.

Re: [casper] setting up the equalizer gains for poco

hi mandana, where you set the ADC input level depends on the RFI environment. it's a balance between setting the level high enough to minimize quantization noise, yet low enough that the input signal doesn't saturate the ADC very often. if you don't have much RFI, a good level for an 8 bit

Re: [casper] Where to buy Viking Modular DDR2?

hi luis, i think mo ohady at digicom just bought 200 of these. he can probably sell you some: m...@digicom.org best wishes, dan On 6/14/2011 1:57 PM, Luis Quintero wrote: All, I wonder if someone knows where to buy in US the Viking Modular DDR2 memories (1Rx8 PC2-5300R-555-13-F0)

Re: [casper] ADF4350 as sampling clock generator for CASPER projects

Hi Glenn and others interested in frequency synthesizers: The $295 Valon Technology 5007 dual synthesizer board has two synthesizers that cover 138 MHz to 4400 MHz. Phase noise and other specs at: http://valontechnology.com/5007%20product%20data%20sheet%2011-04-10.pdf Jitter at 1500 MHz is

Re: [casper] clock signals...

hi jesus, to follow up on rick and jack's comments: to use the dual =1Gsps ADC at 1200 Msps, then as you point out, you need to use the ADC in interleave mode: you need to supply a 600 MHz clock to the ADC board; and the ADC will then supply a 150 MHz clock to the FPGA (the ADC clock is

Re: [casper] Low level design on a Roach board

hi aziz, can you use the standard casper libraries and tools? if you can use the standard libraries and tools, then you will be able to share your designs with the casper community as well as use the casper libraries and open source instrument designs. you'll also be able to get a lot of help

Re: [casper] newbie question

hi gerry, adc boards are listed at https://casper.berkeley.edu/wiki/Hardware but there's no price sheet. you can get quotes for most of these open source boards from m...@digicom.org you might consider the ADC1x5000-8https://casper.berkeley.edu/wiki/ADC1x5000-8, which can also be used as a dual

Re: [casper] ROACH2 power consumption

hi kaushal, francois provided numbers for worst case power consumption of roach II. they also have made measurements: about 65 watts typical for lightly loaded fgpa design, measured at the 220VAC input (includes the losses in power supplies, etc). for a heavily loaded fpga design using the

Re: [casper] High speed processing on host

hi marcus, there are several casper instruments that digitize data using ADC's plugged into one or more FGPA board(s). The FPGA boards packetize and time stamp the ADC data and send it over 10Gbit ethernet to one or more CPU's and GPU's. here are a couple of examples. the VEGAS instrument

Re: [casper] Spectrometer using ADC on PCI Express card feeding NVidia GPU

hi david, there are a few casper instruments that are similar to what you are suggesting. 1) some of the VEGAS spectrometer modes use a roach to digitize the data and send almost raw adc samples to a GPU where the spectroscopy is done. 2) some of the GUPPI pulsar machines use casper hardware to

Re: [casper] Roach I Board Power Requirements

hi joe, can you leave the DC-DC converters on the roach board? then you only need to supply the 12, 5 and 3.3 volts that come from the ATX power supply. best wishes, dan On Thu, Jan 19, 2012 at 10:28 AM, Joseph Greenberg jgree...@nrao.eduwrote: We at NRAO are going to mount the Roach I

Re: [casper] Roach I Board Power Requirements

, 2012 at 10:53 AM, Joseph Greenberg jgree...@nrao.eduwrote: ** Hi Dan, Thanks for the reply. Dan Werthimer wrote: hi joe, can you leave the DC-DC converters on the roach board? Yes. Are they standard on all Roach I boards or do we have to specify them? then you only need to supply

Re: [casper] Roach I Board Power Requirements

eliminate using the on-board 3.3V. Too bad tthe Pico device doesn't come in a 48V model. Thanks for all the help, Joe Dan Werthimer wrote: hi joe, the DC-DC converters are standard on the roach boards, so you only need to supply 3.3, 5 and 12 volts to the ATX connector. if you use john ford's

Re: [casper] Which chip for ROACH?

hi billy, the SX95T is the best Roach I chip for correlators, fft's and beamformers, because it has a lot of DSP48 multiplier/accumulator blocks. the LX110T has more slices but doesn't have as many DSP blocks. best wishes, dan On Tue, Jan 31, 2012 at 6:27 PM, Barott, William Chauncey

[casper] beware of non-xilinx supported operating systems

hi tom, beware of non-xilinx supported operating systems. they can waste a lot of your time. we've experience twisted and frustrating behavior with non-xilinx supported operating systems. in one case, our design compiled without any error or warning messages, but the FFT didn't produce the

Re: [casper] Workstop 10 Tutorial 3 trial

hi tom, if you are using kat-ADC's, you'll need to change the adc yellow block in the tutorial. dan On Fri, Mar 2, 2012 at 3:57 PM, Kuiper, Thomas (3266) kui...@jpl.nasa.govwrote: I think that's it! I after replacing the file system, I made the necessary changes from memory and general sys

Re: [casper] Any cable length considerations for ROACH?

hi billy, info on copper and optical cables we've tested is at: https://casper.berkeley.edu/wiki/Equipment_Cables virtex2 fpga's (ibob, bee2) do not meet 10GbeCX4 specifications, but virtex5 fpga's (roach) does meet the 10GbeX4 spec, so 5 meter CX4 cables should work. the longest cable we've

Re: [casper] reliable data streaming protocol for 100Mbps ethernet

hi laura, there are a couple of standard ways people stream data to the PPC and out over the network: ping pong memories - the FGPA write to memory A and then sets a flag saying memory A is full. the PPC code waits for this flag to be set and then moves memory A to

Re: [casper] reliable data streaming protocol for 100Mbps ethernet

hi laura, i second john's remarks: an inexpensive 10Gbit nic card in your computer would make your data streaming task relatively easy, as there are tutorials and several instrument designs that stream data from a roach over 10Gbe into a computer. there's also a lot of good open source

Re: [casper] reliable data streaming protocol for 100Mbps ethernet

a...@luto.us wrote: On Mar 14, 2012 3:26 PM, Dan Werthimer d...@ssl.berkeley.edu wrote: hi laura, i second john's remarks: an inexpensive 10Gbit nic card in your computer would make your data streaming task relatively easy, as there are tutorials and several instrument designs

Re: [casper] reliable data streaming protocol for 100Mbps ethernet

to.) He had suggested that thishttp://www.cdw.com/shop/products/Myricom-Myri-10G-network-adapter/2034587.aspxmay work, but I would be grateful for input from others that are currently using a RedHat machine with a 10GbE NIC. --Laura On Thu, Mar 15, 2012 at 9:45 AM, Dan Werthimer d

Re: [casper] fedora install

hi louis, i urge people to use only xilinx supported operating systems. you might get other operating systems to work in the sense they might not produce error messages and appear to compile your designs. but we've encountered strange results when compiling with non supported operating systems.

[casper] xilinx vivado design tools

article on Xilinx new Vivado Design tools: http://www.eejournal.com/archives/articles/20120501-bigdeal/

Re: [casper] 1-2 GHz sampler

hi bill, i think all the boards you mention have analog bandwidth out to 2 GHz, so they should work well for your 1-2 GHz band. the asiaa board is the least expensive, but this board does not have programmable attenuators like the Kat-ADC. the asiaa board can be used as a single 5 Gsps ADC, or

Re: [casper] 1-2 GHz sampler

: Dan Werthimer d...@ssl.berkeley.edu To: Bill Petrachenko wtpe...@yahoo.ca Sent: Monday, May 28, 2012 11:21:40 PM Subject: Re: [casper] 1-2 GHz sampler the kat-adc has two different front end fiilter options. make sure to order the filter option for high frequency. dan On Mon, May 28, 2012

Re: [casper] ibob CX4 with 15m cable?

hi ian, the ibob uses the old virtex2Pro fpga's, which do not meet 10Gbit ethernet spec, so 3 meters is about as far as you can go with copper cables. as dave mentioned, if you want to go 3 to 100 meters you can use optical CX4 cables. there are some part numbers of optical and copper cables

Re: [casper] Using ROACH 10gbe interface as 1gbe

hi alex, sorry - you can't adapt the 10Gbe port to a 1Gbe port as the CX4 and RJ45 signals are not electrically compatible. there is, as you probably know, a 1Gbe port on the roach I, but it's not directly connected to the FPGA - the data from the FPGA must go through the CPU to the 1Gbe port,

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