Re: [casper] 10Gbe transmission on roach 1

2015-08-17 Thread Kaustubh Rajwade
Hi Jack, Apologies for the late reply. To answer your questions, yes, I have enabled the 10Gbe to receive large packets and I receive packets of the same size that I send out. Cheers, Kaustubh On Thu, Aug 6, 2015 at 8:47 PM, indrajit indra...@iiap.res.in wrote: Dear Kaustubh, Sorry for the

Re: [casper] 10Gbe transmission on roach 1

2015-08-11 Thread Kaustubh Rajwade
Hi Jason, Thanks for that insight. The design is working fine for packet length of 800. Anything beyond that and the core locks up. The tx_over is high suggesting that the tx_buffers overflow for packet length greater than 800. For my application, a size of 800 is sufficient but was just curious

Re: [casper] 10Gbe transmission on roach 1

2015-08-11 Thread Jack Hickish
Hi Kaustubh, Have you set the option in the tgev2 yellow block to enable large tx frames? Do the receive the packets with the size you're expecting (I.e. is the EOF synchronisation logic working properly) Cheers, Jack On Tue, 11 Aug 2015 6:18 am Kaustubh Rajwade rkaustub...@gmail.com wrote: Hi

Re: [casper] 10Gbe transmission on roach 1

2015-08-07 Thread Jason Manley
You actually get 12.5Gbps raw line rate. The 10Gbps spec is the usable linerate, after coding, so should be representative of what you should be able to send. I suspect your problem is with packet size. The default TX/RX buffers on the 10G core are only 8192B each. If I understand correctly,

[casper] 10Gbe transmission on roach 1

2015-08-06 Thread indrajit
Dear Kaustubh, iadc which I am clocking at 560 MHz (hence the board runs at 140 MHz). The data comes in to a 10 GBe block. After 800 clock cycles, The data rate goes like this as per your input .. 5.7142 us is the time for 800 clock cycles @ 140 MHz. So the data rate calculation goes

[casper] 10Gbe transmission on roach 1

2015-08-03 Thread Kaustubh Rajwade
Hi All, I have a simple design on Roach 1 where I stream packets over the 10Gbe network. Currently, I am running the board at 140 MHz. When I try to send packets of length 800, the core locks up. I believe that the 10 Gbe core is synchronized with 156 MHz crystal on the board so this design