Re: [casper] katADC, ISE/SysGen10.1 compatible?
Hi LuisDavid George (as the author of the "yellow block" and underlying controller) is probably the correct person to respond to this question but if you areplanning on switching to the Xilinx 11.x suite, then I would encourage you to do so. We are using 11.5 at KAT and have no problems using the KATADC.FWIW, it looks like ROACH2 will start using 12.x tools so it might be a good idea not to fall too far behind the development versions.JasonOn 26 Mar 2011, at 01:41, Luis Quintero wrote:UPDATE:I created new netlists and verilog files of {fab,cpu}_op_fifo and rx_fifo, using FIFO Generator v4.3 and selecting the options according to theoriginal XCO files.The only thing that I did not copy exactly is the reset_type option of the rx_fifo in v5.3: reset_type=Synchronous_Reset. I am getting this error fromxst:...INSTANCE:iic_adc0...ERROR:HDLCompilers:91 ...\kat_adc_iic_controller_v1_00_a/hdl/verilog/kat_adc_iic_controller.v" line 125 Module 'rx_fifo' does not have a port named 'rst'...The thing is that sync. reset rename the pin to "srst" instead "rst". For testing purposes, I changed this option to async:reset_type=Asynchronous_Reset, and the synthesis finished!! But, is this a safe procedure?I programmed a Roach board, but I am not sure if this trick worked?--In [41]: fpga.progdev('katadc_alone_2011_Mar_25_1844.bof')Out[41]: 'ok'In [36]: corr.katadc.get_ambient_temp(fpga,0)Out[36]: 0.0In [37]: corr.katadc.eeprom_details_get(fpga,0)Out[37]:{'adc_ic_id': 0,'pcb_rev': 0,'reserved': (0, 0, 0, 0),'rf_fe_id': 0,'serial_number': 0}--How can I test if this is working?Thanks again,-- Luis Quintero, Arecibo ObservatoryOn 03/25/2011 04:57 PM, Luis Quintero wrote:Dear katADC users,I am trying to synthesize a simple design using the katadc block (see screen capture in the attachments). This is my tool set in a Windows XP machine:ISE 10.1, SysGen v.10.1.1134, MATLAB R2007b, v7.5.0.342, latest CASPER libs (today's git clone http://casper.berkeley.edu/git/mlib_devel.git).I am getting an exception in xst for iic_adc0:...EXCEPTION:Xdm:FileReader.c:428:$Id: FileReader.c,v 1.36 2004/09/15 20:29:16 jdl Exp $ - Xdm_Exception::UnsupportedFileFormatVersion The Xdm_Model FileFormat version 'V1.5e' is not supportedThe explanation of this issue is available in the Xilinx answers database AR#33915 (http://www.xilinx.com/support/answers/33915.htm). This problem iscaused for version incompatibility of the software that generates some netlist of the CASPER libs and my toolset version.I tried to find all the "iic" things related to katadc in the libs, and generate the netlist using my Xilinx core generator. I started withkat_iic_controller_v1_00_a, I generated the {op,rx}_fifo modules, and I am getting the same exception error from xst.Then I moved to kat_adc_iic_controller_v1_00_a with not success. Apparently the coregen project uses the FIFO generator v5.3, the latest version thatI have is v.4.3.So, my questions are:- Am I seeing the problem in the right way?- Can I generate the netlists of {fab,cpu}_op_fifo and rx_fifo using v4.3 and synthesize the design? If so, can I use the same parameters of the XCOfiles?- Do I have to migrate to ISE/SysGen ver. 11.x? (I planning to do this in the future...)Thanks!-- Luis Quintero, Arecibo Observatory
Re: [casper] katADC, ISE/SysGen10.1 compatible?
Hi Luis.
I created new netlists and verilog files of {fab,cpu}_op_fifo and rx_fifo,
using FIFO Generator v4.3 and selecting the options according to the original
XCO files.
As you have worked out, the FIFO netlists were generated using ISE 11
tools, making them incompatible with 10.1. Regenerating them as you
did was the right way to go. There shouldn't be any reason that you
cant use the KATADC with 10.1.
The only thing that I did not copy exactly is the reset_type option of the
rx_fifo in v5.3: reset_type=Synchronous_Reset. I am getting this error from
xst:
This shouldn't make any difference. Synchronous resets are probably best anyway.
I programmed a Roach board, but I am not sure if this trick worked?
--
In [41]: fpga.progdev('katadc_alone_2011_Mar_25_1844.bof')
Out[41]: 'ok'
In [36]: corr.katadc.get_ambient_temp(fpga,0)
Out[36]: 0.0
In [37]: corr.katadc.eeprom_details_get(fpga,0)
Out[37]:
{'adc_ic_id': 0,
'pcb_rev': 0,
'reserved': (0, 0, 0, 0),
'rf_fe_id': 0,
'serial_number': 0}
--
This is definitely not working. I suspect you are getting all zero's
on reads. I'm not really sure why this is happening.
Firstly I would check that PPC comms are okay by reading and writing
to the sys_scratchpad register. I would then dump the
kat_iic_controller register and look for any non-zero values. If you
don't see anything this most likely means something is wrong with the
generated EDK project. Exactly, what would be hard to say. You could
post your generated XPS_ROACH_base/system.mhs and coreinfo.tab files
which may give some clues.
I think Jason might have some code which manipulates the
kat_iic_controller register directly. This might provide a little more
insight than the corr routines.
Hopefully we can work this one out quickly.
Cheers,
David
Re: [casper] katADC, ISE/SysGen10.1 compatible?
Hey Jason (and CASPER) FWIW, it looks like ROACH2 will start using 12.x tools so it might be a good idea not to fall too far behind the development versions. ROACH-2 will start out using the 11 toolflow. A whole lot of work is required to get things moved over to the 12 and 13 tools. We will need some scheme of migrating from OPB to PLB. That said, we'll get there eventually. Cheers, David
[casper] katADC, ISE/SysGen10.1 compatible?
Dear katADC users,
I am trying to synthesize a simple design using the katadc block (see
screen capture in the attachments). This is my tool set in a Windows XP
machine: ISE 10.1, SysGen v.10.1.1134, MATLAB R2007b, v7.5.0.342, latest
CASPER libs (today's git clone
http://casper.berkeley.edu/git/mlib_devel.git).
I am getting an exception in xst for iic_adc0:
...
EXCEPTION:Xdm:FileReader.c:428:$Id: FileReader.c,v 1.36 2004/09/15
20:29:16 jdl Exp $ - Xdm_Exception::UnsupportedFileFormatVersion The
Xdm_Model File Format version 'V1.5e' is not supported.
...
The explanation of this issue is available in the Xilinx answers
database AR#33915 (http://www.xilinx.com/support/answers/33915.htm).
This problem is caused for version incompatibility of the software that
generates some netlist of the CASPER libs and my toolset version.
I tried to find all the iic things related to katadc in the libs, and
generate the netlist using my Xilinx core generator. I started with
kat_iic_controller_v1_00_a, I generated the {op,rx}_fifo modules, and I
am getting the same exception error from xst.
Then I moved to kat_adc_iic_controller_v1_00_a with not success.
Apparently the coregen project uses the FIFO generator v5.3, the latest
version that I have is v.4.3.
So, my questions are:
- Am I seeing the problem in the right way?
- Can I generate the netlists of {fab,cpu}_op_fifo and rx_fifo using
v4.3 and synthesize the design? If so, can I use the same parameters of
the XCO files?
- Do I have to migrate to ISE/SysGen ver. 11.x? (I planning to do this
in the future...)
Thanks!
-- Luis Quintero, Arecibo Observatory
attachment: katadc_ise_101.png...
INSTANCE:katadc_alone_katadc0 -
C:\test_model\katadc_alone\XPS_ROACH_base\system.mhs line 238 - Running XST
synthesis
INSTANCE:iic_adc0 - C:\test_model\katadc_alone\XPS_ROACH_base\system.mhs line
302 - Running XST synthesis
EXCEPTION:Xdm:FileReader.c:428:$Id: FileReader.c,v 1.36 2004/09/15 20:29:16 jdl
Exp $ - Xdm_Exception::UnsupportedFileFormatVersion The Xdm_Model File Format
version 'V1.5e' is not supported. Please ensure that the file was last modified
by a compatible software version
ERROR:MDT - Aborting XST flow execution!
INFO:MDT - Refer to
C:\test_model\katadc_alone\XPS_ROACH_base\synthesis\iic_adc0_wrapper_xst.srp
for details
Running NGCBUILD ...
ERROR:MDT - IPNAME:iic_adc0_wrapper INSTANCE:iic_adc0 -
C:\test_model\katadc_alone\XPS_ROACH_base\system.mhs line 302 - failed to
move
C:\test_model\katadc_alone\XPS_ROACH_base\implementation\iic_adc0_wrapper.ngc
to
C:\test_model\katadc_alone\XPS_ROACH_base\implementation\iic_adc0_wrapper\iic
_adc0_wrapper.ngc
IPNAME:katadc_alone_xsg_core_config_wrapper
INSTANCE:katadc_alone_xsg_core_config -
C:\test_model\katadc_alone\XPS_ROACH_base\system.mhs line 194 - Running
NGCBUILD
...
Re: [casper] katADC, ISE/SysGen10.1 compatible?
UPDATE:
I created new netlists and verilog files of {fab,cpu}_op_fifo and
rx_fifo, using FIFO Generator v4.3 and selecting the options according
to the original XCO files.
The only thing that I did not copy exactly is the reset_type option of
the rx_fifo in v5.3: reset_type=Synchronous_Reset. I am getting this
error from xst:
...
INSTANCE:iic_adc0...
ERROR:HDLCompilers:91 ...
\kat_adc_iic_controller_v1_00_a/hdl/verilog/kat_adc_iic_controller.v
line 125 Module 'rx_fifo' does not have a port named 'rst'
...
The thing is that sync. reset rename the pin to srst instead rst.
For testing purposes, I changed this option to async:
reset_type=Asynchronous_Reset, and the synthesis finished!! But, is this
a safe procedure?
I programmed a Roach board, but I am not sure if this trick worked?
--
In [41]: fpga.progdev('katadc_alone_2011_Mar_25_1844.bof')
Out[41]: 'ok'
In [36]: corr.katadc.get_ambient_temp(fpga,0)
Out[36]: 0.0
In [37]: corr.katadc.eeprom_details_get(fpga,0)
Out[37]:
{'adc_ic_id': 0,
'pcb_rev': 0,
'reserved': (0, 0, 0, 0),
'rf_fe_id': 0,
'serial_number': 0}
--
How can I test if this is working?
Thanks again,
-- Luis Quintero, Arecibo Observatory
On 03/25/2011 04:57 PM, Luis Quintero wrote:
Dear katADC users,
I am trying to synthesize a simple design using the katadc block (see
screen capture in the attachments). This is my tool set in a Windows
XP machine: ISE 10.1, SysGen v.10.1.1134, MATLAB R2007b, v7.5.0.342,
latest CASPER libs (today's git clone
http://casper.berkeley.edu/git/mlib_devel.git).
I am getting an exception in xst for iic_adc0:
...
EXCEPTION:Xdm:FileReader.c:428:$Id: FileReader.c,v 1.36 2004/09/15
20:29:16 jdl Exp $ - Xdm_Exception::UnsupportedFileFormatVersion The
Xdm_Model File Format version 'V1.5e' is not supported.
...
The explanation of this issue is available in the Xilinx answers
database AR#33915 (http://www.xilinx.com/support/answers/33915.htm).
This problem is caused for version incompatibility of the software
that generates some netlist of the CASPER libs and my toolset version.
I tried to find all the iic things related to katadc in the libs,
and generate the netlist using my Xilinx core generator. I started
with kat_iic_controller_v1_00_a, I generated the {op,rx}_fifo modules,
and I am getting the same exception error from xst.
Then I moved to kat_adc_iic_controller_v1_00_a with not success.
Apparently the coregen project uses the FIFO generator v5.3, the
latest version that I have is v.4.3.
So, my questions are:
- Am I seeing the problem in the right way?
- Can I generate the netlists of {fab,cpu}_op_fifo and rx_fifo using
v4.3 and synthesize the design? If so, can I use the same parameters
of the XCO files?
- Do I have to migrate to ISE/SysGen ver. 11.x? (I planning to do
this in the future...)
Thanks!
-- Luis Quintero, Arecibo Observatory
