FreddyLeaf wrote:
Sorry, I was OOO, thanks for the fix!
https://github.com/llvm/llvm-project/pull/92338
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None
>From 7f5ca96930fe48617115e2403094e2724aa7b9cd Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Thu, 30 May 2024 15:20:18 +0800
Subject: [PATCH] Fix build warning for '[X86] Support EGPR for inline
https://github.com/FreddyLeaf closed
https://github.com/llvm/llvm-project/pull/92338
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>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 01/13] [X86] Support EGPR for inline assembly.
"jR": explictly
@@ -1,21 +1,27 @@
; Check r16-r31 can not be used with 'q','r','l' constraint for backward
compatibility.
-; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 |
FileCheck %s
+; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 |
FileCheck
@@ -57999,13 +58020,25 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
if (Subtarget.is64Bit()) {
if (VT == MVT::i8 || VT == MVT::i1)
- return
FreddyLeaf wrote:
[e752556](https://github.com/llvm/llvm-project/pull/92338/commits/e752556c06ac25d905c6e642bdcb5e9244db5da3)
https://github.com/llvm/llvm-project/pull/92338
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FreddyLeaf wrote:
[e752556](https://github.com/llvm/llvm-project/pull/92338/commits/e752556c06ac25d905c6e642bdcb5e9244db5da3)
https://github.com/llvm/llvm-project/pull/92338
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@@ -0,0 +1,25 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 < %s | FileCheck %s
+; RUN: not llc -mtriple=x86_64 -mattr=+egpr < %s | FileCheck %s
FreddyLeaf wrote:
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 01/13] [X86] Support EGPR for inline assembly.
"jR": explictly
@@ -1,21 +1,27 @@
; Check r16-r31 can not be used with 'q','r','l' constraint for backward
compatibility.
-; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 |
FileCheck %s
+; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 |
FileCheck
@@ -0,0 +1,25 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 < %s | FileCheck %s
+; RUN: not llc -mtriple=x86_64 -mattr=+egpr < %s | FileCheck %s
FreddyLeaf wrote:
I'll try. If so, we can refine
@@ -1,21 +1,27 @@
; Check r16-r31 can not be used with 'q','r','l' constraint for backward
compatibility.
-; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 |
FileCheck %s
+; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 |
FileCheck
https://github.com/FreddyLeaf edited
https://github.com/llvm/llvm-project/pull/92338
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@@ -1,21 +1,27 @@
; Check r16-r31 can not be used with 'q','r','l' constraint for backward
compatibility.
-; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 |
FileCheck %s
+; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 |
FileCheck
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 01/12] [X86] Support EGPR for inline assembly.
"jR": explictly
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: llc -mtriple=x86_64 -mattr=+egpr < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64
FreddyLeaf wrote:
81f58b6, pls review if I understand correctly.
https://github.com/llvm/llvm-project/pull/92338
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FreddyLeaf wrote:
81f58b6
https://github.com/llvm/llvm-project/pull/92338
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@@ -5394,10 +5394,12 @@ X86:
- ``Z``: An immediate 32-bit unsigned integer.
- ``q``: An 8, 16, 32, or 64-bit register which can be accessed as an 8-bit
``l`` integer register. On X86-32, this is the ``a``, ``b``, ``c``, and ``d``
- registers, and on X86-64, it is all of the
@@ -5394,10 +5394,12 @@ X86:
- ``Z``: An immediate 32-bit unsigned integer.
- ``q``: An 8, 16, 32, or 64-bit register which can be accessed as an 8-bit
``l`` integer register. On X86-32, this is the ``a``, ``b``, ``c``, and ``d``
- registers, and on X86-64, it is all of the
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 01/11] [X86] Support EGPR for inline assembly.
"jR": explictly
@@ -57581,6 +57581,14 @@ X86TargetLowering::getConstraintType(StringRef
Constraint) const {
case '2':
return C_RegisterClass;
}
+case 'j':
+ switch (Constraint[1]) {
+ default:
+break;
+ case 'r':
+ case 'R':
+return
@@ -57660,6 +57668,19 @@ X86TargetLowering::getSingleConstraintMatchWeight(
break;
}
break;
+ case 'j':
+if (StringRef(Constraint).size() != 2)
+ break;
+switch (Constraint[1]) {
+default:
+ return CW_Invalid;
+case 'r':
+case 'R':
@@ -57581,6 +57581,14 @@ X86TargetLowering::getConstraintType(StringRef
Constraint) const {
case '2':
return C_RegisterClass;
}
+case 'j':
+ switch (Constraint[1]) {
+ default:
+break;
+ case 'r':
+ case 'R':
+return
@@ -5418,6 +5418,8 @@ X86:
operand will get allocated only to RAX -- if two 32-bit operands are needed,
you're better off splitting it yourself, before passing it to the asm
statement.
+- ``jR``: An 8, 16, 32, or 64-bit integer EGPR when EGPR feature is on.
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 01/10] [X86] Support EGPR for inline assembly.
"jR": explictly
@@ -5418,6 +5418,8 @@ X86:
operand will get allocated only to RAX -- if two 32-bit operands are needed,
you're better off splitting it yourself, before passing it to the asm
statement.
+- ``jR``: An 8, 16, 32, or 64-bit integer EGPR when EGPR feature is on.
+ Otherwise,
@@ -58024,15 +58043,22 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
case 'r': // GENERAL_REGS
case 'l': // INDEX_REGS
if (VT == MVT::i8 || VT == MVT::i1)
-return std::make_pair(0U, ::GR8_NOREX2RegClass);
+
@@ -58255,6 +58281,22 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
}
break;
}
+ } else if (Constraint.size() == 2 && Constraint[0] == 'j') {
+switch (Constraint[1]) {
+default:
+ break;
+case 'R':
+
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: llc -mtriple=x86_64 -mattr=+egpr < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 < %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: not llc -mtriple=x86_64 -mattr=+egpr < %s 2>&1 | FileCheck %s
--check-prefix=ERR
+; RUN: llc
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 < %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: not llc -mtriple=x86_64 -mattr=+egpr < %s 2>&1 | FileCheck %s
--check-prefix=ERR
+; RUN: llc
https://github.com/FreddyLeaf edited
https://github.com/llvm/llvm-project/pull/92338
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>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 1/9] [X86] Support EGPR for inline assembly.
"jR": explictly
@@ -58024,15 +58043,22 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
case 'r': // GENERAL_REGS
case 'l': // INDEX_REGS
if (VT == MVT::i8 || VT == MVT::i1)
-return std::make_pair(0U, ::GR8_NOREX2RegClass);
+
@@ -5418,6 +5418,8 @@ X86:
operand will get allocated only to RAX -- if two 32-bit operands are needed,
you're better off splitting it yourself, before passing it to the asm
statement.
+- ``jR``: An 8, 16, 32, or 64-bit integer EGPR when EGPR feature is on.
+ Otherwise,
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: llc -mtriple=x86_64 -mattr=+egpr < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64
@@ -5418,6 +5418,8 @@ X86:
operand will get allocated only to RAX -- if two 32-bit operands are needed,
you're better off splitting it yourself, before passing it to the asm
statement.
+- ``jR``: An 8, 16, 32, or 64-bit integer EGPR when EGPR feature is on.
+ Otherwise,
FreddyLeaf wrote:
ping @KanRobert
https://github.com/llvm/llvm-project/pull/92338
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>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 1/8] [X86] Support EGPR for inline assembly.
"jR": explictly
https://github.com/FreddyLeaf closed
https://github.com/llvm/llvm-project/pull/93136
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FreddyLeaf wrote:
> Not sure - CI checks aren't running either
Woops, I was thinking that is CI checks. I was just wondering for CI checks.
Now it's recovered. Thanks anyway!
https://github.com/llvm/llvm-project/pull/93136
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FreddyLeaf wrote:
any idea on why `Labelling new pull requests / greeter (pull_request_target)`
is **skipped**? @phoebewang @RKSimon
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@@ -58016,15 +58035,27 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
break;
case 'r': // GENERAL_REGS
case 'l': // INDEX_REGS
+ if (Subtarget.useInlineAsmGPR32()) {
+if (VT == MVT::i8 || VT == MVT::i1)
+
https://github.com/FreddyLeaf closed
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@@ -139,6 +139,9 @@ Changes to the Windows Target
Changes to the X86 Backend
--
+- Removed knl/knm specific ISA lowerings: AVX512PF, AVX512ER, PREFETCHWT1,
FreddyLeaf wrote:
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 1/8] [X86] Support EGPR for inline assembly.
"jR": explictly
FreddyLeaf wrote:
> Please note it in release notes.
[13a0f8d](https://github.com/llvm/llvm-project/pull/92883/commits/13a0f8d87343fd1a6380a66b7986ad1ce34b06fc)
https://github.com/llvm/llvm-project/pull/92883
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@@ -1,373 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
FreddyLeaf wrote:
[13a0f8d](https://github.com/llvm/llvm-project/pull/92883/commits/13a0f8d87343fd1a6380a66b7986ad1ce34b06fc)
@@ -8,16 +8,12 @@ target triple = "x86_64-unknown-linux-gnu"
define dso_local i32 @main() local_unnamed_addr #0 !dbg !7 {
entry:
tail call void @llvm.prefetch(ptr inttoptr (i64 291 to ptr), i32 0, i32 0,
i32 1), !dbg !9
- tail call void @llvm.x86.avx512.gatherpf.dpd.512(i8
@@ -1,373 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
FreddyLeaf wrote:
scheduleinfo was removed. Now I think we should keep schedule info for these
instructions, will add back.
@@ -268,30 +268,6 @@ define void @gather_qps(<8 x i64> %ind, <8 x float> %src,
ptr %base, ptr %stbuf)
ret void
}
-declare void @llvm.x86.avx512.gatherpf.qps.512(i8, <8 x i64>, ptr , i32, i32);
FreddyLeaf wrote:
yes, this should be a bug before.
@@ -23,7 +23,7 @@
br i1 %6, label %4, label %5, !llvm.loop !9
}
- attributes #0 = { nofree norecurse nosync nounwind uwtable writeonly
mustprogress "frame-pointer"="none" "min-legal-vector-width"="0"
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: llc -mtriple=x86_64 -mattr=+egpr < %s | FileCheck %s
--check-prefix=EGPR
+; RUN: llc -mtriple=x86_64
@@ -0,0 +1,29 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 < %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: not llc -mtriple=x86_64 -mattr=+egpr < %s 2>&1 | FileCheck %s
--check-prefix=ERR
+; RUN: llc
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 1/7] [X86] Support EGPR for inline assembly.
"jR": explictly
https://github.com/FreddyLeaf ready_for_review
https://github.com/llvm/llvm-project/pull/92883
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FreddyLeaf wrote:
gcc recently formally removed knl/knm supports at trunk:
https://godbolt.org/z/nKvo1P48d
Per conclusion before in https://github.com/llvm/llvm-project/pull/75580, this
patch removed specific ISA supports of knl/knm while keep -march/tune support
https://github.com/FreddyLeaf edited
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FreddyLeaf wrote:
> `
> [4087704](/llvm/llvm-project/pull/92338/commits/40877041618aa8f472f0da7cda06c21f4007a1ec)`
Thanks reminding. Added in 4087704, pls help review.
https://github.com/llvm/llvm-project/pull/92338
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https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 1/6] [X86] Support EGPR for inline assembly.
"jR": explictly
FreddyLeaf wrote:
[4d1ad30](https://github.com/llvm/llvm-project/pull/92338/commits/4d1ad3090416cda320c88f1ddc0937b5749e64b4)
moved but not merged. These two constraints will behavior different under
-mattr=+egpr.
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 1/5] [X86] Support EGPR for inline assembly.
"jR": explictly
FreddyLeaf wrote:
ping for review
https://github.com/llvm/llvm-project/pull/92338
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https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 1/4] [X86] Support EGPR for inline assembly.
"jR": explictly
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector ,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
FreddyLeaf wrote:
> > > Will the feature
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector ,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
FreddyLeaf wrote:
SSELevel relies on
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector ,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
FreddyLeaf wrote:
> Will the feature be
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 1/3] [X86] Support EGPR for inline assembly.
"jR": explictly
FreddyLeaf wrote:
> Please put the corresponding GCC links for your description
done.
https://github.com/llvm/llvm-project/pull/92338
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@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector ,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
FreddyLeaf wrote:
pls notice that this
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector ,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
FreddyLeaf wrote:
`mcmodel` maybe not a
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector ,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
FreddyLeaf wrote:
I want to use
https://github.com/FreddyLeaf created
https://github.com/llvm/llvm-project/pull/92338
"jR": explictly enables EGPR
"r": enables/disables EGPR w/wo -mapx-inline-asm-use-gpr32
-mapx-inline-asm-use-gpr32 will also define a new Macro:
__APX_INLINE_ASM_USE_GPR32__
>From
https://github.com/FreddyLeaf closed
https://github.com/llvm/llvm-project/pull/91323
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https://github.com/FreddyLeaf edited
https://github.com/llvm/llvm-project/pull/91323
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FreddyLeaf wrote:
[a627464](https://github.com/llvm/llvm-project/pull/91323/commits/a627464ef0ed4e999dc52b6b2d445548b559fe8b)
https://github.com/llvm/llvm-project/pull/91323
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https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/91323
>From 3bab8062eb7b924234b1f4959adc0bc72fb53417 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Tue, 7 May 2024 20:57:54 +0800
Subject: [PATCH 1/5] [X86][CFE] Support EGPR in inline assembly.
---
@@ -0,0 +1,10 @@
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown %s -o /dev/null
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-feature +egpr %s -o
/dev/null
+
+int foo(void) {
+ register int a __asm__("ebx");
+#ifdef __EGPR__
FreddyLeaf wrote:
@@ -0,0 +1,10 @@
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown %s -o /dev/null
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-feature +egpr %s -o
/dev/null
+
+int foo(void) {
+ register int a __asm__("ebx");
+#ifdef __EGPR__
FreddyLeaf wrote:
@@ -0,0 +1,10 @@
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown %s -o /dev/null
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-feature +egpr %s -o
/dev/null
+
+int foo(void) {
+ register int a __asm__("ebx");
+#ifdef __EGPR__
FreddyLeaf wrote:
@@ -0,0 +1,10 @@
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown %s -o /dev/null
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-feature +egpr %s -o
/dev/null
+
+int foo(void) {
+ register int a __asm__("ebx");
+#ifdef __EGPR__
FreddyLeaf wrote:
@@ -83,8 +85,23 @@ const TargetInfo::AddlRegName AddlRegNames[] = {
{{"r13d", "r13w", "r13b"}, 43},
{{"r14d", "r14w", "r14b"}, 44},
{{"r15d", "r15w", "r15b"}, 45},
+{{"r16d", "r16w", "r16b"}, 165},
FreddyLeaf wrote:
it's the index of "r16" in
@@ -1763,10 +1823,14 @@ void
X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl ) con
}
ArrayRef X86TargetInfo::getGCCRegNames() const {
+ if (HasEGPR)
+return llvm::ArrayRef(ExtendedGCCRegNames);
return llvm::ArrayRef(GCCRegNames);
FreddyLeaf
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/91323
>From 3bab8062eb7b924234b1f4959adc0bc72fb53417 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Tue, 7 May 2024 20:57:54 +0800
Subject: [PATCH 1/4] [X86][CFE] Support EGPR in inline assembly.
---
@@ -0,0 +1,10 @@
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown %s -o /dev/null
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-feature +egpr %s -o
/dev/null
+
+int foo(void) {
+ register int a __asm__("ebx");
+#ifdef __EGPR__
FreddyLeaf wrote:
@@ -1763,10 +1823,14 @@ void
X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl ) con
}
ArrayRef X86TargetInfo::getGCCRegNames() const {
+ if (HasEGPR)
+return llvm::ArrayRef(ExtendedGCCRegNames);
return llvm::ArrayRef(GCCRegNames);
FreddyLeaf
https://github.com/FreddyLeaf ready_for_review
https://github.com/llvm/llvm-project/pull/91323
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https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/91323
>From 3bab8062eb7b924234b1f4959adc0bc72fb53417 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Tue, 7 May 2024 20:57:54 +0800
Subject: [PATCH 1/3] [X86][CFE] Support EGPR in inline assembly.
---
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/91323
>From 3bab8062eb7b924234b1f4959adc0bc72fb53417 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Tue, 7 May 2024 20:57:54 +0800
Subject: [PATCH 1/2] [X86][CFE] Support EGPR in inline assembly.
---
https://github.com/FreddyLeaf converted_to_draft
https://github.com/llvm/llvm-project/pull/91323
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https://github.com/FreddyLeaf created
https://github.com/llvm/llvm-project/pull/91323
None
>From 3bab8062eb7b924234b1f4959adc0bc72fb53417 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Tue, 7 May 2024 20:57:54 +0800
Subject: [PATCH] [X86][CFE] Support EGPR in inline assembly.
---
https://github.com/FreddyLeaf closed
https://github.com/llvm/llvm-project/pull/88343
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@@ -954,6 +954,8 @@ void X86TargetInfo::getTargetDefines(const LangOptions
,
Builder.defineMacro("__CCMP__");
if (HasCF)
Builder.defineMacro("__CF__");
+ if (HasEGPR && HasPush2Pop2 && HasPPX && HasNDD)
FreddyLeaf wrote:
4929d88
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/88343
>From 88e99b1f3f99140e13f7acb8e7e10162dc1694a0 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Wed, 10 Apr 2024 16:49:05 +0800
Subject: [PATCH 1/2] [X86] Define __APX_F__ when APX is enabled.
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