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https://github.com/llvm/llvm-project/pull/91022
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@@ -85,6 +85,10 @@ def SMEUnsupported : AArch64Unsupported {
SME2Unsupported.F);
}
+def MTEUnsupported : AArch64Unsupported {
+ let F = [HasMTE];
+}
+
jthackray wrote:
Thanks for removing those. Can't see anything else obviously wrong.
https://github.com/jthackray edited
https://github.com/llvm/llvm-project/pull/91022
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@@ -85,6 +85,10 @@ def SMEUnsupported : AArch64Unsupported {
SME2Unsupported.F);
}
+def MTEUnsupported : AArch64Unsupported {
+ let F = [HasMTE];
+}
+
jthackray wrote:
Oh yes. Thanks.
https://github.com/llvm/llvm-project/pull/91022
https://github.com/jthackray approved this pull request.
LGTM. (You've still got a few FIXMEs in AArch64SchedOryon.td, I assume you know
about these)
https://github.com/llvm/llvm-project/pull/91022
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@@ -85,6 +85,10 @@ def SMEUnsupported : AArch64Unsupported {
SME2Unsupported.F);
}
+def MTEUnsupported : AArch64Unsupported {
+ let F = [HasMTE];
+}
+
jthackray wrote:
I can't see that MTEUnsupported is referenced from elsewhere in
jthackray wrote:
> The command-line names or FEAT_ names should probably be what we are aiming
> for if we are changing them one-way or the other.
Yes, standardising on FEAT_* names would be good to match the TRM, so we avoid
the
AEK_PREDRES/FEAT_SPECRES, AEK_PERFMON/FEAT_PMUv3, etc.
https://github.com/jthackray approved this pull request.
LGTM (presumably these were mechanically renamed, given the diff size).
https://github.com/llvm/llvm-project/pull/90320
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LGTM.
https://github.com/llvm/llvm-project/pull/90614
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@@ -632,7 +632,18 @@ inline constexpr CpuInfo CpuInfos[] = {
AArch64::AEK_PAUTH, AArch64::AEK_SVE2BITPERM,
AArch64::AEK_FLAGM, AArch64::AEK_PERFMON,
AArch64::AEK_PREDRES,
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/90440
>From 16f06cb0d4b84a8084e963dc7d2036ead9446a87 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Sat, 27 Apr 2024 22:51:19 +0100
Subject: [PATCH 1/4] [AArch64] Add support for Cortex-R82AE and improve
@@ -632,7 +632,18 @@ inline constexpr CpuInfo CpuInfos[] = {
AArch64::AEK_PAUTH, AArch64::AEK_SVE2BITPERM,
AArch64::AEK_FLAGM, AArch64::AEK_PERFMON,
AArch64::AEK_PREDRES,
@@ -143,6 +143,7 @@ void AArch64Subtarget::initializeProperties(bool
HasMinSize) {
case CortexA78AE:
case CortexA78C:
case CortexR82:
+ case CortexR82AE:
jthackray wrote:
Thanks, done.
https://github.com/llvm/llvm-project/pull/90440
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/90440
>From 16f06cb0d4b84a8084e963dc7d2036ead9446a87 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Sat, 27 Apr 2024 22:51:19 +0100
Subject: [PATCH 1/3] [AArch64] Add support for Cortex-R82AE and improve
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/90440
>From 16f06cb0d4b84a8084e963dc7d2036ead9446a87 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Sat, 27 Apr 2024 22:51:19 +0100
Subject: [PATCH 1/2] [AArch64] Add support for Cortex-R82AE and improve
https://github.com/jthackray edited
https://github.com/llvm/llvm-project/pull/90440
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- Fix mismatches between function parameter definitions and declarations
(#89512)
- Revert "[llvm][RISCV] Enable trailing fences for seq-cst stores by default
(#87376)"
- Revert "[RISCV] Support RISCV Atomics
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https://github.com/llvm/llvm-project/pull/90439
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- Fix mismatches between function parameter definitions and declarations
(#89512)
- Revert "[llvm][RISCV] Enable trailing fences for seq-cst stores by default
(#87376)"
- Revert "[RISCV] Support RISCV Atomics
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https://github.com/llvm/llvm-project/pull/90143
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@@ -447,6 +447,16 @@ def TuneNeoverseN2 : SubtargetFeature<"neoversen2",
"ARMProcFamily", "NeoverseN2
FeatureEnableSelectOptimize,
FeaturePredictableSelectIsExpensive]>;
+def TuneNeoverseN3 :
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/90143
>From 020b30260b501902d728fbc9a92b4bc6fa81af18 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Tue, 2 Apr 2024 22:08:50 +0100
Subject: [PATCH 1/2] [AArch64] Add support for Neoverse-N3, Neoverse-V3 and
https://github.com/jthackray created
https://github.com/llvm/llvm-project/pull/90143
Neoverse-N3, Neoverse-V3 and Neoverse-V3AE are Armv9.2 AArch64 CPUs.
Technical Reference Manual for Neoverse-N3:
https://developer.arm.com/documentation/107997/latest/
Technical Reference Manual for
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https://github.com/llvm/llvm-project/pull/87414
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>From 5ced9f33871ea66647e04f62c637b92259805c2e Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Tue, 2 Apr 2024 22:08:50 +0100
Subject: [PATCH] [AArch64] Add support for Neoverse-N3, Neoverse-V3 and
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https://github.com/llvm/llvm-project/pull/85401
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@@ -58,6 +58,7 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo
{
CortexA55,
CortexA510,
CortexA520,
+CortexA520AE,
jthackray wrote:
Yes, good idea. Amended.
https://github.com/llvm/llvm-project/pull/85401
@@ -67,6 +67,8 @@ Changes to Interprocedural Optimizations
Changes to the AArch64 Backend
--
+* Added support for Cortex-A520AE and Cortex-A720AE CPUs.
jthackray wrote:
Sure, now fixed.
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/85401
>From 4faf1f908c0c7ddef2833be3dd1b87b3abf302d8 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Thu, 14 Mar 2024 09:26:34 +
Subject: [PATCH 1/2] [AArch64] Add support for Cortex-A520AE and
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/85401
>From 4faf1f908c0c7ddef2833be3dd1b87b3abf302d8 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Thu, 14 Mar 2024 09:26:34 +
Subject: [PATCH] [AArch64] Add support for Cortex-A520AE and Cortex-A720AE
https://github.com/jthackray edited
https://github.com/llvm/llvm-project/pull/85401
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None
>From 5124e8c25660c27561586356b28ebd9252a567ed Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Thu, 14 Mar 2024 09:26:34 +
Subject: [PATCH] [AArch64] Add support for Cortex-A520AE and
https://github.com/jthackray edited
https://github.com/llvm/llvm-project/pull/85203
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https://github.com/jthackray approved this pull request.
Approved, but please find additional reviewer.
https://github.com/llvm/llvm-project/pull/85203
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jthackray wrote:
> When `+sve` is passed in the command line, if the Architecture being targeted
> is V8.6A/V9.1A or later, `+f32mm` is also added. This enables FEAT_32MM,
> however at the time of writing no CPU's support this. This leads to the
> FEAT_32MM instructions being compiled for
https://github.com/jthackray edited
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@@ -74,6 +74,7 @@ Changes to the AMDGPU Backend
Changes to the ARM Backend
--
+* FEAT_F32MM is no longer activated by default when using `+sve` on v8.6-A or
greater. The feature is still availble and can be using by adding `+f32mm` to
the command
https://github.com/jthackray edited
https://github.com/llvm/llvm-project/pull/84485
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jthackray wrote:
Linux and Windows builds are passing, but someone has left a trailing
whitespace character at clang/docs/ReleaseNotes.rst:407 (not me), so I'll merge
anyway.
https://github.com/llvm/llvm-project/pull/84485
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https://github.com/llvm/llvm-project/pull/84485
>From 40c20f5b4413bd8aac0249d4d1fc4fb4ce8c6438 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Fri, 8 Mar 2024 13:39:35 +
Subject: [PATCH 1/2] [ARM][AArch64] Add support for Arm Cortex A78AE CPU
jthackray wrote:
> Also does this address the -mcpu=native part of #84450 as well?
I've added a host id (0xd42) to llvm/lib/TargetParser/Host.cpp, so I think so
(unless there's something else required).
https://github.com/llvm/llvm-project/pull/84485
jthackray wrote:
> Should this be added to the release notes? (so it doesn't get forgotten in a
> mad scramble in a few months time)
Sure, happy to do that.
https://github.com/llvm/llvm-project/pull/84485
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None
>From 40c20f5b4413bd8aac0249d4d1fc4fb4ce8c6438 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Fri, 8 Mar 2024 13:39:35 +
Subject: [PATCH] [ARM][AArch64] Add support for Arm Cortex A78AE CPU
https://github.com/jthackray approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/81297
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jthackray wrote:
> The clang-format failures are caused by preexisting/unchanged code. All newly
> added code passes clang-format.
Yes, I had this issue when I landed new cores previously. This whole file needs
an NFC clang-format cleanup, IMHO.
@@ -784,27 +784,32 @@ inline constexpr CpuInfo CpuInfos[] = {
(AArch64::ExtensionBitset(
{AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_CRC}))},
{"tsv110", ARMV8_2A,
- (AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2,
https://github.com/jthackray edited
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https://github.com/jthackray requested changes to this pull request.
https://github.com/llvm/llvm-project/pull/81297
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jthackray wrote:
The author (Gleb) doesn't yet have llvm commit access, so has asked me to merge
it for him.
https://github.com/llvm/llvm-project/pull/80819
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https://github.com/jthackray approved this pull request.
Looks good to me.
https://github.com/llvm/llvm-project/pull/80819
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https://github.com/jthackray approved this pull request.
Good stuff, approved.
https://github.com/llvm/llvm-project/pull/80163
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https://github.com/jthackray approved this pull request.
Thanks, Lucas. I can't spot anything obviously wrong, so approved.
https://github.com/llvm/llvm-project/pull/78994
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https://github.com/jthackray approved this pull request.
No specific comments, but am in favour of this, as it reduces code complexity
and should ensure accuracy of features.
https://github.com/llvm/llvm-project/pull/78270
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https://github.com/jthackray approved this pull request.
I'm not an expert in this area, but this code LGTM.
https://github.com/llvm/llvm-project/pull/75486
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https://github.com/jthackray approved this pull request.
Looks great! :)
https://github.com/llvm/llvm-project/pull/76237
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https://github.com/jthackray approved this pull request.
+2
https://github.com/llvm/llvm-project/pull/75947
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jthackray wrote:
Long diff! Looks good to me, great work.
https://github.com/llvm/llvm-project/pull/75947
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jthackray wrote:
> Looking good. Is there a document to reference in the commit message?
Sure, I can put a link to the Technical Reference Manual
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@@ -94,6 +94,11 @@ Changes to the AArch64 Backend
* Added support for Cortex-A520, Cortex-A720 and Cortex-X4 CPUs.
+* Neoverse-N2 was incorrectly marked as an Armv8.5a core. This has been
+ changed to an Armv9.0a core. However, crypto options are not enabled
+ by default
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/75055
>From f04fea5a67c37a7ae33b611adb04733893563342 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Mon, 11 Dec 2023 14:30:46 +
Subject: [PATCH 1/2] [AArch64] Correctly mark Neoverse-N2 as an Armv9.0a
https://github.com/jthackray edited
https://github.com/llvm/llvm-project/pull/75055
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https://github.com/llvm/llvm-project/pull/75055
Neoverse-N2 was incorrectly marked as an Armv8.5a core. This has been
changed to an Armv9.0a core. However, crypto options are not enabled
by default for Armv9 cores, so `-mcpu=neoverse-n2+crypto` is required
https://github.com/jthackray closed
https://github.com/llvm/llvm-project/pull/74822
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@@ -896,9 +896,13 @@ Arm and AArch64 Support
Support has been added for the following processors (-mcpu identifiers in
parenthesis):
- * Arm Cortex-A520 (cortex-a520).
- * Arm Cortex-A720 (cortex-a720).
- * Arm Cortex-X4 (cortex-x4).
+ --target=arm
+ * Arm
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/74822
>From 5925f180b6a8623ae1f1497f89c1f6ef35517e4a Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Thu, 23 Nov 2023 15:54:01 +
Subject: [PATCH 1/5] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/74822
>From 5925f180b6a8623ae1f1497f89c1f6ef35517e4a Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Thu, 23 Nov 2023 15:54:01 +
Subject: [PATCH 1/4] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU
@@ -899,6 +899,7 @@ Arm and AArch64 Support
* Arm Cortex-A520 (cortex-a520).
* Arm Cortex-A720 (cortex-a720).
* Arm Cortex-X4 (cortex-x4).
+ * Arm Cortex-M52 (cortex-m52).
jthackray wrote:
Sure. Something like this?
```
+ --target=arm
+ * Arm
jthackray wrote:
> Going by the page (didn't see a link to a manual, maybe I missed it), MVE and
> FPU are optional.
>
> "Optional Helium technology (M-profile Vector Extension) supporting up to:"
> "Optional FPU with support for half precision (fp16), single precision (fp32)
> and double
@@ -102,7 +102,7 @@ Changes to the AMDGPU Backend
* Implemented :ref:`llvm.get.rounding `
-* Added support for Cortex-A520, Cortex-A720 and Cortex-X4 CPUs.
+* Added support for Cortex-A520, Cortex-A720, Cortex-X4 and Cortex-M52 CPUs.
jthackray wrote:
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/74822
>From 5925f180b6a8623ae1f1497f89c1f6ef35517e4a Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Thu, 23 Nov 2023 15:54:01 +
Subject: [PATCH 1/3] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/74822
>From 5925f180b6a8623ae1f1497f89c1f6ef35517e4a Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Thu, 23 Nov 2023 15:54:01 +
Subject: [PATCH 1/2] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU
https://github.com/jthackray created
https://github.com/llvm/llvm-project/pull/74822
Cortex-M52 is an Armv8.1 AArch32 CPU.
Technical specifications available at:
https://developer.arm.com/processors/cortex-m52
>From 5925f180b6a8623ae1f1497f89c1f6ef35517e4a Mon Sep 17 00:00:00 2001
From:
https://github.com/jthackray approved this pull request.
Great stuff. Looks good to me.
https://github.com/llvm/llvm-project/pull/73777
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https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/72395
>From 07b24207d100ac7d5deac76543c01710b8cab79e Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Fri, 10 Nov 2023 15:37:08 +
Subject: [PATCH 1/3] [AArch64] Add support for Cortex-A520, Cortex-A720 and
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/72395
>From 07b24207d100ac7d5deac76543c01710b8cab79e Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Fri, 10 Nov 2023 15:37:08 +
Subject: [PATCH 1/2] [AArch64] Add support for Cortex-A520, Cortex-A720 and
@@ -1351,6 +1382,11 @@ def ProcessorFeatures {
FeatureFP16FML, FeatureSVE, FeatureTRBE,
FeatureSVE2BitPerm, FeatureBF16, FeatureETE,
FeaturePerfMon, FeatureMatMulInt8,
@@ -1325,6 +1352,10 @@ def ProcessorFeatures {
FeatureMatMulInt8, FeatureBF16, FeatureAM,
FeatureMTE, FeatureETE, FeatureSVE2BitPerm,
FeatureFP16FML];
+ list A520 =
@@ -1372,6 +1408,11 @@ def ProcessorFeatures {
FeatureSPE, FeatureBF16, FeatureMatMulInt8,
FeatureMTE, FeatureSVE2BitPerm,
FeatureFullFP16,
FeatureFP16FML];
+ list X4 =
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/72395
>From 07b24207d100ac7d5deac76543c01710b8cab79e Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Fri, 10 Nov 2023 15:37:08 +
Subject: [PATCH 1/2] [AArch64] Add support for Cortex-A520, Cortex-A720 and
https://github.com/jthackray approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/72392
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https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/72395
>From 07b24207d100ac7d5deac76543c01710b8cab79e Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Fri, 10 Nov 2023 15:37:08 +
Subject: [PATCH] [AArch64] Add support for Cortex-A520, Cortex-A720 and
https://github.com/jthackray created
https://github.com/llvm/llvm-project/pull/72395
Cortex-A520, Cortex-A720 and Cortex-X4 are Armv9.2 AArch64 CPUs.
Technical Reference Manual for Cortex-A520:
https://developer.arm.com/documentation/102517/latest/
Technical Reference Manual for
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