Hey, I have an ASR9k with a 4x10GE card in a MOD80-TR. All four of the ports are in a bundle-ether.
About a week ago we began having flaps on all four of the ports in the bundle. We just yesterday started seeing messages like this: IOS XR 'STARKAD Mother Board FPGA' detected clock reference failure / DPLL unlock indicator on 'ZARLINK Bus'. Instance reporting the problem is 1 I looked up the issue, it shouldn't apply due to the software version and we don't use clock synchronization. What I am wondering is if anyone has seen this particular error message before outside of Cisco's description of what causes it? Just wondering. -Drew _______________________________________________ cisco-nsp mailing list cisco-nsp@puck.nether.net https://puck.nether.net/mailman/listinfo/cisco-nsp archive at http://puck.nether.net/pipermail/cisco-nsp/
