On 1/15/10 12:57 AM, Peter Stuge wrote:
Unfortunately, msrtool is not
currently available as payload, but perhaps coreinfo can be used to
display MSRs?
(It would be nice to have msrtool diff mode available in coreinfo,
using a file stored in cbfs for comparison!)
I think a diff mode
Hello,
I wanted to upgrade my seabios version, but some troubles arrived.
0.5.0 : keyboard timeout problem (I think)
error: ps2_recvbyte timeout
keyboard self test failed (got e0
not 0xaa)
0.5.1 : same problem as 0.5.0 and Vista don't want to boot
Hello,
What is the best way to build programs using the crossgcc tool?
I just added something like:
export PATH=$PATH:/path/to/crossgcc/bin
to my .bashrc in my home directory.
It seems to work ok, but is that the best way to use it?
--
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org
Am 15.01.2010 15:44, schrieb Joseph Smith:
Hello,
What is the best way to build programs using the crossgcc tool?
I just added something like:
export PATH=$PATH:/path/to/crossgcc/bin
to my .bashrc in my home directory.
It seems to work ok, but is that the best way to use it?
abuild
Ticket
Owner
Status
Description
#154 carldani new Flashing BIOSes from Fujitsu/Siemens is not supported
#153 stepan new resume from suspend on epia-m
#152 carldani new v3 Geode cs5536 UART2 wrongly configured
Gentlemen,
Can Coreboot support multiple PCMCIA ExpressCards like an 8
raid setup.
Will it support hot swap, hot plug-n-play and auto-configuration. Will it
enable booting an OS from an Expresscard. Will it support advance
Expresscard support.
All other Bios Firmware
Stefan,
Thanks for the review and commit !
Nils.
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
s...@coreboot.org wrote:
Support for the AMD Geode GX2 Processors to Msrtool.
It seems to work as it was tested
Please do not accept it seems to work for new register
descriptions, always review them against the available
documentation. Thanks.
//Peter
--
coreboot mailing list:
Piotr Piwko wrote:
./msrtool 0x20{18,19,1a,1b,1c,1d} 0x4c{0f,14}
OK, here is my output:
0x2018 = 0x100770144840
0x2019 = 0x18006a7332a3
0x201a = 0x130cd101
0x201b = 0x
0x201c = 0x00ff00ff
0x201d =
On 1/15/10 8:20 PM, Peter Stuge wrote:
s...@coreboot.org wrote:
Support for the AMD Geode GX2 Processors to Msrtool.
It seems to work as it was tested
Please do not accept it seems to work for new register
descriptions, always review them against the available
documentation.
Stefan Reinauer wrote:
Please do not accept it seems to work for new register
descriptions,
I figured nobody has the time to check this, not even the author of
msrtool.
Someone else using GX2 might hav been motivated (though they didn't
speak up so far) or after the reminder maybe someone
On Fri, 15 Jan 2010 21:27:15 +0100, Stefan Reinauer ste...@coresystems.de
wrote:
On 1/15/10 8:20 PM, Peter Stuge wrote:
s...@coreboot.org wrote:
Support for the AMD Geode GX2 Processors to Msrtool.
It seems to work as it was tested
Please do not accept it seems to work for new register
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Hello,
While thinking how to implement the resume without memory hole I came cross
following piece of code in AMD CAR:
set_init_ram_access(); /* So we can access RAM from [1M, CONFIG_RAMTOP) */
print_debug(Copying data from cache to RAM --
#133: Create a typical failures FAQ
+---
Reporter: stuge| Owner: somebody
Type: enhancement |Status: closed
Priority: major| Milestone:
#123: layout file
+---
Reporter: viva...@…| Owner: somebody
Type: defect |Status: closed
Priority: major| Milestone: flashrom
#119: Winbond W39V040FBPZ is not written correctly by flashrom
-+--
Reporter: charles.hern...@… | Owner: somebody
Type: enhancement| Status: new
#103: flashrom: Add -T to test all operations in one invocation
-+--
Reporter: stuge | Owner: hailfinger
Type: enhancement| Status: new
Priority: major
#106: flashrom: Add -T to automatically test all flash chip operations
+---
Reporter: stuge| Owner: somebody
Type: enhancement |Status: closed
Priority: major
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Thanks for the analysis. I can see it being useful for other things too.
Ok.
My understanding was that CAR refers to L2. As long as nothing gets
replaced from the L2, everything is as it should be. ROM contents can
always be fetched again, so
coreboot wrote:
* resolution: = fixed
Comment:
This has been solved by making the libpci check conditional on actually
needing libpci (i.e. not for the serial and USB and dummy flashers).
I disagree with this. The point was to create a configure script and
check for pciutils one time
My understanding was that CAR refers to L2. As long as nothing gets
replaced from the L2, everything is as it should be. ROM contents can
always be fetched again, so that's not critical for correctness.
This is OK, but L2 CAR is in more detail described in fam11h otherwise AMD
always
It clearly shows that L2 is used for this kind of things. Was this
intended? The
L2 I think contains also the cached ROM code... so situation is bit more
complicated than one can expect.
Thanks for the analysis. I can see it being useful for other things too.
My understanding was that CAR
#120: flashrom: ICH SPI Hardware Sequencing
-+--
Reporter: t...@… | Owner: stuge
Type: enhancement| Status: assigned
Priority: major |
#104: flashrom: Partial operations; change flash drivers to not erase in the
write function
---+
Reporter: stuge| Owner: hailfinger
Type: enhancement | Status: new
#104: flashrom: Partial operations; change flash drivers to not erase in the
write function
---+
Reporter: stuge| Owner: hailfinger
Type: enhancement | Status: new
On 16.01.2010 00:55, Peter Stuge wrote:
coreboot wrote:
* resolution: = fixed
Comment:
This has been solved by making the libpci check conditional on actually
needing libpci (i.e. not for the serial and USB and dummy flashers).
I disagree with this. The point was to create
#104: flashrom: Partial operations; change flash drivers to not erase in the
write function
---+
Reporter: stuge| Owner: hailfinger
Type: enhancement | Status: new
#104: flashrom: Partial operations; change flash drivers to not erase in the
write function
---+
Reporter: stuge| Owner: hailfinger
Type: enhancement | Status: new
#104: flashrom: Partial operations; change flash drivers to not erase in the
write function
---+
Reporter: stuge| Owner: hailfinger
Type: enhancement | Status:
#104: flashrom: Partial operations; change flash drivers to not erase in the
write function
---+
Reporter: stuge| Owner: hailfinger
Type: enhancement | Status:
On Fri, Jan 15, 2010 at 02:27:39PM +0100, conged...@voila.fr wrote:
Hello,
I wanted to upgrade my seabios version, but some troubles arrived.
0.5.0 : keyboard timeout problem (I think)
error: ps2_recvbyte timeout
keyboard self test failed (got
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