Re: [coreboot] Regarding How-To for new board support

. This keeps popping up regularly. To prevent people wasting there and your time in the future maybe someone with wiki write rights (you?) could edit the Will coreboot work on my machine? alinea in the coreboot FAQ: http://www.coreboot.org/FAQ Greetings, Nils. -- coreboot mailing list: coreboot

Re: [coreboot] tiny bootblock problem

of the GX2 databook.:) Philip Prindeville wrote: Caching is bits 30:29 of CR0. There are actually a lot more MSR registers for defining cache regions. Thanks, Nils. attachment: GX2_MTRR-- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] tiny bootblock problem

to get it right? Thanks, Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Current status of WYSE S50 support

doesn't work. No ACPI. (no real problem when you don't use suspend) Beeper doesn't work. Flashrom works. If you want an experimental coreboot rom image send me a mail. Greetings, Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [msrtool] Bug report

tracking system does not seem to know msrtool. Thanks, Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [msrtool] Bug report

have a new mail address. Thanks, Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] Coreboot on AMD Geode; No VGA

Hi Andrew, As i understand it the description of the problem belongs to the previous V2 version of the VGA patch witch this V3 version (at the bottom off the tread) together with the mode hack patch (little patch to vgatables.c) addresses. Thanks, Nils. -- coreboot mailing list: coreboot

[coreboot] Coreboot on AMD Geode; No VGA

in Seabios. Thanks, Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Wyse S10

, Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Using lpgcc

that way on my Debian system. Following the readme i only downloaded libpayload and put my example file (hello.c + makefile) in the directory /hello : nils@debian:~$ svn co svn://coreboot.org/repos/trunk/payloads/libpayload Alibpayload/crypto Alibpayload/crypto/Makefile.inc Alibpayload

[coreboot] [PATCH] Update libpayload repo in readme

Update repo path in libpayload readme. Signed-off-by: Nils Jacobs njaco...@hetnet.nl Thanks, Nils. Index: README === --- README (revision 6468) +++ README (working copy) @@ -14,7 +14,7 @@ Installation - $ svn co svn

Re: [coreboot] Using lpgcc

error output on my computer. More suggestions? Thanks, Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Using lpgcc

Unfortunately the updated repo r6468 gives exactly the same error output on my computer. More suggestions? To clarify this a little: This command works: nils@debian:~/hello$ /home/nils/libpayload/install/libpayload/bin/lpgcc -o hello.elf hello.c And the basename error seems to be gone now

[coreboot] Using lpgcc

hello all, After building and installing libpayload i tried building the test program hello.c . Unfortunately i got a (error?) message: nils@debian:~/hello$ /opt/libpayload/bin/lpgcc -o hello.elf hello.c basename: missing operand Try `basename --help' for more information. Is this something i am

[coreboot] HT1000 USB problem?

://bugzilla.redhat.com/show_bug.cgi?id=227657 https://bugzilla.redhat.com/show_bug.cgi?id=205520 Thanks, Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] JCALG1 archive

Hello All, I have a rom image witch contains an JCALG1 archive. I would like to know what it contains , does anyone know of a ready to use tool that can extract an JCALG1 archive? Thanks, Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [commit] r6418 - trunk/src/northbridge/amd/lx

the UART fifos (if any) and also Should this change also be applied for the almost same function in Geode GX2? Thanks,Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] abuild error

Hi Scott and Stefan, Scott wrote: Hello Nils, If I build ts5300 using xgcc 4.5.1, I get: Fixed space: 0xe05b-0x1 total: 8101 slack: 2 Percent slack: 0.0% 16bit size: 38896 32bit segmented size: 2416 32bit flat size: 51424 Linking out/rom16.o Stripping out

Re: [coreboot] abuild error

systems the crosgcc is useless as reference. Thanks, Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] abuild error

% (128KiB rom) Thanks, Scott Thanks for your answer. Which coreboot revision and board did you use? Is that the technologic/ts5300 which gives me trouble? Are these numbers including SeaBios which is nowadays automatically included as payload? Thanks, Nils. -- coreboot mailing list: coreboot

Re: [coreboot] [MSRTOOL] [PATCH] Add Geode GX2 memmory desriptor registers.

Hi Stefan, Op woensdag 19 januari 2011 07:56:53 schreef u: * Nils njaco...@hetnet.nl [110113 15:42]: Add Geode GX2 memmory descriptors. Add a simple README file. Signed-off-by: Nils Jacobs njaco...@hetnet.nl Thanks, Nils. Thanks, r6274 Thanks for the review and committing

Re: [coreboot] [PATCH] Geode GX2 Kconfig framebuffer choice

and committing. Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Geode GX2 VGA problems

? Thanks, Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [PATCH] Geode GX2 Kconfig framebuffer choice

Add a GX2 Kconfig option to choose the framebuffer size. Signed-off-by: Nils Jacobs njaco...@hetnet.nl This patch is buid and boot tested. Hi Peter, You wrote: +config VIDEO_MB + int + default 8 + depends on NORTHBRIDGE_AMD_GX2 + Acked-by: Peter Stuge peter at stuge.se

Re: [coreboot] abuild error

OK i have done some more hours of building and testing. After i do buildgcc there is no .xcompile file. After doing make menuconfig i have the following .xcompile file: |nils@debian:~/coreboot_6255$ cat .xcompile |# elf32-i386 toolchain |AS:=/home/nils/coreboot_6255/util/crossgcc/xgcc/bin/i386

Re: [coreboot] abuild error

Hi Stefan, You wrote: It doesn't occur with the coreboot toolchain iirc though I did a fresh unmoddified checkout on r6255. Then i did buildgcc. The downloading/building of this beast takes more than an hour on my old laptop. :) Then i got the same result: nils@debian:~/coreboot_6255$ util

Re: [coreboot] abuild error

in coreboot/util/crossgcc no .xcompile i have tried: in coreboot dir /home/nils/coreboot/util/crossgcc/buildgcc this builds xgcc in coreboot dir but no .xcompile I could not find any documentation on how to use this. It would be nice if someone could shed some light on this. Thanks, Nils

[coreboot] [MSRTOOL] [PATCH] Add Geode GX2 memmory desriptor registers.

Add Geode GX2 memmory descriptors. Add a simple README file. Signed-off-by: Nils Jacobs njaco...@hetnet.nl Thanks, Nils. Index: geodegx2.c === --- geodegx2.c (revision 6228) +++ geodegx2.c (working copy) @@ -26,6 +26,592

[coreboot] Geode GX2 VGA problems

VSA2 or VGAbios can not find them? I don't know how this exactly works and maybe i am doing something stupid but maybe someone could give me any advise on how to debug this further. Thanks, Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] abuild error

) Could not add the file to CBFS, it's probably too big. File size: 46723 bytes (45 KB). make: *** [coreboot-builds/technologic_ts5300/coreboot.rom] Fout 1 Is this a known problem? Thanks, Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH 2/7] Geode GX2 cleanup next round

Change the print_conf activation from =BIOS_ERR to =BIOS_DEBUG. Signed-off-by: Nils Jacobs njaco...@hetnet.nl Op donderdag 30 december 2010 02:44:12 schreef u: On Wed, Dec 29, 2010 at 4:46 PM, Nils njaco...@hetnet.nl wrote: Op woensdag 29 december 2010 21:44:08 schreef u: On Wed, Dec 29

Re: [coreboot] [commit] r6221 - in trunk/src: include/cpu/amd mainboard/amd/rumba mainboard/lippert/frontrunner mainboard/wyse/s50 northbridge/amd/gx2 southbridge/amd/cs5535

. Signed-off-by: Nils Jacobs njaco...@hetnet.nl Acked-by: Myles Watson myle...@gmail.com Any idea why this broke the lippert frontrunner? http://qa.coreboot.org/log_buildbrd.php?revision=6222device=frontrunnerve ndor=lippertnum=2 See previous message. My older patch was not yet committed

Re: [coreboot] build service results for r6222

. And maybe also: [coreboot] [PATCH 3/6 V2] Geode GX2 cleanup patch Thanks, Nils. It seems that part of this older patch : [coreboot] [PATCH 4/6 V2] Geode GX2 cleanup patch is already commited by Myles. So i will send a updated patch. Thanks, Nils. -- coreboot mailing list: coreboot@coreboot.org http

[coreboot] [PATCH 4/6 V3] Geode GX2 cleanup patch

Remove duplicated GX2 processor IIOC mode setting on CS5535 southbridge code and fix CIS mode comments. Signed-off-by: Nils Jacobs njaco...@hetnet.nl V2: Add a extra comment. V3: Remove already commited part. Thanks, Nils. Index: src/southbridge/amd/cs5535/early_setup.c

Re: [coreboot] [PATCH 4/6 V3] Geode GX2 cleanup patch

I wrote: Remove duplicated GX2 processor IIOC mode setting on CS5535 southbridge code and fix CIS mode comments. Signed-off-by: Nils Jacobs njaco...@hetnet.nl V2: Add a extra comment. V3: Remove already commited part. Thanks, Nils. This can be dropped, Stefan already committed

[coreboot] [PATCH 0/2] Geode GX2 cleanup again

Hello all, Here comes the next round of patches for Geode GX2. This patch set is ABUILD and boot tested on my Wyse S50 . The second patch depends on the first one to cleanly apply. Thanks, Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [PATCH 1/2] Geode GX2 cleanup again

For gx2/northbridgeinit.c -some white space fixes -some codingstyle fixes -some comment fixes. Signed-off-by: Nils Jacobs njaco...@hetnet.nl Thanks, Nils. Index: src/northbridge/amd/gx2/northbridgeinit.c === --- src/northbridge/amd

[coreboot] [PATCH 2/2] Geode GX2 cleanup again

-update gx2/northbridgeinit.c to lx standards -remove not longer needed code from gx2/northbridge.c Signed-off-by: Nils Jacobs njaco...@hetnet.nl Thanks, Nils. Index: src/northbridge/amd/gx2/northbridge.c === --- src/northbridge

[coreboot] [PATCH 0/7] Geode GX2 cleanup next round

Hello all, Here comes the next round of split up and updated patches for Geode GX2. This patch set is ABUILD and boot tested on my Wyse S50 in combination with the 2 not yet committed patches from the previous round. Thanks, Nils. -- coreboot mailing list: coreboot@coreboot.org http

[coreboot] [PATCH 1/7] Geode GX2 cleanup next round

-by: Nils Jacobs njaco...@hetnet.nl Thanks, Nils. Index: src/include/cpu/amd/gx2def.h === --- src/include/cpu/amd/gx2def.h (revision 6218) +++ src/include/cpu/amd/gx2def.h (working copy) @@ -77,7 +77,6 @@ #define GL1_GLCP 3 #define

[coreboot] [PATCH 2/7] Geode GX2 cleanup next round

Add a MSR printing function to northbridge.c like in the Geode LX code. Signed-off-by: Nils Jacobs njaco...@hetnet.nl Thanks, Nils. Index: src/southbridge/amd/cs5535/cs5535.h === --- src/southbridge/amd/cs5535/cs5535.h (revision

[coreboot] [PATCH 4/7] Geode GX2 cleanup next round

-Remove the AES register names.(GX2 has no AES registers) Signed-off-by: Nils Jacobs njaco...@hetnet.nl Thanks, Nils. Index: src/include/cpu/amd/gx2def.h === --- src/include/cpu/amd/gx2def.h (revision 6218) +++ src/include/cpu/amd

[coreboot] [PATCH 3/7] Geode GX2 cleanup next round

-Clean up some comments. -Remove some white spaces. -Remove some leading zeros. -Fix a typo in LX code. Signed-off-by: Nils Jacobs njaco...@hetnet.nl Thanks, Nils. Index: src/southbridge/amd/cs5535/cs5535.h === --- src/southbridge

Re: [coreboot] [PATCH 7/7] Geode GX2 cleanup next round

Hi Myles, Thanks for reviewing and committing my patches. Op woensdag 29 december 2010 21:42:39 schreef u: On Wed, Dec 29, 2010 at 12:05 PM, Nils njaco...@hetnet.nl wrote: Move hardcoded IRQ defining from northbridge.c to irq_tables.c . There's also an added init function for the WYSE

Re: [coreboot] [PATCH 2/7] Geode GX2 cleanup next round

Op woensdag 29 december 2010 21:44:08 schreef u: On Wed, Dec 29, 2010 at 12:04 PM, Nils njaco...@hetnet.nl wrote: Add a MSR printing function to northbridge.c like in the Geode LX code. It's surprising to have it included +#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL = BIOS_ERR but then have

Re: [coreboot] [PATCH 4/6] Geode GX2 cleanup patch

.(see above) Thanks, Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [PATCH 4/6 V2] Geode GX2 cleanup patch

Remove duplicated GX2 processor IIOC mode setting on CS5535 southbridge code and fix CIS mode comments. Signed-off-by: Nils Jacobs njaco...@hetnet.nl V2: Add a extra comment. Thanks, Nils. Index: src/southbridge/amd/cs5535/early_setup.c

[coreboot] [PATCH 6/6] Geode GX2 cleanup patch

Move VIDEO_MB to Kconfig. Signed-off-by: Nils Jacobs njaco...@hetnet.nl Thanks, Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [PATCH 6/6] Geode GX2 cleanup patch

Sorry i pushed the wrong button. Disregard my last mail for now. Thanks, Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [PATCH 0/6] Geode GX2 cleanup patch

Hello all, I finally had a little time to work on further splitting up and updating my patches for Geode GX2. This patch set is ABUILD and boot tested on my Wyse S50. Thanks, Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [PATCH 2/6] Geode GX2 cleanup patch

Replace some MSR register numbers with names. Signed-off-by: Nils Jacobs njaco...@hetnet.nl Thanks, Nils. Index: src/include/cpu/amd/gx2def.h === --- src/include/cpu/amd/gx2def.h (revision 6205) +++ src/include/cpu/amd/gx2def.h

[coreboot] [PATCH 3/6] Geode GX2 cleanup patch

Add a while (1) function around the hlt instruction to assure the processor can't wake up from an interrupt. Signed-off-by: Nils Jacobs njaco...@hetnet.nl This was suggested by Uwe Hermann. Thanks! I also included the same patch for Geode LX. Nils. Index: src/northbridge/amd/gx2/pll_reset.c

[coreboot] [PATCH 4/6] Geode GX2 cleanup patch

Remove wrong GX2 processor IIOC mode setting on CS5535 southbridge code and fix CIS mode comments. Signed-off-by: Nils Jacobs njaco...@hetnet.nl Thanks, Nils. Index: src/southbridge/amd/cs5535/early_setup.c === --- src/southbridge

[coreboot] [PATCH 5/6] Geode GX2 cleanup patch

Delete some unused code. Signed-off-by: Nils Jacobs njaco...@hetnet.nl Thanks, Nils. Index: src/cpu/amd/model_gx2/cpureginit.c === --- src/cpu/amd/model_gx2/cpureginit.c (revision 6205) +++ src/cpu/amd/model_gx2/cpureginit.c

[coreboot] [PATCH 6/6] Geode GX2 cleanup patch

Move VIDEO_MB to Kconfig. Signed-off-by: Nils Jacobs njaco...@hetnet.nl Thanks, Nils. Index: src/northbridge/amd/gx2/Kconfig === --- src/northbridge/amd/gx2/Kconfig (revision 6205) +++ src/northbridge/amd/gx2/Kconfig (working copy

Re: [coreboot] [PATCH] Geode GX2 print(k) V2

Op vrijdag 5 november 2010 01:14:03 schreef u: On Thu, Nov 04, 2010 at 11:35:56PM +0100, Nils wrote: Remove banner wrapper function and unify print(k). Signed-off-by: Nils Jacobs njaco...@hetnet.nl Thanks, 6021. Uwe. Thanks for the review and commit. Nils. -- coreboot mailing

Re: [coreboot] [PATCH] Add cpu speed selection to Geode GX2 boards

Op vrijdag 5 november 2010 01:23:48 schreef u: On Tue, Nov 02, 2010 at 10:33:44PM +0100, Nils wrote: This patch adds Kconfig cpu speed selection to Geode GX2 boards as requested by Uwe. Signed-off-by: Nils Jacobs njaco...@hetnet.nl Thanks, r6023. Uwe. Thanks for the review

Re: [coreboot] [PATCH] Define unused DIMM1 to 0xFF on Geode GX2 boards

Op vrijdag 5 november 2010 01:20:03 schreef u: On Tue, Nov 02, 2010 at 10:33:22PM +0100, Nils wrote: This patch defines the unused DIMM1 to 0xFF to make it obvious it is a bogus value. Signed-off-by: Nils Jacobs njaco...@hetnet.nl Thanks, r6022. I added some comments too to make

Re: [coreboot] [PATCH 0/4] Geode GX2 auto DRAM detect patch V2

Op vrijdag 5 november 2010 01:29:52 schreef u: On Mon, Nov 01, 2010 at 08:28:27PM +0100, Nils wrote: Shouldn't there be a while (1) around the hlt instruction? ?? i don't know should it? The code seems to work, but if it is preferred/needed i will add it. As far as I know the hlt

[coreboot] [PATCH] Geode GX2 print(k) V2

Remove banner wrapper function and unify print(k). Signed-off-by: Nils Jacobs njaco...@hetnet.nl The banner part was requested by Uwe. This is Abuild and boot tested. V2:Also change Assymetirc into Asymmetric thanks to Idwer for spotting. Thanks, Nils. Index: src/northbridge/amd/gx2/raminit.c

Re: [coreboot] [PATCH] Geode GX2 comment cleanup 1

Op woensdag 3 november 2010 14:20:31 schreef u: Thanks, r6014 with some further cosmetic fixes I noticed. Uwe. Thanks for the fast review and commit. Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] Geode GX2 comment cleanup 2

Hi Uwe, Op woensdag 3 november 2010 14:23:36 schreef u: Thanks, r6015 Thanks for the fast review and commit. Clean up stuff looks better than This patch cleans up stuff in svn logs. OK will do better next time. Thanks, Nils. -- coreboot mailing list: coreboot@coreboot.org http

Re: [coreboot] [PATCH] Remove unused code from Geode GX2

Uwe wrote, Op woensdag 3 november 2010 14:24:47 schreef u: Thanks, r6016. Thanks for the fast review and commit. Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [PATCH] Geode GX2 print(k)

Remove banner wrapper function and unify print(k). Signed-off-by: Nils Jacobs njaco...@hetnet.nl The banner part was requested by Uwe. This is Abuild and boot tested. Thanks, Nils. Index: src/northbridge/amd/gx2/raminit.c

[coreboot] [PATCH] Geode GX2 comment cleanup 1

This patch cleans up some comments and white space in gx2/northbridgeinit.c and gx2/raminit.c. Signed-off-by: Nils Jacobs njaco...@hetnet.nl This is Abuild and boot tested. Thanks, Nils. Index: src/northbridge/amd/gx2/raminit.c

[coreboot] [PATCH] Geode GX2 comment cleanup 2

This patch cleans up some more comments and white space in model_gx2/cpureginit.c . Signed-off-by: Nils Jacobs njaco...@hetnet.nl This is Abuild and boot tested. Thanks, Nils. Index: src/cpu/amd/model_gx2/cpureginit.c === --- src

[coreboot] [PATCH] Define unused DIMM1 to 0xFF on Geode GX2 boards

This patch defines the unused DIMM1 to 0xFF to make it obvious it is a bogus value. Signed-off-by: Nils Jacobs njaco...@hetnet.nl This was requested by Myles. This is Abuild and boot tested. Thanks, Nils. Index: src/mainboard/wyse/s50/romstage.c

[coreboot] [PATCH] Remove unused code from Geode GX2

This patch removes some unused code from gx2/raminit.c . Signed-off-by: Nils Jacobs njaco...@hetnet.nl This is Abuild and boot tested. Thanks, Nils. Index: src/northbridge/amd/gx2/raminit.c === --- src/northbridge/amd/gx2/raminit.c

[coreboot] [PATCH] Add cpu speed selection to Geode GX2 boards

This patch adds Kconfig cpu speed selection to Geode GX2 boards as requested by Uwe. Signed-off-by: Nils Jacobs njaco...@hetnet.nl This is Abuild and boot tested. Thanks, Nils. Index: src/mainboard/wyse/s50/Kconfig === --- src

[coreboot] print(k) question

Hi all, Could someone explain the difference between printk(BIOS_EMERG, message\n) and print_emerg(message\n) and witch one is preferred? Thanks, Nils -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH 0/4] Geode GX2 auto DRAM detect patch V2

) around the hlt instruction? ?? i don't know should it? The code seems to work, but if it is preferred/needed i will add it. Can you point me to some example code or could you supply some code snipped i can test? Thanks, Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org

[coreboot] [PATCH 1/4] Geode GX2 auto DRAM detect patch V2

This patch changes the MSR register numbers in to more descriptive names. Signed-off-by: Nils Jacobs njaco...@hetnet.nl Thanks, Nils Index: src/northbridge/amd/gx2/raminit.c === --- src/northbridge/amd/gx2/raminit.c (revision 6006

[coreboot] [PATCH 2/4] Geode GX2 auto DRAM detect patch V2

This patch cleans up some white space and comments. It also adds a copyright header to pll_reset.c . Signed-off-by: Nils Jacobs njaco...@hetnet.nl Thanks, Nils. Index: src/include/cpu/amd/gx2def.h === --- src/include/cpu/amd

[coreboot] [PATCH 4/4] Geode GX2 auto DRAM detect patch V2

) Signed-off-by: Nils Jacobs njaco...@hetnet.nl Thanks, Nils. Index: src/include/cpu/amd/gx2def.h === --- src/include/cpu/amd/gx2def.h (revision 6006) +++ src/include/cpu/amd/gx2def.h (working copy) @@ -412,6 +412,13 @@ #define

[coreboot] [PATCH 3/4] Geode GX2 auto DRAM detect patch V2

This patch removes some unused code. Signed-off-by: Nils Jacobs njaco...@hetnet.nl Index: src/northbridge/amd/gx2/pll_reset.c === --- src/northbridge/amd/gx2/pll_reset.c (revision 6006) +++ src/northbridge/amd/gx2/pll_reset.c

[coreboot] [PATCH 0/4] Geode GX2 auto DRAM detect patch V2

This patch series splits up the Geode GX2 auto DRAM detect patch into 4 patches as requested. It should be easy to review now. The patches are Abuild and boot tested on my Wyse S50 . They should be applied in this order. Thanks, Nils. -- coreboot mailing list: coreboot@coreboot.org http

Re: [coreboot] [PATCH] Geode GX2 auto DRAM detect patch

I am happy to see there is still some interest in GX2 patches. I will try to split the patch up in 2-3 patches. Unfortunately i will probably have very little time for hobby next week so it can take a while. Thanks, Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org

Re: [coreboot] [PATCH] Geode GX2 auto DRAM detect patch

,Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] Geode GX2 auto DRAM detect patch

‘sdram_set_spd_registers’: src/northbridge/amd/gx2/raminit.c:482: error: ‘DIMM1’ undeclared (first use in this function) make: *** [build/mainboard/wyse/s50/romstage.pre.inc] Fout 1 n Thanks,Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] Geode GX2 auto DRAM detect patch

fine with me. Should i redo the patch for that? Thanks, nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] Geode GX2 auto DRAM detect patch

***Ping*** It would be nice if someone finds the time to ack/commit or comment my patch. On 10/7/10 , Nils wrote: This patch brings the adapted Geode LX auto DRAM detect code to GX2 , cleans up some files and adds a processor speed setting function in human readable Mhz. Signed-off-by: Nils

[coreboot] [PATCH] Geode GX2 auto DRAM detect patch

This patch brings the adapted Geode LX auto DRAM detect code to GX2 , cleans up some files and adds a processor speed setting function in human readable Mhz. Signed-off-by: Nils Jacobs njaco...@hetnet.nl It is Abuild and boot tested on my Wyse S50 with 3 different SODIMMs (128Mb pc2700, 256Mb

Re: [coreboot] [commit] r5872 - in trunk/src/mainboard: . olpc

(europe)? Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] Move CAR config from mainboard to CPU config for AMD GX2 boards.

Hi Warren, I think you forgot to convert the rest of the GX2 boards. :) (AMD Rumba, Lippert Frontrunner, OLPC btest and OLPC rev_a) And when you are at it should ARCH_X86 and UDELAY_TSC also be moved? Thanks, Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org

[coreboot] FrontRunner and OLPC memory type?

of the parameters but it would be better to use the exact parameters. So if someone could give me the type numbers for the used SDRAM chips i can search for datasheets and implement the right timing numbers. Thanks,Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman

Re: [coreboot] Wyse S50

. It`s still on my to do list. Thanks,Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] Geode GX2 post code patch

Hi Peter, Peter wrote: r5671 Thanks for committing the patch. Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] Convert Geode GX2 boards to CAR

Hi Joseph and Peter, Thanks for commiting my patch. Now i can dig up the next patch. Thanks,Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [PATCH] Geode GX2 post code patch

This patch lets Geode GX2 use geode_post_code.h just like LX and cleans up gx2def.h and geode_post_code.h a little. It is abuild tested and boot tested on my Wyse S50. Signed-off-by: Nils Jacobs njaco...@hetnet.nl Acked-by: Nils Jacobs njaco...@hetnet.nl (trivial) As this is a trivial patch

Re: [coreboot] Broken include paths

/file.h to make it obvious that they're not in src/include Abuild tested. Signed-off-by: Myles Watson mylesgw at gmail.com I like that. Acked-by: Nils Jacobs njaco...@hetnet.nl Thanks,Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] Convert Geode GX2 boards to CAR

to buy type 1MB SIMM to expand my Philips 386 pc to 2MB! That were times. Nowadays i make my circuits mostly on breadboard. Nils. Ps:I hear that nowadays you can order PCB`s real cheap in china. But i didn`t use it for my simple designs yet as i found the shipping cost for 1 PCB to high

Re: [coreboot] [PATCH] Convert Geode GX2 boards to CAR

Hi Joseph, Op vrijdag 16 juli 2010 14:41:47 schreef u: On Tue, 6 Jul 2010 20:27:12 +0200, Nils njaco...@hetnet.nl wrote: Ping!? Could anybody tell me how to proceed? Peter:did i gave the wrong answers? :) Thanks,Nils. Nils, I really would hate to see your great work go to the way

Re: [coreboot] [PATCH] Convert Geode GX2 boards to CAR

Ping!? Could anybody tell me how to proceed? Peter:did i gave the wrong answers? :) Thanks,Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] Convert Geode GX2 boards to CAR

Hi All, Nils wrote: Peter wrote: Nils wrote: +++ src/cpu/amd/model_gx2/cache_as_ram.inc(revision 0) .. + post_code(0xc5) +DCacheSetupBad: + hlt /* issues */ + jmp DCacheSetupBad Should this maybe fail more loudly than a POST code, which can be disbled completely

Re: [coreboot] [PATCH] Convert Geode GX2 boards to CAR

satisfied . Thanks,Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] Name change leftovers ?

Hi Stefan, I found some references to LinuxBios on the Trac roadmap page you might want to change ? http://tracker.coreboot.org/trac/coreboot/roadmap Thanks,Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Geode GX2 CAR.

Hi Marc, Op maandag 21 juni 2010 21:35:04 schreef u: Nils, I don't think that the GX2 has that bug and the register bit definitions are completely different. I would leave it out. Marc Ok i understand that it is a LX silicon bug and i wil leave it out. Thanks for the advice. Nils

[coreboot] Geode GX2 CAR.

a similar test be needed/desired for GX2 ? Thanks,Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Minor update on IDE mode on Wyse S10 (CS5536)

coreboot you can enable or disable flash_enable. Normaly it is disabled so you can use IDE.(But for your flash drive i think you want flash enabled) With coreboot you can use a normal recent kernel with the appropriate drivers. Succes,Nils -- coreboot mailing list: coreboot@coreboot.org http

Re: [coreboot] [PATCH] Wyse S50 RAMBASE 0x100000 fix

. Stefan wrote: Why 1F6BF000 ? I extracted that value from the original bios with MSRtool , and it worked. If you have a better setting and / or patch i will be glad to test it. Thanks,Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

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