[coreboot] [MSRTOOL][PATCH] Add Geode GX2 processor support.

Hello all, The attached patch (for review) brings support for the AMD Geode GX2 processors to Msrtool. It seems to work as i tested it on my Wyse Winterm S50. Signed-off-by: Nils Jacobs njaco...@hetnet.nl Msrtool -l -s output(+ File attached): msrtool 4966M Detected system linux: Linux

[coreboot] VSA2 source?

Hi all, I am looking for the latest geode vsa2 , and the only source i found seems down.(http://marcjonesconsulting.com/gplvsa/gpl_vsa_lx_102.bin.gz) Would it be possible to mirror it on coreboot.org? Thanks,Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman

[coreboot] coreboot and MSM800BEV

on my (non-CAR) board at revision r4992 and the problem disappeared at r4995. So it might be worth a try to test a newer revision. Good luck!,Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [PATCH] Repair vsmsetup on GX2

The attached patch fixes vsmsetup for the AMD GX2 . It was broken at least since rev 4611. This patch is newconfig build and boot tested, it now gives a : VSA2 VR signature verified message. Signed-off-by: Nils Jacobs njaco...@hetnet.nl There is at least one little problem with this patch

[coreboot] [PATCH] Repair vsmsetup on GX2

Hi Patrick, Thanks for the hint. But it does`t seem to help if i add this to /amd/rumba/Kconfig : config RAMBASE hex default 0x4000 depends on BOARD_AMD_RUMBA Do you have more hints or was it not wat you meant? Thanks,Nils. -- coreboot mailing list: coreboot

[coreboot] [PATCH-v2] Repair vsmsetup on GX2

(mostly copy and paste) i won`t be able to follow your suggestions. I hope someone else knows how and has the time to do it. Thank,Nils. P.s. My patch for MSRTOOL from some time ago has had not much interest also. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman

[coreboot] [MSRTOOL][PATCH] Add Geode GX2 processor support.

Stefan, Thanks for the review and commit ! Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Warnings

it to work anymore on rev5120 and some other rev`s i tried. (Linux errors out with: hda: lost interrupt) I will send the details in a separate mail. Thanks,Nils -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] GX2 problems

Hi Joseph, Op zaterdag 1 mei 2010 21:34:19 schreef u: Hey Nils, I just acquired as S30, which is the same as the S50 but less onboard flash/memory :-) Very nice! The more people working on it the better. I hope the GX2 tree is working again soon. P.s. i forgot to mention there is another

Re: [coreboot] GX2 problems

ok. After long experimenting i found a kernel config that seems to work only on kernel 2.6.24 and enables the hdd on the flash interface. Probably a bug in 2.6.24. I use that kernel for flashing. If you need that give me a pm. Greetings,Nils. -- coreboot mailing list: coreboot@coreboot.org http

Re: [coreboot] [PATCH] improve realmode api

oopses. I will not ack nor nack because i know to little about programming. Thanks,Nils. Last part of rev5532 + improve realmode api patch: sizeram: sizem 0x200 setup_gx2_cache: enable for 524288 KB msr 0x1808 will be set to 25fff002:11ffe000 MSR 0x1026 is now 0x2dfbe040:0x400fffe0

Re: [coreboot] [PATCH] improve realmode api

Hi, During my investigations i found this Geode GX2 hardware bug discription, could that have anything to do with my problems? Thanks,Nils. AMD Geode™ GX Processors Silicon Revision 2.1 Specification Update: 1.15 Limit fault during exception in SMM with unreal code segment Description: When

Re: [coreboot] GX2 problems

Op zondag 9 mei 2010 00:00:22 schreef u: xULL; // Enable reads for C-F setShadow(shadowSettings); } What's this doing? Is it potentially dangerous for other systems? I was strugling with memory regions and saw this in the LX code. -- coreboot mailing list:

Re: [coreboot] [commit] r5533 - in trunk/src/mainboard: . wyse wyse/s50

have changed the memmory region setup to match the LX boards. I wil send a patch for that later. Thanks,Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Warnings

Op zondag 9 mei 2010 00:36:49 schreef u: On 5/1/10 1:34 AM, Nils wrote: Hi Stefan, First of all thanks for the great improvements in Geode (GX2). On 4/30/10 7:50 PM, Stefan Reinauer wrote: src/northbridge/amd/gx2/chipsetinit.c:271: warning: suggest parentheses around '-' inside

[coreboot] [PATCH] improve realmode api

a patch, but i haven`t had time. I am focusing on the board till now. Thanks,Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] improve realmode api

Op zondag 9 mei 2010 00:41:06 schreef u: Attached a log from rev5470. cool thanks... could you send one for 5471 too, please? Here you go, attached. Nils. coreboot-4.0-r5471M-v5471_145 Wed May 5 23:09:30 CEST 2010 starting... POST: 0xa0 POST: 0xa1 coreboot-4.0-r5471M-v5471_145 Wed

Re: [coreboot] wyse s50

Op zondag 9 mei 2010 14:42:54 schreef u: hi Nils, could you please make a patch for your wyse s50 target that adds - GPLv2 headers to all files - adds your copyright to the files you created or changed (like irq_tables.c) Sorry to ask for this late.. I guess I could add it, too

[coreboot] [PATCH] Wyse S50 cleanup

-by: Nils Jacobs njaco...@hetnet.nl Hi Stefan, I hope this is what you had in mind regarding the GPLv2 headers? Thanks,Nils. Index: src/mainboard/wyse/Kconfig === --- src/mainboard/wyse/Kconfig (revision 5543) +++ src/mainboard/wyse/Kconfig

Re: [coreboot] GX2 problems

Op zondag 9 mei 2010 00:00:22 schreef u: On 5/1/10 1:58 AM, Nils wrote: Index: src/northbridge/amd/gx2/northbridgeinit.c === --- src/northbridge/amd/gx2/northbridgeinit.c (revision 5520) +++ src/northbridge/amd/gx2

Re: [coreboot] [PATCH] cleanup CS5535/CS5536 specific init in GX2 code

the CS5536 code for GX2 ? You are aware of the fact that the wyse s50 has a CS5536? (i think the Rumba and olpc`s also) Thanks,Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [commit] r5544 - in trunk/src/mainboard/wyse: . s50

Hi Stefan, You wrote: Author: stepan Date: Fri May 14 11:45:29 2010 New Revision: 5544 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5544 Thanks for committing! Regards,Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] cleanup CS5535/CS5536 specific init in GX2 code

Op vrijdag 14 mei 2010 20:03:25 schreef u: On Fri, 14 May 2010 19:57:22 +0200, Nils njaco...@hetnet.nl wrote: Op vrijdag 14 mei 2010 13:13:39 schreef u: This patch should fix the hda interrupt lost problem on the Wyse S50 Hi Stefan, Thanks for making this patch. :) Unfortunately i

Re: [coreboot] Geode db800 vs Wyse S50

in rev5543 that affects Geodes GX2 and LX. (VSA loading crashes) Greetings,Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] cleanup CS5535/CS5536 specific init in GX2 code

/c9e5c1ad/attachment-0001.ksh I had a little time to do some more tests. I tested your patch together with the patch Peter made in commit 5581 on rev5542 and it works ok, the lost interrupt problem is gone. So the patch is Acked-by: Nils Jacobs njaco...@hetnet.nl Now the next problem left

Re: [coreboot] Wyse S10 Information

is somewhere in the 2Megabyte flash and (even according to the specs) that is all that is available to the thinclient. Ok the flashrom chip in the S50 is 256KB. In the S50 only the bios is in the chip. The operating system Linux v6 is on the flashboard. Nils. -- coreboot mailing list: coreboot

[coreboot] [Re: coreboot] Wyse S10 Information

/coreboot_ram takes ~35 seconds so you have to be a little patience while booting. Nils -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] Fix geode lx VSA loading

Hi all, I boot tested the last revision (by Stefan) of this patch on my Wyse S50 (GX2) and it seems to work nice! So this patch is: Acked-by: Nils Jacobs njaco...@hetnet.nl Thanks,Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] cosmetical oprom update

... Name: oprom.diff URL: http://www.coreboot.org/pipermail/coreboot/attachments/20100604/9866ca6f/attachment.ksh I boot tested the patch on my Wyse S50 (GX2) and it seems to work nice! So this patch is: Acked-by: Nils Jacobs njaco...@hetnet.nl Thanks,Nils. -- coreboot mailing list: coreboot

[coreboot] [PATCH] Wyse S50 RAMBASE 0x100000 fix

This patch fixes RAMBASE 0x10 for Wyse S50. I think that the problem was that extended memory was not setup early enough. This patch is boot tested on r5621. Signed-off-by: Nils Jacobs njaco...@hetnet.nl Thanks,Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org

[coreboot] [PATCH] Wyse S50 RAMBASE 0x100000 fix

This patch fixes RAMBASE 0x10 for Wyse S50. I think that the problem was that extended memory was not setup early enough. This patch is boot tested on r5621. Signed-off-by: Nils Jacobs njaco...@hetnet.nl And now with patch attached,sorry. Thanks,Nils. Index: src/mainboard/wyse/s50/Kconfig

Re: [coreboot] [PATCH] Wyse S50 RAMBASE 0x100000 fix

. Stefan wrote: Why 1F6BF000 ? I extracted that value from the original bios with MSRtool , and it worked. If you have a better setting and / or patch i will be glad to test it. Thanks,Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Minor update on IDE mode on Wyse S10 (CS5536)

coreboot you can enable or disable flash_enable. Normaly it is disabled so you can use IDE.(But for your flash drive i think you want flash enabled) With coreboot you can use a normal recent kernel with the appropriate drivers. Succes,Nils -- coreboot mailing list: coreboot@coreboot.org http

[coreboot] Geode GX2 CAR.

a similar test be needed/desired for GX2 ? Thanks,Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Geode GX2 CAR.

Hi Marc, Op maandag 21 juni 2010 21:35:04 schreef u: Nils, I don't think that the GX2 has that bug and the register bit definitions are completely different. I would leave it out. Marc Ok i understand that it is a LX silicon bug and i wil leave it out. Thanks for the advice. Nils

[coreboot] Name change leftovers ?

Hi Stefan, I found some references to LinuxBios on the Trac roadmap page you might want to change ? http://tracker.coreboot.org/trac/coreboot/roadmap Thanks,Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] Convert Geode GX2 boards to CAR

Hi All, Nils wrote: Peter wrote: Nils wrote: +++ src/cpu/amd/model_gx2/cache_as_ram.inc(revision 0) .. + post_code(0xc5) +DCacheSetupBad: + hlt /* issues */ + jmp DCacheSetupBad Should this maybe fail more loudly than a POST code, which can be disbled completely

Re: [coreboot] [PATCH] Convert Geode GX2 boards to CAR

satisfied . Thanks,Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] Convert Geode GX2 boards to CAR

Ping!? Could anybody tell me how to proceed? Peter:did i gave the wrong answers? :) Thanks,Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] Convert Geode GX2 boards to CAR

Hi Joseph, Op vrijdag 16 juli 2010 14:41:47 schreef u: On Tue, 6 Jul 2010 20:27:12 +0200, Nils njaco...@hetnet.nl wrote: Ping!? Could anybody tell me how to proceed? Peter:did i gave the wrong answers? :) Thanks,Nils. Nils, I really would hate to see your great work go to the way

Re: [coreboot] [PATCH] Convert Geode GX2 boards to CAR

to buy type 1MB SIMM to expand my Philips 386 pc to 2MB! That were times. Nowadays i make my circuits mostly on breadboard. Nils. Ps:I hear that nowadays you can order PCB`s real cheap in china. But i didn`t use it for my simple designs yet as i found the shipping cost for 1 PCB to high

Re: [coreboot] Broken include paths

/file.h to make it obvious that they're not in src/include Abuild tested. Signed-off-by: Myles Watson mylesgw at gmail.com I like that. Acked-by: Nils Jacobs njaco...@hetnet.nl Thanks,Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] Convert Geode GX2 boards to CAR

Hi Joseph and Peter, Thanks for commiting my patch. Now i can dig up the next patch. Thanks,Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [PATCH] Geode GX2 post code patch

This patch lets Geode GX2 use geode_post_code.h just like LX and cleans up gx2def.h and geode_post_code.h a little. It is abuild tested and boot tested on my Wyse S50. Signed-off-by: Nils Jacobs njaco...@hetnet.nl Acked-by: Nils Jacobs njaco...@hetnet.nl (trivial) As this is a trivial patch

Re: [coreboot] [PATCH] Geode GX2 post code patch

Hi Peter, Peter wrote: r5671 Thanks for committing the patch. Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Wyse S50

. It`s still on my to do list. Thanks,Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] FrontRunner and OLPC memory type?

of the parameters but it would be better to use the exact parameters. So if someone could give me the type numbers for the used SDRAM chips i can search for datasheets and implement the right timing numbers. Thanks,Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman

Re: [coreboot] [PATCH] Move CAR config from mainboard to CPU config for AMD GX2 boards.

Hi Warren, I think you forgot to convert the rest of the GX2 boards. :) (AMD Rumba, Lippert Frontrunner, OLPC btest and OLPC rev_a) And when you are at it should ARCH_X86 and UDELAY_TSC also be moved? Thanks, Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org

Re: [coreboot] [commit] r5872 - in trunk/src/mainboard: . olpc

(europe)? Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [PATCH] Geode GX2 auto DRAM detect patch

This patch brings the adapted Geode LX auto DRAM detect code to GX2 , cleans up some files and adds a processor speed setting function in human readable Mhz. Signed-off-by: Nils Jacobs njaco...@hetnet.nl It is Abuild and boot tested on my Wyse S50 with 3 different SODIMMs (128Mb pc2700, 256Mb

Re: [coreboot] [PATCH] Geode GX2 auto DRAM detect patch

***Ping*** It would be nice if someone finds the time to ack/commit or comment my patch. On 10/7/10 , Nils wrote: This patch brings the adapted Geode LX auto DRAM detect code to GX2 , cleans up some files and adds a processor speed setting function in human readable Mhz. Signed-off-by: Nils

Re: [coreboot] [PATCH] Geode GX2 auto DRAM detect patch

‘sdram_set_spd_registers’: src/northbridge/amd/gx2/raminit.c:482: error: ‘DIMM1’ undeclared (first use in this function) make: *** [build/mainboard/wyse/s50/romstage.pre.inc] Fout 1 n Thanks,Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] Geode GX2 auto DRAM detect patch

fine with me. Should i redo the patch for that? Thanks, nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] Geode GX2 auto DRAM detect patch

,Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] Geode GX2 auto DRAM detect patch

I am happy to see there is still some interest in GX2 patches. I will try to split the patch up in 2-3 patches. Unfortunately i will probably have very little time for hobby next week so it can take a while. Thanks, Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org

[coreboot] [PATCH 1/4] Geode GX2 auto DRAM detect patch V2

This patch changes the MSR register numbers in to more descriptive names. Signed-off-by: Nils Jacobs njaco...@hetnet.nl Thanks, Nils Index: src/northbridge/amd/gx2/raminit.c === --- src/northbridge/amd/gx2/raminit.c (revision 6006

[coreboot] [PATCH 2/4] Geode GX2 auto DRAM detect patch V2

This patch cleans up some white space and comments. It also adds a copyright header to pll_reset.c . Signed-off-by: Nils Jacobs njaco...@hetnet.nl Thanks, Nils. Index: src/include/cpu/amd/gx2def.h === --- src/include/cpu/amd

[coreboot] [PATCH 4/4] Geode GX2 auto DRAM detect patch V2

) Signed-off-by: Nils Jacobs njaco...@hetnet.nl Thanks, Nils. Index: src/include/cpu/amd/gx2def.h === --- src/include/cpu/amd/gx2def.h (revision 6006) +++ src/include/cpu/amd/gx2def.h (working copy) @@ -412,6 +412,13 @@ #define

[coreboot] [PATCH 3/4] Geode GX2 auto DRAM detect patch V2

This patch removes some unused code. Signed-off-by: Nils Jacobs njaco...@hetnet.nl Index: src/northbridge/amd/gx2/pll_reset.c === --- src/northbridge/amd/gx2/pll_reset.c (revision 6006) +++ src/northbridge/amd/gx2/pll_reset.c

[coreboot] [PATCH 0/4] Geode GX2 auto DRAM detect patch V2

This patch series splits up the Geode GX2 auto DRAM detect patch into 4 patches as requested. It should be easy to review now. The patches are Abuild and boot tested on my Wyse S50 . They should be applied in this order. Thanks, Nils. -- coreboot mailing list: coreboot@coreboot.org http

Re: [coreboot] [PATCH 0/4] Geode GX2 auto DRAM detect patch V2

) around the hlt instruction? ?? i don't know should it? The code seems to work, but if it is preferred/needed i will add it. Can you point me to some example code or could you supply some code snipped i can test? Thanks, Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org

[coreboot] [PATCH] Geode GX2 comment cleanup 1

This patch cleans up some comments and white space in gx2/northbridgeinit.c and gx2/raminit.c. Signed-off-by: Nils Jacobs njaco...@hetnet.nl This is Abuild and boot tested. Thanks, Nils. Index: src/northbridge/amd/gx2/raminit.c

[coreboot] [PATCH] Geode GX2 comment cleanup 2

This patch cleans up some more comments and white space in model_gx2/cpureginit.c . Signed-off-by: Nils Jacobs njaco...@hetnet.nl This is Abuild and boot tested. Thanks, Nils. Index: src/cpu/amd/model_gx2/cpureginit.c === --- src

[coreboot] [PATCH] Define unused DIMM1 to 0xFF on Geode GX2 boards

This patch defines the unused DIMM1 to 0xFF to make it obvious it is a bogus value. Signed-off-by: Nils Jacobs njaco...@hetnet.nl This was requested by Myles. This is Abuild and boot tested. Thanks, Nils. Index: src/mainboard/wyse/s50/romstage.c

[coreboot] [PATCH] Remove unused code from Geode GX2

This patch removes some unused code from gx2/raminit.c . Signed-off-by: Nils Jacobs njaco...@hetnet.nl This is Abuild and boot tested. Thanks, Nils. Index: src/northbridge/amd/gx2/raminit.c === --- src/northbridge/amd/gx2/raminit.c

[coreboot] [PATCH] Add cpu speed selection to Geode GX2 boards

This patch adds Kconfig cpu speed selection to Geode GX2 boards as requested by Uwe. Signed-off-by: Nils Jacobs njaco...@hetnet.nl This is Abuild and boot tested. Thanks, Nils. Index: src/mainboard/wyse/s50/Kconfig === --- src

[coreboot] print(k) question

Hi all, Could someone explain the difference between printk(BIOS_EMERG, message\n) and print_emerg(message\n) and witch one is preferred? Thanks, Nils -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] Geode GX2 comment cleanup 1

Op woensdag 3 november 2010 14:20:31 schreef u: Thanks, r6014 with some further cosmetic fixes I noticed. Uwe. Thanks for the fast review and commit. Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] Geode GX2 comment cleanup 2

Hi Uwe, Op woensdag 3 november 2010 14:23:36 schreef u: Thanks, r6015 Thanks for the fast review and commit. Clean up stuff looks better than This patch cleans up stuff in svn logs. OK will do better next time. Thanks, Nils. -- coreboot mailing list: coreboot@coreboot.org http

Re: [coreboot] [PATCH] Remove unused code from Geode GX2

Uwe wrote, Op woensdag 3 november 2010 14:24:47 schreef u: Thanks, r6016. Thanks for the fast review and commit. Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [PATCH] Geode GX2 print(k)

Remove banner wrapper function and unify print(k). Signed-off-by: Nils Jacobs njaco...@hetnet.nl The banner part was requested by Uwe. This is Abuild and boot tested. Thanks, Nils. Index: src/northbridge/amd/gx2/raminit.c

[coreboot] [PATCH] Geode GX2 print(k) V2

Remove banner wrapper function and unify print(k). Signed-off-by: Nils Jacobs njaco...@hetnet.nl The banner part was requested by Uwe. This is Abuild and boot tested. V2:Also change Assymetirc into Asymmetric thanks to Idwer for spotting. Thanks, Nils. Index: src/northbridge/amd/gx2/raminit.c

Re: [coreboot] [PATCH] Geode GX2 print(k) V2

Op vrijdag 5 november 2010 01:14:03 schreef u: On Thu, Nov 04, 2010 at 11:35:56PM +0100, Nils wrote: Remove banner wrapper function and unify print(k). Signed-off-by: Nils Jacobs njaco...@hetnet.nl Thanks, 6021. Uwe. Thanks for the review and commit. Nils. -- coreboot mailing

Re: [coreboot] [PATCH] Add cpu speed selection to Geode GX2 boards

Op vrijdag 5 november 2010 01:23:48 schreef u: On Tue, Nov 02, 2010 at 10:33:44PM +0100, Nils wrote: This patch adds Kconfig cpu speed selection to Geode GX2 boards as requested by Uwe. Signed-off-by: Nils Jacobs njaco...@hetnet.nl Thanks, r6023. Uwe. Thanks for the review

Re: [coreboot] [PATCH] Define unused DIMM1 to 0xFF on Geode GX2 boards

Op vrijdag 5 november 2010 01:20:03 schreef u: On Tue, Nov 02, 2010 at 10:33:22PM +0100, Nils wrote: This patch defines the unused DIMM1 to 0xFF to make it obvious it is a bogus value. Signed-off-by: Nils Jacobs njaco...@hetnet.nl Thanks, r6022. I added some comments too to make

Re: [coreboot] [PATCH 0/4] Geode GX2 auto DRAM detect patch V2

Op vrijdag 5 november 2010 01:29:52 schreef u: On Mon, Nov 01, 2010 at 08:28:27PM +0100, Nils wrote: Shouldn't there be a while (1) around the hlt instruction? ?? i don't know should it? The code seems to work, but if it is preferred/needed i will add it. As far as I know the hlt

[coreboot] [PATCH 6/6] Geode GX2 cleanup patch

Move VIDEO_MB to Kconfig. Signed-off-by: Nils Jacobs njaco...@hetnet.nl Thanks, Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [PATCH 6/6] Geode GX2 cleanup patch

Sorry i pushed the wrong button. Disregard my last mail for now. Thanks, Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [PATCH 0/6] Geode GX2 cleanup patch

Hello all, I finally had a little time to work on further splitting up and updating my patches for Geode GX2. This patch set is ABUILD and boot tested on my Wyse S50. Thanks, Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [PATCH 2/6] Geode GX2 cleanup patch

Replace some MSR register numbers with names. Signed-off-by: Nils Jacobs njaco...@hetnet.nl Thanks, Nils. Index: src/include/cpu/amd/gx2def.h === --- src/include/cpu/amd/gx2def.h (revision 6205) +++ src/include/cpu/amd/gx2def.h

[coreboot] [PATCH 3/6] Geode GX2 cleanup patch

Add a while (1) function around the hlt instruction to assure the processor can't wake up from an interrupt. Signed-off-by: Nils Jacobs njaco...@hetnet.nl This was suggested by Uwe Hermann. Thanks! I also included the same patch for Geode LX. Nils. Index: src/northbridge/amd/gx2/pll_reset.c

[coreboot] [PATCH 4/6] Geode GX2 cleanup patch

Remove wrong GX2 processor IIOC mode setting on CS5535 southbridge code and fix CIS mode comments. Signed-off-by: Nils Jacobs njaco...@hetnet.nl Thanks, Nils. Index: src/southbridge/amd/cs5535/early_setup.c === --- src/southbridge

[coreboot] [PATCH 5/6] Geode GX2 cleanup patch

Delete some unused code. Signed-off-by: Nils Jacobs njaco...@hetnet.nl Thanks, Nils. Index: src/cpu/amd/model_gx2/cpureginit.c === --- src/cpu/amd/model_gx2/cpureginit.c (revision 6205) +++ src/cpu/amd/model_gx2/cpureginit.c

[coreboot] [PATCH 6/6] Geode GX2 cleanup patch

Move VIDEO_MB to Kconfig. Signed-off-by: Nils Jacobs njaco...@hetnet.nl Thanks, Nils. Index: src/northbridge/amd/gx2/Kconfig === --- src/northbridge/amd/gx2/Kconfig (revision 6205) +++ src/northbridge/amd/gx2/Kconfig (working copy

Re: [coreboot] [PATCH 4/6] Geode GX2 cleanup patch

.(see above) Thanks, Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [PATCH 4/6 V2] Geode GX2 cleanup patch

Remove duplicated GX2 processor IIOC mode setting on CS5535 southbridge code and fix CIS mode comments. Signed-off-by: Nils Jacobs njaco...@hetnet.nl V2: Add a extra comment. Thanks, Nils. Index: src/southbridge/amd/cs5535/early_setup.c

[coreboot] [PATCH 0/7] Geode GX2 cleanup next round

Hello all, Here comes the next round of split up and updated patches for Geode GX2. This patch set is ABUILD and boot tested on my Wyse S50 in combination with the 2 not yet committed patches from the previous round. Thanks, Nils. -- coreboot mailing list: coreboot@coreboot.org http

[coreboot] [PATCH 1/7] Geode GX2 cleanup next round

-by: Nils Jacobs njaco...@hetnet.nl Thanks, Nils. Index: src/include/cpu/amd/gx2def.h === --- src/include/cpu/amd/gx2def.h (revision 6218) +++ src/include/cpu/amd/gx2def.h (working copy) @@ -77,7 +77,6 @@ #define GL1_GLCP 3 #define

[coreboot] [PATCH 2/7] Geode GX2 cleanup next round

Add a MSR printing function to northbridge.c like in the Geode LX code. Signed-off-by: Nils Jacobs njaco...@hetnet.nl Thanks, Nils. Index: src/southbridge/amd/cs5535/cs5535.h === --- src/southbridge/amd/cs5535/cs5535.h (revision

[coreboot] [PATCH 4/7] Geode GX2 cleanup next round

-Remove the AES register names.(GX2 has no AES registers) Signed-off-by: Nils Jacobs njaco...@hetnet.nl Thanks, Nils. Index: src/include/cpu/amd/gx2def.h === --- src/include/cpu/amd/gx2def.h (revision 6218) +++ src/include/cpu/amd

[coreboot] [PATCH 3/7] Geode GX2 cleanup next round

-Clean up some comments. -Remove some white spaces. -Remove some leading zeros. -Fix a typo in LX code. Signed-off-by: Nils Jacobs njaco...@hetnet.nl Thanks, Nils. Index: src/southbridge/amd/cs5535/cs5535.h === --- src/southbridge

Re: [coreboot] [PATCH 7/7] Geode GX2 cleanup next round

Hi Myles, Thanks for reviewing and committing my patches. Op woensdag 29 december 2010 21:42:39 schreef u: On Wed, Dec 29, 2010 at 12:05 PM, Nils njaco...@hetnet.nl wrote: Move hardcoded IRQ defining from northbridge.c to irq_tables.c . There's also an added init function for the WYSE

Re: [coreboot] [PATCH 2/7] Geode GX2 cleanup next round

Op woensdag 29 december 2010 21:44:08 schreef u: On Wed, Dec 29, 2010 at 12:04 PM, Nils njaco...@hetnet.nl wrote: Add a MSR printing function to northbridge.c like in the Geode LX code. It's surprising to have it included +#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL = BIOS_ERR but then have

Re: [coreboot] [PATCH 2/7] Geode GX2 cleanup next round

Change the print_conf activation from =BIOS_ERR to =BIOS_DEBUG. Signed-off-by: Nils Jacobs njaco...@hetnet.nl Op donderdag 30 december 2010 02:44:12 schreef u: On Wed, Dec 29, 2010 at 4:46 PM, Nils njaco...@hetnet.nl wrote: Op woensdag 29 december 2010 21:44:08 schreef u: On Wed, Dec 29

Re: [coreboot] [commit] r6221 - in trunk/src: include/cpu/amd mainboard/amd/rumba mainboard/lippert/frontrunner mainboard/wyse/s50 northbridge/amd/gx2 southbridge/amd/cs5535

. Signed-off-by: Nils Jacobs njaco...@hetnet.nl Acked-by: Myles Watson myle...@gmail.com Any idea why this broke the lippert frontrunner? http://qa.coreboot.org/log_buildbrd.php?revision=6222device=frontrunnerve ndor=lippertnum=2 See previous message. My older patch was not yet committed

Re: [coreboot] build service results for r6222

. And maybe also: [coreboot] [PATCH 3/6 V2] Geode GX2 cleanup patch Thanks, Nils. It seems that part of this older patch : [coreboot] [PATCH 4/6 V2] Geode GX2 cleanup patch is already commited by Myles. So i will send a updated patch. Thanks, Nils. -- coreboot mailing list: coreboot@coreboot.org http

[coreboot] [PATCH 4/6 V3] Geode GX2 cleanup patch

Remove duplicated GX2 processor IIOC mode setting on CS5535 southbridge code and fix CIS mode comments. Signed-off-by: Nils Jacobs njaco...@hetnet.nl V2: Add a extra comment. V3: Remove already commited part. Thanks, Nils. Index: src/southbridge/amd/cs5535/early_setup.c

Re: [coreboot] [PATCH 4/6 V3] Geode GX2 cleanup patch

I wrote: Remove duplicated GX2 processor IIOC mode setting on CS5535 southbridge code and fix CIS mode comments. Signed-off-by: Nils Jacobs njaco...@hetnet.nl V2: Add a extra comment. V3: Remove already commited part. Thanks, Nils. This can be dropped, Stefan already committed

[coreboot] [PATCH 0/2] Geode GX2 cleanup again

Hello all, Here comes the next round of patches for Geode GX2. This patch set is ABUILD and boot tested on my Wyse S50 . The second patch depends on the first one to cleanly apply. Thanks, Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [PATCH 1/2] Geode GX2 cleanup again

For gx2/northbridgeinit.c -some white space fixes -some codingstyle fixes -some comment fixes. Signed-off-by: Nils Jacobs njaco...@hetnet.nl Thanks, Nils. Index: src/northbridge/amd/gx2/northbridgeinit.c === --- src/northbridge/amd

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