I have been over the memory map a dozen times. I have set my mem parameter
in the bootargs to as much as 10 megs lower than the start of my cmem
region. I have given DSPLINK more than enough space in the codec servers
memory map and have adjusted the dsplink's memory map to match.
No matter what
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Mat Laibowitz wrote:
I have been over the memory map a dozen times. I have set my mem parameter
in the bootargs to as much as 10 megs lower than the start of my cmem
region. I have given DSPLINK more than enough space in the codec servers
memory
From: Troy Kisky [mailto:troy.ki...@boundarydevices.com]
Sent: Saturday, April 11, 2009 7:17 AM
nsek...@ti.com wrote:
From: Steve Chen [sc...@mvista.com]
[...]
diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c
index 635e31f..eecd983 100644
---
Yes, a very similar problem indeed.
I tried your patch from [1], and the problem did go away.
The code no longer crashes with a kernel paging error!
This is major progress, thanks.
I am still not able to get the video decoder codecs that use viddec2
interface to work, but not at least I have a
Hi,
I need to test the various peripheral device and drivers available on
the TI Davinci DM 644x board. For the I have gone through the available
test provided by the TI (functional and performance). But these test
contains test cases for only few peripherals. I need to test for all
other
On Wednesday 08 April 2009 13:17:56 Chaithrika U S wrote:
Display driver for TI DM646x EVM
Signed-off-by: Manjunath Hadli m...@ti.com
Signed-off-by: Brijesh Jadav brijes...@ti.com
Signed-off-by: Chaithrika U S chaithr...@ti.com
These patches add the display driver support for TI DM646x EVM.
From: Steve Chen sc...@mvista.com
The skb data allocated for packet data received is 4 byte aligned.
Unfortunately, this causes non-32bit aligned accesses in IP stack because
the MAC header is non-word aligned (14 bytes).
The result can be observed by looking at /proc/cpu/alignment while the
Thanks for help.
Now I am able to display logo, after enabling Framebuffer Console
support in kernel config.
Device Drivers - Graphics Support - Console display driver support
--- * Framebuffer Console support
Background for the logo is blue by default, I am successfully able to
replace
Hi,
i work with dm6446 on Linux 2.6.10 MV Kernel.
Now i test the audio, but i have some trouble.
the aic23b is the master mode.
the msbsq is the slave mode.
when play music , i only hear a lot of noise but can not hear any music.
when record music, i just hear a lot of noise
Hello Zhang,
I think you need to change the option in struct
nand_davinci_platform_data nand_data,
.ecc_mode = NAND_ECC_SOFT, to use s/w ECC.
Regards,
Philby
On Thu, 2009-04-09 at 10:33 +0800, shaofeng zhang wrote:
Hi Johns,
I had read your message from the email list, and I want to
On Mon, 2009-04-13 at 21:46 +0800, airpla...@yahoo.com.cn wrote:
Hi,
i work with dm6446 on Linux 2.6.10 MV Kernel.
Now i test the audio, but i have some trouble.
the aic23b is the master mode.
the msbsq is the slave mode.
when play music , i only hear a lot of noise but
On Friday 10 April 2009, nsek...@ti.com wrote:
This issue is resolved by using a 2-byte extra offset in the packet buffer.
Isn't the issue that NET_IP_ALIGN is supposed to resolve,
when properly used by network drivers?
___
-Original Message-
From: davinci-linux-open-source-boun...@linux.davincidsp.com
[mailto:davinci-linux-open-source-boun...@linux.davincidsp.com] On Behalf
Of David Brownell
Sent: Thursday, April 09, 2009 5:44 PM
To: Tom Wheeler
Cc: davinci-linux-open-source@linux.davincidsp.com
hi all,
i was using old compilation tools v1.2 and when i moved to v2.0 i can not
compile with the following error
--
From: David Brownell [mailto:davi...@pacbell.net]
Sent: Monday, April 13, 2009 8:43 PM
On Friday 10 April 2009, nsek...@ti.com wrote:
This issue is resolved by using a 2-byte extra offset in the packet
buffer.
Isn't the issue that NET_IP_ALIGN is supposed to resolve,
when properly used by
The codecs.decode_slice package is saying I have a library for the
environment/configuration you're building, and it's named
lib/decode_slice.a470MV. It does this via the getLibs() fxn in it's
package.xs file.
Just a sanity check (as this is a common error)... the codec is saying I have
a
Mark A. Greer mgr...@mvista.com writes:
From: Mark A. Greer mgr...@mvista.com
Fix the definitions of at24_setup() in two davinci board files
that are incorrect.
Signed-off-by: Mark A. Greer mgr...@mvista.com
Thanks, pushing.
Kevin
---
arch/arm/mach-davinci/board-dm644x-evm.c |4
Isn't the issue that NET_IP_ALIGN is supposed to resolve,
when properly used by network drivers?
Looking at the documentation for that macro, drivers are supposed
to call skb_reserve() with NET_IP_ALIGN as argument. The patch is
doing the same, just not using the macro NET_IP_ALIGN.
Troy Kisky troy.ki...@boundarydevices.com writes:
Before this, if a noevent channel was in use, the code
would go into an infinite loop.
Signed-off-by: Troy Kisky troy.ki...@boundarydevices.com
Thanks, pushing.
Kevin
diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
nsek...@ti.com writes:
From: Steve Chen sc...@mvista.com
The skb data allocated for packet data received is 4 byte aligned.
Unfortunately, this causes non-32bit aligned accesses in IP stack because
the MAC header is non-word aligned (14 bytes).
The result can be observed by looking at
David Brownell davi...@pacbell.net writes:
On Tuesday 07 April 2009, Mark A. Greer wrote:
Its unfortunate that the hook name in the drivers ATM is clk_enable().
I really *do not understand* where you're coming from at all.
I think what Mark is getting at is that it's unfortunate that the
On Fri, Apr 10, 2009 at 08:57:40PM +0400, Sergei Shtylyov wrote:
Hello.
Mark A. Greer wrote:
An example with the da830 evm is nand nor flash. The board has
both but only one can be used at a time.
Mark, you're ovesimlifying the matter here too much: NAND and NOR
flashes are on the
On Wed, Apr 08, 2009 at 02:58:18PM -0700, David Brownell wrote:
On Tuesday 07 April 2009, Mark A. Greer wrote:
Its better than making a whole bunch of globals and a whole bunch of
platform_device_register() calls in every board file. That's
unnecessary code bloat. This routine (whatever
On Wed, Apr 08, 2009 at 02:30:52PM -0700, David Brownell wrote:
On Tuesday 07 April 2009, Mark A. Greer wrote:
Maybe this will help.
Its just a hack for your dm355 spi example try to get my
point across. It uses lspc as the tag for what the device
is but the clk struct could be
On Mon, Apr 13, 2009 at 10:58:11AM -0700, Kevin Hilman wrote:
David Brownell davi...@pacbell.net writes:
On Tuesday 07 April 2009, Mark A. Greer wrote:
Its unfortunate that the hook name in the drivers ATM is clk_enable().
I really *do not understand* where you're coming from at
On Wed, Apr 08, 2009 at 02:07:24PM -0700, David Brownell wrote:
[ this is the followup re points I didn't address first time ]
On Monday 06 April 2009, Mark A. Greer wrote:
On Tue, Mar 31, 2009 at 07:19:13PM -0700, David Brownell wrote:
...
Without coupling pinmux with the other two,
On Monday 13 April 2009, Kevin Hilman wrote:
David Brownell davi...@pacbell.net writes:
On Tuesday 07 April 2009, Mark A. Greer wrote:
Its unfortunate that the hook name in the drivers ATM is clk_enable().
I really *do not understand* where you're coming from at all.
I think
I would suggest hooking up CCS and looking at what's going on with the DSP when
this happens. The DSP server needs to get to a handshake point with the ARM,
and it appears that the ARM is timing out after not receiving a response from
the DSP (error code DSP_EBASE + 0x17 is a timeout error).
Mark A. Greer mgr...@mvista.com writes:
Round 2.
I believe I have addressed all of the issues that I agreed to address.
Every patch has checkpatch.pl's cleanly, builds cleanly, and has been
tested on a dm355 evm, dm6446 evm, and dm6467 evm. The last patch was
also tested on a da830 evm.
Mark A. Greer mgr...@mvista.com writes:
From: Mark A. Greer mgr...@mvista.com
Create a structure to encapsulate SoC-specific information.
This will assist in generalizing code so it can be used by
different SoCs that have similar hardware but with minor
differences such as having a
On Mon, Apr 13, 2009 at 02:30:49PM -0700, Kevin Hilman wrote:
Mark A. Greer mgr...@mvista.com writes:
#define DAVINCI_ASYNC_EMIF_CONTROL_BASE0x01e1
#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x0200
@@ -189,8 +190,13 @@ static struct davinci_uart_config uart_config
On Mon, Apr 13, 2009 at 02:18:02PM -0700, Kevin Hilman wrote:
Mark A. Greer mgr...@mvista.com writes:
Round 2.
I believe I have addressed all of the issues that I agreed to address.
Every patch has checkpatch.pl's cleanly, builds cleanly, and has been
tested on a dm355 evm, dm6446
From: Mark A. Greer mgr...@mvista.com
Fix the definitions of at24_setup() in two davinci board files
that are incorrect.
Signed-off-by: Mark A. Greer mgr...@mvista.com
---
arch/arm/mach-davinci/board-dm644x-evm.c |4 +---
arch/arm/mach-davinci/board-dm646x-evm.c |3 +--
2 files changed,
From: Mark A. Greer mgr...@mvista.com
The ARM kernel supports writethrough data cache via the
CONFIG_CPU_DCACHE_WRITETHROUGH option. However, that
functionality wasn't implemented in the arch/arm/boot/compressed
code. It is now necessary due to a new ARM926EJS processor
that has an issue with
Do not re-enable interrupts if receive processing has used its entire
budget.
As described in net/core/dev.c, function net_rx_action, drivers must not
modify
the NAPI state if they consume their entire weight. Davinci EMAC driver was
re-enabling interrupts in the rare case that it has used
Avik Ghose wants you to join Yaari!
Is Avik your friend?
a
href=http://yaari.com/?controller=useraction=mailregisterfriend=1sign=YaariDDL664IJJ621UMC925ADC422;Yes,
Avik is my friend!/a a
href=http://yaari.com/?controller=useraction=mailregisterfriend=0sign=YaariDDL664IJJ621UMC925ADC422;No,
In response to a request, I have created a patch against kernel version
2.6.29-davinci1, using git-format-patch. This is similar code to that
patch that I submitted earlier, except this time for 2.6.29, rather than
2.6.27.
However, I still have some issues with this fix; it deserves a better
Mark A. Greer mgr...@mvista.com writes:
On Mon, Apr 13, 2009 at 02:18:02PM -0700, Kevin Hilman wrote:
Mark A. Greer mgr...@mvista.com writes:
Round 2.
I believe I have addressed all of the issues that I agreed to address.
Every patch has checkpatch.pl's cleanly, builds cleanly, and
Hello,
I tried to test the linux-2.6.28-davinci1 (download from the
http://source.mvista.com/git/) on my platform board.
(my nand flash is NAND01GR3B2B: Manufacturer ID= 0x20,Device ID= 0xA1,Pages
Per Block= 0x40.Number of Blocks= 0x400,Bytes Per Page= 0x800)
and I found that the kernel scan nand
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