Hi,
I have been trying to test DMA by making my own workspace, but even simple
1d-1d transfer is NOT WORKING.
It always hangs in ACPY3_wait()(in the line StatusReg=*iprRegister). I am
using the normal method of initializing the DMA using DMAN3 routines.
If I use the TI example workspace (fastcopytest), it seems to be working
fine.
I tried another thing. I put my linker command file in the fastcopytest
application. Then, "fastcopytest" also did not work.
Could someone help me out with this problem.
Follwoing are some of the linker command files I have used(and DMA has failed
with all of them).
For the last linker file, I have used a Tconf file with 40MB from 0x85300000
for HEAP, 64K of L1DSRAM, 4MB from 0x86b00080 for DDR1 section and 1MB from
0x87f00000 for DSPLINK memory.
*************************************************************************
Linker File 1
*************************************************************************
-heap 0x0C00000
/*-stack 0x8000 */
-stack 0x2000 /*8Kb*/
_DMAN3_EDMA3BASE = 0x01C00000;
MEMORY
{
/*GEM UMAP1 Memory Map SIZE 1MB*/
/* IMBUF MEM Shared between A/B*/
IBUF o = 0x11100000 l = 0x00002000
/*IMGBUF Full Mem*/
IBUF_FULL o= 0x11104000 l = 0x00004000
/*IMX Working MEM*/
IWMEM o= 0x11108000 l = 0x00008000
/*SEQ P MEM*/
SEQPMEM o= 0x11110000 l = 0x00001000
/*VMEM FOR VLCD*/
VMEM o= 0x11111000 l = 0x00001000
/*HMEM FOR VLCD*/
HMEM o= 0x11112000 l = 0x00001000
/*QMEM FOR VLCD*/
QMEM o= 0x11113000 l = 0x00000400
/*IMC cmd memory*/
IMXCMDMEM o= 0x11114000 l = 0x00002000
/*GEM L1P(Secure ROM) Memory Map SIZE 16KB*/
ROM o = 0x00E00000 l = 0x00004000
/*GEM CFG Space(Internal) Memory Map SIZE 4096KB*/
GEM_REG o = 0x01800000 l = 0x00400000
/* GEM CFG Registers */
CFG_REG1: o = 01C00000h l = 3000h
CFG_PARAM: o = 01C04000h l = 4000h
/*SEQ data MEM*/
SEQDMEM: o = 01CDF400h l = 400h /* SEQ Data Memory */
/* CFG Registers */
CFG_REG2: o = 01CDF800h l = 320800h /* CFG Registers */
/*ASYNC EMIF Region 0 Code Region 200 KB*/
AEMIF_CE0_CODE o= 0x02000000 l= 0x00032000
/*ASYNC EMIF Data Region 0 31.8 MB Size */
AEMIF_CE0 o= 0x02032000 l= 0x01FCE000
/*ASYNC EMIF Region 1 Code Region 200 KB*/
AEMIF_CE1_CODE o= 0x04000000 l= 0x00032000
/*ASYNC EMIF Data Region 1 31.8 MB Size */
AEMIF_CE1 o= 0x04032000 l= 0x01FCE000
/*ASYNC EMIF Region 2 Code Region 200 KB*/
AEMIF_CE2_CODE o= 0x06000000 l= 0x00032000
/*ASYNC EMIF Data Region 2 31.8 MB Size */
AEMIF_CE2 o= 0x06032000 l= 0x01FCE000
/*ASYNC EMIF Region 3 Code Region 200 KB*/
AEMIF_CE3_CODE o= 0x08000000 l= 0x00032000
/*ASYNC EMIF Data Region 3 32 MB Size */
AEMIF_CE3 o= 0x08032000 l= 0x01FCE000
/*VLYNQ Remote Region 64 MB Size */
VLYNQREMOTE o= 0x0C000000 l= 0x04000000
/*ARM RAM0 Memory Map SIZE 16 KB*/
ARMRAM0 o= 0x10008000 l= 0x00002000
/*ARM RAM1 Memory Map SIZE 16 KB*/
ARMRAM1 o= 0x1000A000 l= 0x00002000
/*ARM ROM Memory Map SIZE 16 KB*/
ARMROM o= 0x1000C000 l= 0x00002000
/*GEM UMAP1 Memory Map SIZE 1MB*/
/*GEM UMAP0(L2 Cache) Memory Map */
/* 64KB of SRAM/Cache */
L2 o = 0x11800000 l = 0x00010000
/*GEM L1P RAM Memory Map SIZE 32 KB*/
L1PCache o = 0x11E08000 l = 0x00008000
/* GEM L1D RAM Memory Map SIZE 64 KB */
/* Note that when GEM is powered on, only the */
/* first 48K is SRAM, as L1D is in 32K cache. */
/* Hence enethough this is declared as a flat */
/* 64K section, remember that anything that */
/* requires static initialization {fill value} */
/* or dynamic initialization {.cinit} need to */
/* occupy the first 48K bytes. Only scratch */
/* buffers can occupy 48K-64K. */
L1DRam o = 0x11F04000 l = 0x00010000
/* GEM L1D Cache Memory Map SIZE 32 KB */
/* This will be reset to 16K cache mode by */
/* code. Remember default on power up is 32K */
/* cache mode. */
L1D_cache o = 0x11F14000 l = 0x00004000
/*DDR EMIF Control Registers Memory Map SIZE 32KB */
DDREMIFREG o= 0x20000000 l= 0x00008000
/*AEMIF/VLYNQ Shadow Region 224 MB */
AEIMIF_VLYNQ o= 0x42000000 l= 0x0E000000
GEM_DDR_EMIF : o= 0x80000000 l= 0x02000000
}
SECTIONS
{
.text : > GEM_DDR_EMIF
.data : > GEM_DDR_EMIF
.stack : > GEM_DDR_EMIF
.sysmem : > GEM_DDR_EMIF
.bss : > GEM_DDR_EMIF
.cinit : > GEM_DDR_EMIF
.cio : > GEM_DDR_EMIF
.far : > GEM_DDR_EMIF
.pinit : > GEM_DDR_EMIF
.const : > GEM_DDR_EMIF
.switch : > GEM_DDR_EMIF
.bios : > GEM_DDR_EMIF
ISRAM : > L1DRam
CFGRAM : > CFG_PARAM
.intDataMem : > L1DRam
}
**********************************************************************
Linker file 2
**********************************************************************
-heap 0x02800000
-stack 0x2000 /*8Kb*/
-l h263_deccfg.cmd
-l api.l64
_DMAN3_EDMA3BASE = 0x01C00000;
MEMORY {
CACHE_L1P : origin = 0x11e08000, len = 0x8000
CACHE_L1D : origin = 0x11f10000, len = 0x8000
EXTMEM : origin = 0x85300000, len = 0x02d00000
L1DSRAM : origin = 0x11004000, len = 0x10000
}
SECTIONS
{
.image > EXTMEM
.sysmem > EXTMEM
.far: {} > EXTMEM
.text: {} > EXTMEM
.const: {} > EXTMEM
.cinit: {} > EXTMEM
.stack: {} > EXTMEM
.switch: {} > EXTMEM
.cio: {} > EXTMEM
.intDataMem : > L1DSRAM
}
**********************************************************************
Linker file 3
**********************************************************************
-heap 0x00200000
-l dma_deccfg.cmd
/*-l api.l64*/
_DMAN3_EDMA3BASE = 0x01C00000;
SECTIONS
{
.sysmem: {} > DDR
.intDataMem: {} > L1DSRAM
}
**********************************************************************
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