RE: Cache Coherency between ARM core and DSP

Be careful with your cache operations. A WB-inv is not the catch all operation. You can do some damage if you do it in the wrong place. A few hints/tips: * Make sure that only one of the processors is accessing the data at any given time. * Before touching a buffer for the first time the

RE: Cache Coherency between ARM core and DSP

PROTECTED] On Behalf Of Griffis, Brad Sent: Sunday, June 29, 2008 1:55 PM To: amr ali; davinci-linux-open-source@linux.davincidsp.com Subject: RE: Cache Coherency between ARM core and DSP Be careful with your cache operations. A WB-inv is not the catch all operation. You can do some damage if you do