Tanmay is no longer at Linaro
Signed-off-by: Marcin Juszkiewicz
---
Maintainers.txt | 1 -
1 file changed, 1 deletion(-)
diff --git Maintainers.txt Maintainers.txt
index 2e6e87bb6d..afbd2cff0e 100644
--- Maintainers.txt
+++ Maintainers.txt
@@ -295,7 +295,6 @@ M: Ard Biesheuvel
M: Leif
).
Fix up coding style issues as part of copy:
- Add m prefix to module-global variables.
- Add doxygen function comment header.
Cc: Ard Biesheuvel
Cc: Graeme Gregory
Cc: Radoslaw Biernacki
Cc: Tanmay Jagdale
Cc: Rebecca Cran
Reported-by: Marcin Juszkiewicz
Signed-off-by: Leif Lindholm
-off-by: Marcin Juszkiewicz
Tested-by: Marcin Juszkiewicz
---
Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc
b/Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc
index 14733a37183d..ba145aff6413
W dniu 16.12.2021 o 14:16, Ard Biesheuvel pisze:
Platform/LeMaker/CelloBoard/CelloBoard.dsc
As for RdkQemu - I think it is time we just remove that.
I would vote for removal of CelloBoard as well. It never went into any
serious mass production and nowadays you probably count working ones
W dniu 5.09.2023 o 15:52, Leif Lindholm pisze:
I am moving this command outside of EDK2.
This reverts commit 2c2cb235289642775a7c4e6eaeffa6d3828d279c.
Missing signed-off-by. I can add it before pushing if you can confirm
you meant for it to be there.
Oops.
Signed-off-by: Marcin
W dniu 5.09.2023 o 08:11, Yuquan Wang pisze:
Hi, Leif
On 2023-09-04 21:51, quic_llindhol wrote:
>
> However, this version still breaks bisect: attempting to build at 1/3
> or 2/3 leads to:
> ---
>
/work/git/edk2-platforms/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf(72):
> error
Is there a way to have VT100 (or any other black/white, non-ANSI)
terminal for UEFI Shell?
I do many runs of QEMU/sbsa-ref with logging and all those ANSI colour
codes only make problems.
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W dniu 7.09.2023 o 19:40, Andrew (EFI) Fish pisze:
On Sep 7, 2023, at 8:00 AM, Marcin Juszkiewicz wrote:
Is there a way to have VT100 (or any other black/white, non-ANSI)
terminal for UEFI Shell?
I do many runs of QEMU/sbsa-ref with logging and all those ANSI colour
codes only make problems
:
- proper email address used to skip moderation queue
Marcin Juszkiewicz (1):
Revert "ArmPkg: add ArmCpuInfo EFI application"
ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.c | 2430 --
ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.inf | 31 -
ArmPkg/
I am moving this command outside of EDK2.
This reverts commit 2c2cb235289642775a7c4e6eaeffa6d3828d279c.
---
ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.c | 2430 --
ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.inf | 31 -
ArmPkg/ArmPkg.dsc|1 -
3
W dniu 13.10.2023 o 15:24, Gerd Hoffmann pisze:
So two solutions came to my mind:
1. rewrite DSDT generation into C
You might want have a look at DynamicTablesPkg/ for that
Wasn't is involving using ConfigurationManager? Or maybe I just had
wrong assumption after reading code.
2. provide
I want to add EHCI/XHCI switching so platforms older than 0.3
would not complain about missing XHCI.
---
Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 1 +
Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 116 -
Silicon/Qemu/SbsaQemu/AcpiTables/Xhci.asl | 132
I want to add EHCI/XHCI switching so platforms older than 0.3
would not complain about missing XHCI.
---
Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 1 +
Silicon/Qemu/SbsaQemu/AcpiTables/Ehci.asl | 132
2 files changed, 133 insertions(+)
diff --git
If platform version < 0.3 then we want EHCI. Otherwise XHCI needs to be
present.
The problem:
LocateAndInstallAcpiFromFvConditional() gets only DBG2 and FACP tables.
Looks like synchronization issue as there were moments when it got all
present tables.
Anyway even if all goes well then SSDT
.
Any ideas what I did wrong? All patches are work-in-progress.
---
Marcin Juszkiewicz (5):
SbsaQemu: introduce macro to compare platform version
WIP: SbsaQemu: rename USB controller variables to be generic
SbsaQemu: move XHCI to SSDT
SbsaQemu: add EHCI to SSDT
WIP
We want to check "if platver < 0.3" in an easy way.
---
.../IndustryStandard/SbsaQemuPlatformVersion.h | 25
1 file changed, 25 insertions(+)
diff --git
a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuPlatformVersion.h
If run on PlatformVersion <0.3 then we have EHCI controller (not
working) instead of XHCI one.
*BSD platforms hang with wrong combination.
---
Silicon/Qemu/SbsaQemu/SbsaQemu.dec| 4 ++--
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 4
W dniu 17.10.2023 o 13:46, Nhi Pham pisze:
Then looked again at code from
Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiDsdt.c and noticed
UpdateStatusMethodObject() function. Copied some code and it worked.
Could you please check whether we can replace the
UpdateStatusMethodObject() function
for older platforms
- no SSDT overlays for EHCI/XHCI
- no EHCI at all (it does not work anyway)
- no Pcd renaming
---
Marcin Juszkiewicz (4):
SbsaQemu: introduce macro to compare platform version
SbsaQemu: add AcpiLib
SbsaQemu: initialize XHCI only if it exists
SbsaQemu: disable
We want to check "if platver < 0.3" in an easy way.
---
.../IndustryStandard/SbsaQemuPlatformVersion.h | 25
1 file changed, 25 insertions(+)
diff --git
a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuPlatformVersion.h
It will be needed for playing with disabling XHCI later.
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
index 36723e21d7b5..1e650350cb63
We need platform version to be at least 0.3 to have XHCI
in virtual hardware. On older platforms there is non-working
EHCI which we ignore.
Signed-off-by: Marcin Juszkiewicz
---
.../SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c| 47 +++-
1 file changed, 25 insertions(+), 22
We need platform version to be at least 0.3 to have XHCI
in virtual hardware. On older platforms there is non-working
EHCI which we ignore.
Set DSDT node to be disabled so operating system will not try
to initialize not-existing hardware.
Signed-off-by: Marcin Juszkiewicz
---
.../Drivers
We want to check "if platver < 0.3" in an easy way.
Signed-off-by: Marcin Juszkiewicz
---
.../IndustryStandard/SbsaQemuPlatformVersion.h | 25
1 file changed, 25 insertions(+)
diff --git
a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuPlatfor
platforms
- no SSDT overlays for EHCI/XHCI
- no EHCI at all (it does not work anyway)
- no Pcd renaming
---
Marcin Juszkiewicz (4):
SbsaQemu: introduce macro to compare platform version
SbsaQemu: add AcpiLib
SbsaQemu: initialize XHCI only if it exists
SbsaQemu: disable XH
It will be needed for playing with disabling XHCI later.
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
index 806651fc55a0..fa85bd8dab89
We need platform version to be at least 0.3 to have XHCI
in virtual hardware. On older platforms there is non-working
EHCI which we ignore.
Signed-off-by: Marcin Juszkiewicz
---
.../SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c| 49 +++-
1 file changed, 27 insertions(+), 22
We need platform version to be at least 0.3 to have XHCI
in virtual hardware. On older platforms there is non-working
EHCI which we ignore.
Set DSDT node to be disabled so operating system will not try
to initialize not-existing hardware.
Signed-off-by: Marcin Juszkiewicz
---
.../Drivers
W dniu 18.09.2023 o 13:35, Leif Lindholm pisze:
On Mon, Sep 18, 2023 at 13:03:12 +0200, Marcin Juszkiewicz wrote:
There are some changes in progress which make BL1 bigger than 0x8000
which EDK2 uses.
TF-A defines BL1 size to be 0x12000 one. So let follow it.
Signed-off-by: Marcin Juszkiewicz
.
Then he added missing timer into EDK2 ArmPkg and to "virt" platform.
This patch enables NS EL2 virtual timer on SBSA Reference Platform.
Marcin Juszkiewicz (1):
Platform/QemuSbsa: define NS EL2 virtual timer in GTDT
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 2 ++
Silicon/Qem
Armv8.1+ cpus have Virtual Host Extension (VHE) which added non-secure
EL2 virtual timer.
This change adds it into GTDT to fullfil Arm BSA (Base System
Architecture) requirements.
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 2 ++
Silicon/Qemu
W dniu 18.09.2023 o 14:33, Ard Biesheuvel pisze:
On Mon, 18 Sept 2023 at 13:35, Leif Lindholm wrote:
Note for the interested:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/23417
TL;DR: the fip base and bl1 size don't line up. The bl1 size was
already set to sufficient size,
There are some changes in progress which make BL1 bigger than 0x8000
which EDK2 uses.
TF-A defines BL1 size to be 0x12000 one. So let follow it.
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/SbsaQemu/SbsaQemu.fdf | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
Juszkiewicz
Tested-by: Marcin Juszkiewicz
GTDT for SBSA Reference Platform will use it for NS EL2 virtual timer:
default:
Virtual EL2 Timer GSIV : 0x1C
Virtual EL2 Timer Flags: 0x6
non-vhe cpu:
Virtual EL2 Timer GSIV : 0x0
Virtual EL2 Timer Flags
W dniu 20.09.2023 o 12:04, Leif Lindholm pisze:
On Wed, Sep 20, 2023 at 10:25:09 +0200, Marcin Juszkiewicz wrote:
Armv8.1+ cpus have Virtual Host Extension (VHE) which added non-secure
EL2 virtual timer.
It's still valid to use other CPUs than "max" with this platform.
Don
se-n2" cpu support)
FIP size was too small to fit TF-A debug builds with RME (WIP) support
enabled. We need it to merge fixed FIP size in EDK2-platforms.
CPU enablement allows SBSA Reference Platform to boot Linux on
"neoverse-n2" cpu.
Marcin Juszkiewicz (1):
Qemu/Sbsa:
se-n2" cpu support)
FIP size was too small to fit TF-A debug builds with RME (WIP) support
enabled.
CPU enablement allows SBSA Reference Platform to boot Linux on
"neoverse-n2" cpu.
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/Sbsa/License.txt | 2 +-
Platform/Qemu/Sb
.
Then he added missing timer into EDK2 ArmPkg and to "virt" platform.
This patchset enables NS EL2 virtual timer on SBSA Reference Platform.
changes since v1:
- GTDT generated from C
- NS EL2 virtual timer is disabled for Arm v8.0 cpus
Marcin Juszkiewicz (2):
Silicon/SbsaQemu: move IORT
There are more and more things in SbsaQemuAcpiDxe.c file which
should be elsewhere.
Signed-off-by: Marcin Juszkiewicz
---
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h | 37 +++
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 24 +---
2 files changed, 38 insertions
We need to have some conditional code while generating GTDT due
to adding non-secure EL2 virtual timer.
Signed-off-by: Marcin Juszkiewicz
---
.../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 1 -
.../SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 6 +
.../Drivers/SbsaQemuAcpiDxe
Those changes float around whenever I do some changes in code. Time to
send them for merge and stop bothering.
Marcin Juszkiewicz (2):
Silicon/SbsaQemu: drop duplicated Pcd
Silicon/SbsaQemu: fix comment to show proper table name
.../Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
PcdAcpiDefaultOemRevision was listed twice.
Signed-off-by: Marcin Juszkiewicz
---
.../Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 2 --
1 file changed, 2 deletions(-)
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
b/Silicon/Qemu/SbsaQemu
Someone did copy/paste in past and forgot to alter table name in
comment.
Signed-off-by: Marcin Juszkiewicz
---
Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe
W dniu 25.09.2023 o 20:03, Pedro Falcato pisze:
On Mon, Sep 25, 2023 at 10:03 AM Marcin Juszkiewicz
And can someone take a look at config of code obfuscator used for linting?
It spits out amount of information showing that noone looked at updating it
to current version:
You're supposed
.
This also registers the non-discoverable XHCI for sbsa-ref.
Signed-off-by: Yuquan Wang
Tested-off-by: Marcin Juszkiewicz
With this change applied I can finally run OpenBSD 7.3 on SBSA Reference
Platform as it hang when EDK2 says 'there is EHCI' when it is no longer
It is weird that I can have NVME, can install OS on it but cannot boot
from it.
This change adds NVME support so it can be mapped and used.
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 6 ++
Platform/Qemu/SbsaQemu/SbsaQemu.fdf | 5 +
2 files changed, 11
I feel sick each time I have to edit EDK2 code.
All those INF, DEC, DSC, FDF, XYZ files are something I do not even try
to understand, just got minimal knowledge what goes where by asking Leif
(thanks a lot!) and observing build error messages.
I got used to UINTN and other weird variable
Can someone point me to documentation on how to use ACPI table
generators and ConfigurationManagerProtocol? And tell which of platforms
is a good example of using those?
From first look it seems like using ACPI table generators may allow to
simplify code by not creating tables by hand (or in
W dniu 18.10.2023 o 05:28, Nhi Pham pisze:
Hi Marcin,
There is a nitpicking below.
Other than, it looks good to me.
Acked-by: Nhi Pham
a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
index
We need platform version to be at least 0.3 to have XHCI
in virtual hardware. On older platforms there is non-working
EHCI which we ignore.
Signed-off-by: Marcin Juszkiewicz
---
.../SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c| 47 +++-
1 file changed, 25 insertions(+), 22
It will be needed for playing with disabling XHCI later.
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
index 36723e21d7b5..1e650350cb63
We need platform version to be at least 0.3 to have XHCI
in virtual hardware. On older platforms there is non-working
EHCI which we ignore.
Set DSDT node to be disabled so operating system will not try
to initialize not-existing hardware.
Signed-off-by: Marcin Juszkiewicz
---
.../Drivers
:
- XHCI initialized only on PlatVer 0.3+
- XHCI disabled in DSDT for older platforms
- no SSDT overlays for EHCI/XHCI
- no EHCI at all (it does not work anyway)
- no Pcd renaming
---
Marcin Juszkiewicz (4):
SbsaQemu: introduce macro to compare platform version
SbsaQemu: add AcpiLib
We want to check "if platver < 0.3" in an easy way.
---
.../IndustryStandard/SbsaQemuPlatformVersion.h | 25
1 file changed, 25 insertions(+)
diff --git
a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuPlatformVersion.h
W dniu 18.10.2023 o 10:47, Ard Biesheuvel pisze:
Nit: EDK2 Coding Style says that you need a space before (.
Ah, right. forgot to crucify the source.
Is it necessary to handle the result of Status?
EDK2 is full of handling Status on touching ACPI tables. So I followed.
Can you just do
190: Device (PCI0) Warning 3073 -
Multiple types ^ (Device object requires either a _HID or _ADR, but not both)
PCI Firmware specification does not require _ADR for Host bridges.
Signed-off-by: Marcin Juszkiewicz
---
Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 1 -
1 file changed, 1
W dniu 18.10.2023 o 15:36, Laszlo Ersek pisze:
EDK2 expects some random version of uncrustify.
It is not part of BaseTools so I use upstream version. And it looks like
they format in different way using the same config file.
Project URL (to clone and build):
W dniu 18.10.2023 o 12:32, Nhi Pham pisze:
Acked-by: Nhi Pham
Nit: I think you want to run uncrustify for Patch 3 as well :)
Done, will check other changes too.
I have a strong feeling that Qemu part of EDK2 needs a bit
bigger patch when it comes to formatting:
W dniu 18.10.2023 o 10:46, Ard Biesheuvel pisze:
I don't mind adding this here but it is slightly unidiomatic so I'd
like Leif's take on this too.
... and it also lacks a s-o-b line
Oops. Added in local copy.
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W dniu 18.10.2023 o 13:23, Pedro Falcato pisze:
On Wed, Oct 18, 2023 at 12:16 PM Marcin Juszkiewicz
wrote:
W dniu 18.10.2023 o 12:32, Nhi Pham pisze:
Acked-by: Nhi Pham
Nit: I think you want to run uncrustify for Patch 3 as well :)
Done, will check other changes too.
I have a strong
We want to check "if platver < 0.3" in an easy way.
Signed-off-by: Marcin Juszkiewicz
---
.../IndustryStandard/SbsaQemuPlatformVersion.h | 25
1 file changed, 25 insertions(+)
diff --git
a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuPlatfor
| 3 +-
6 files changed, 127 insertions(+), 24 deletions(-)
---
base-commit: 8b20188ced2318c970b3666d2a7c132c40aaee68
change-id: 20231013-ehci-xhci-fix-c529356a7a8f
Best regards,
--
Marcin Juszkiewicz
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Groups.io Links: You receive all messages sent to this group
It will be needed for playing with disabling XHCI later.
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
index 36723e21d7b5..1e650350cb63
We need platform version to be at least 0.3 to have XHCI
in virtual hardware. On older platforms there is non-working
EHCI which we ignore.
Signed-off-by: Marcin Juszkiewicz
---
.../SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c| 49 +++-
1 file changed, 27 insertions(+), 22
We need platform version to be at least 0.3 to have XHCI
in virtual hardware. On older platforms there is non-working
EHCI which we ignore.
Set DSDT node to be disabled so operating system will not try
to initialize not-existing hardware.
Signed-off-by: Marcin Juszkiewicz
---
.../Drivers
During boot of debug build I noticed this message:
Warning: This BaseRngTimerLib implementation will be deprecated.
Please use the MdeModulePkg implementation equivalent.
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 2 +-
1 file changed, 1 insertion(+), 1
W dniu 7.10.2023 o 01:10, Michael Kubacki pisze:
Python 3.12 released recently. The Python version is currently specified
to allow updates to newer minor versions. Time is needed to adjust
scripts for Python 3.12 so this series fixes the Python version to 3.11.
Some places that were already
W dniu 13.10.2023 o 15:31, Marcin Juszkiewicz via groups.io pisze:
W dniu 13.10.2023 o 15:24, Gerd Hoffmann pisze:
So two solutions came to my mind:
1. rewrite DSDT generation into C
You might want have a look at DynamicTablesPkg/ for that
Wasn't is involving using ConfigurationManager
We want to check "if platver < 0.3" in an easy way.
---
.../IndustryStandard/SbsaQemuPlatformVersion.h | 25
1 file changed, 25 insertions(+)
diff --git
a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuPlatformVersion.h
for EHCI/XHCI
- no EHCI at all (it does not work anyway)
- no Pcd renaming
---
Marcin Juszkiewicz (4):
SbsaQemu: introduce macro to compare platform version
SbsaQemu: add AcpiLib
SbsaQemu: initialize XHCI only if it exists
SbsaQemu: disable XHCI in DSDT if not present
It will be needed for playing with disabling XHCI later.
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
index 36723e21d7b5..1e650350cb63
We need platform version to be at least 0.3 to have XHCI
in virtual hardware. On older platforms there is non-working
EHCI which we ignore.
Signed-off-by: Marcin Juszkiewicz
---
.../SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c| 47 +++-
1 file changed, 25 insertions(+), 22
We need platform version to be at least 0.3 to have XHCI
in virtual hardware. On older platforms there is non-working
EHCI which we ignore.
Set DSDT node to be disabled so operating system will not try
to initialize not-existing hardware.
Signed-off-by: Marcin Juszkiewicz
---
.../Drivers
W dniu 18.08.2023 o 20:17, Oliver Smith-Denny pisze:
Currently, unlike OVMF, ArmVirtQemu does not display any graphics, only
the QEMU monitor. Graphics are helpful to confirm booting into an OS is
successful, interacting with the EFI shell while getting separate
logging messages, etc.
Ah,
and there is no IORT, Linux boots.
Changes since v3:
- use proper amount of nodes (3) in IORT
Changes since v2:
- no ITS == no IORT
Changes since v1:
- IORT is generated in C
- no ITS == no ITS node in IORT
- introduced PcdSmmuBase
Marcin Juszkiewicz (2):
Platform/QemuSbsa: add dynamic
From: Shashi Mallela
SBSA Reference Platform has GIC ITS support. Let make use of it.
Base address is read from TF-A via SMC call.
GIC ITS allows us to have complex PCI Express setups.
Co-authored-by: Marcin Juszkiewicz
Signed-off-by: Shashi Mallela
Signed-off-by: Marcin Juszkiewicz
If firmware is used with QEMU 8.0 or older then there will be no GIC ITS
support.
In such case we would not add information about it into MCFG and there
will be no IORT table.
Signed-off-by: Marcin Juszkiewicz
---
.../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 1 -
.../SbsaQemuAcpiDxe
Store Smmu base address in variable in case it would be needed
in more than one place.
Signed-off-by: Marcin Juszkiewicz
---
Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 1 +
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 1 +
2 files changed, 2 insertions(+)
diff --git a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
b
W dniu 21.08.2023 o 20:27, Leif Lindholm pisze:
Hmm, wait. Patch 1/3 adds Iort.aslc and patch 3/3 deletes it. I know
1/3 is Shashi's original implementation and 3/3 is heavily based on
that (if rewritten), but there's no point in merging the churn.
I kind of wanted to get review of both parts.
SBSA Reference Platform can have GIC ITS present. And when it has then
we can have complex PCI Express setup (and some other things).
On systems with GIC ITS support it's address is read from TF-A via SMC
call. IORT is generated, MADT has ITS information. Linux boots and sees
GIC ITS as expected.
about it into MCFG
and there will be no IORT table.
Co-authored-by: Marcin Juszkiewicz
Signed-off-by: Shashi Mallela
Signed-off-by: Marcin Juszkiewicz
---
Silicon/Qemu/SbsaQemu/SbsaQemu.dec| 4 +
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 4 +
.../Qemu/SbsaQemu/AcpiTables
some offsets and check does it work.
It did but I am not sure is it the proper way.
Marcin Juszkiewicz (1):
Platform/QemuSbsa: enlarge firmware offsets
Platform/Qemu/SbsaQemu/SbsaQemu.fdf | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
--
2.41.0
GenFv: ERROR 3000: Invalid
the required fv image size 0x216510 exceeds the set fv image size 0x20
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/SbsaQemu/SbsaQemu.fdf | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.fdf
W dniu 19.07.2023 o 14:08, Marcin Juszkiewicz via groups.io pisze:
If firmware is used with QEMU 8.0 or older then there will be no GIC ITS
support.
In such case we would not add information about it into MCFG and there
will be no IORT table.
Signed-off-by: Marcin Juszkiewicz
---
.../Qemu
W dniu 13.11.2023 o 12:58, Laszlo Ersek pisze:
Note that 73.0.3 indents the subexpression to the "//" comment on the
previous line, while 73.0.8 ignores the comment -- which I think is
justified here.
I believe this improvement may come from uncrustify commit 239c4fad745b
("Prevent endless
From: Marcin Juszkiewicz
Update the TF-A binaries to have Neoverse-N1 support.
This support was merged into TF-A:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/19863
This allows SBSA Reference Platform to use Arm v8.2 cpu without using
"max" cpu.
Signed-off-
W dniu 7.04.2023 o 17:29, Marcin Juszkiewicz pisze:
Changes since v4:
- functions to read system registers are renamed and moved to ArmLib
Marcin Juszkiewicz (2):
ArmLib: add functions to read system registers
add ArmCpuInfo EFI application
ArmPkg/ArmPkg.dsc
ArmCpuInfo uses those to read system registers and other parts of EDK2
may find them useful.
Signed-off-by: Marcin Juszkiewicz
---
ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h| 50 +++-
.../Library/ArmLib/AArch64/AArch64Support.S | 58 ---
2 files changed, 99
App goes through ID_AA64*_EL1 system registers and decode their values.
Signed-off-by: Marcin Juszkiewicz
---
ArmPkg/ArmPkg.dsc|1 +
ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.inf | 33 +
ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.c | 2346 ++
3
W dniu 20.04.2023 o 14:43, Leif Lindholm pisze:
On Fri, Apr 07, 2023 at 17:29:57 +0200, Marcin Juszkiewicz wrote:
+#
+# This flag specifies whether HII resource section is generated into PE image.
+#
+ UEFI_HII_RESOURCE_SECTION = TRUE
The above stanza, and its comment, can be dropped
ArmCpuInfo needs to be able to read ID_AA64ISAR2_EL1 system register.
Older toolchains do not know it.
Same solution as one for QEMU:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg929586.html
Signed-off-by: Marcin Juszkiewicz
---
ArmPkg/Include/Chipset/AArch64.h | 4
1 file
ArmCpuInfo uses those to read system registers and other parts of EDK2
may find them useful.
Signed-off-by: Marcin Juszkiewicz
---
ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h| 50 +++-
.../Library/ArmLib/AArch64/AArch64Support.S | 58 ---
2 files changed, 99
App goes through ID_AA64*_EL1 system registers and decode their values.
Signed-off-by: Marcin Juszkiewicz
---
ArmPkg/ArmPkg.dsc|1 +
ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.inf | 31 +
ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.c | 2427 ++
3
W dniu 21.04.2023 o 16:37, Rebecca Cran pisze:
I noticed CI failed for the push PR
(https://github.com/tianocore/edk2/pull/4292).
Ecc is complaining about missing Doxygen info for the functions:
/ArmCpuInfo/ArmCpuInfo.c
b/MdeModulePkg/Application/ArmCpuInfo/ArmCpuInfo.c
new file mode 100644
index 00..79a02ae430
--- /dev/null
+++ b/MdeModulePkg/Application/ArmCpuInfo/ArmCpuInfo.c
@@ -0,0 +1,2277 @@
+/** @file
+
+ Copyright (c) 2023 Marcin Juszkiewicz
+ SPDX-License-Identifier: BSD-2
W dniu 4.04.2023 o 20:29, Michael D Kinney pisze:
Add GCC and leave GCC5 for now and give time for all downstream
consumers to accommodate the name change.
At a later date, remove GCC5.
In meantime you may also have message "GCC5 is deprecated, please switch
to GCC" + few seconds delay.
We
App goes through ID_AA64*_EL1 system registers and decode their values.
First version which does not use much of current AArch64 support code
present in EDK2. Written to check what data is there and what can be
done with it.
Signed-off-by: Marcin Juszkiewicz
---
MdeModulePkg/MdeModulePkg.dsc
App goes through ID_AA64*_EL1 system registers and decode their values.
Signed-off-by: Marcin Juszkiewicz
---
ArmPkg/ArmPkg.dsc|1 +
ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.inf | 38 +
ArmPkg/Application/ArmCpuInfo/readargs.h | 12 +
ArmPkg/Application
W dniu 7.04.2023 o 12:55, Ard Biesheuvel pisze:
Hello Marcin,
Thanks for this - it looks useful.
> Some comments below.
Thanks.
On Fri, 7 Apr 2023 at 12:40, Marcin Juszkiewicz
wrote:
App goes through ID_AA64*_EL1 system registers and decode their values.
First version which does not
W dniu 7.04.2023 o 15:40, Pedro Falcato pisze:
(+cc old CCs)
(Marcin, you're dropping CC's on your replies)
Oops, sorry.
ASM files that require preprocessing should have a capital S here (.S vs .s)
After renaming it to readregs.S (and changing in ArmCpuInfo.inf) I get:
build.py...
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