Change high speed to HS
Change non-high speed to FS/LS
Implementation of notify_suspend and notify_resume will be different
according to mxs_phy_data-flags.
Signed-off-by: Peter Chen peter.c...@freescale.com
---
drivers/usb/phy/phy-mxs-usb.c |8
1 files changed, 4 insertions(+), 4
The mxs-phy has several bugs and features at different
versions, the driver code can get it through of_device_id.data.
Signed-off-by: Peter Chen peter.c...@freescale.com
---
drivers/usb/phy/phy-mxs-usb.c | 58 ++--
1 files changed, 49 insertions(+), 9
This API is used to set wakeup enable at PHY registers, in that
case, the PHY can be waken up from suspend due to external events,
like vbus change, dp/dm change and id change.
Signed-off-by: Peter Chen peter.c...@freescale.com
---
include/linux/usb/phy.h | 16
1 files
After clear portsc.phcd, PHY needs 200us stable time for switch
32K clock to AHB clock.
Signed-off-by: Peter Chen peter.c...@freescale.com
---
drivers/usb/phy/phy-mxs-usb.c | 11 +++
1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/phy/phy-mxs-usb.c
It is used to access un-regulator registers according to
different controllers.
Signed-off-by: Peter Chen peter.c...@freescale.com
---
drivers/usb/phy/phy-mxs-usb.c |8
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/phy/phy-mxs-usb.c
Hi Felipe Shawn,
The serial adds power management support for MXS PHY, it includes:
- Add one PHY API .set_wakeup, and related API implementation at mxs phy driver
- misc changes and bug fixes for mxs phy to support low power mode and wakeup.
It is based on Greg's usb-next, 3.13-rc1.
Changes
Add fsl,imx6q-usbphy for imx6dq and imx6dl, add
fsl,imx6sl-usbphy for imx6sl.
Signed-off-by: Peter Chen peter.c...@freescale.com
---
Documentation/devicetree/bindings/usb/mxs-phy.txt |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git
The auto setting is used to open related power and clocks
automatically after receiving wakeup signal.
With this feature, the PHY's clock and power can be recovered
correctly from low power mode, it is guaranteed by IC logic.
Signed-off-by: Peter Chen peter.c...@freescale.com
---
When we need the PHY can be waken up by external signals,
we can call this API. Besides, we call mxs_phy_disconnect_line
at this API to close the connection between USB PHY and
controller, after that, the line state from controller is SE0.
Once the PHY is out of power, without calling
Add anatop phandle which is used to access anatop registers to
control PHY's power and other USB operations.
Signed-off-by: Peter Chen peter.c...@freescale.com
---
Documentation/devicetree/bindings/usb/mxs-phy.txt |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git
Add anatop phandle for usbphy
Signed-off-by: Peter Chen peter.c...@freescale.com
---
arch/arm/boot/dts/imx6qdl.dtsi |2 ++
arch/arm/boot/dts/imx6sl.dtsi |2 ++
2 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
It is needed by imx6 SoC series, but not for imx23 and imx28.
Signed-off-by: Peter Chen peter.c...@freescale.com
---
drivers/usb/phy/phy-mxs-usb.c | 23 +--
1 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/phy/phy-mxs-usb.c
Two PHY bugs are fixed by IC logic, but these bits are not
enabled by default, so we enable them at driver.
The two bugs are: MXS_PHY_ABNORMAL_IN_SUSPEND and MXS_PHY_SENDING_SOF_TOO_FAST
which are described at code.
Signed-off-by: Peter Chen peter.c...@freescale.com
---
On Tue, Dec 17, 2013 at 1:18 AM, Bjorn Andersson
bjorn.anders...@sonymobile.com wrote:
No matter how we build the individual pinctrl drivers we will always
need the pinctrl framework in a multi-soc zImage; so I can't see that
we gain anything from being able to compile PINCTRL as a module.
I
On Thu, Dec 19, 2013 at 11:42:22AM +0800, Bo Shen wrote:
When the PWM controller is registered successfully, the clock can not
unprepare, so fix it.
Signed-off-by: Bo Shen voice.s...@atmel.com
---
drivers/pwm/pwm-atmel.c |2 ++
1 file changed, 2 insertions(+)
Applied, thanks.
On Friday 20 December 2013 12:32 AM, Tero Kristo wrote:
On 12/19/2013 08:26 PM, Tony Lindgren wrote:
* Tero Kristo t-kri...@ti.com [131219 03:26]:
Divider clock can now be registered to use low level register access ops.
Preferred initialization method is via clock description.
This seems to
On 12/20/2013 12:07 PM, Rajendra Nayak wrote:
On Friday 20 December 2013 12:32 AM, Tero Kristo wrote:
On 12/19/2013 08:26 PM, Tony Lindgren wrote:
* Tero Kristo t-kri...@ti.com [131219 03:26]:
Divider clock can now be registered to use low level register access ops.
Preferred initialization
Changes since the first RFC version of the patches:
- Drop out already applied:
ASoC: hdmi-codec: Add SNDRV_PCM_FMTBIT_32_LE playback format
- Change sound node's compatible property
form: ti,am33xx-beaglebone-black to ti,am33xx-beaglebone-black-audio
- Some minor style issue fixes from TI
The added clk-gpio is a basic clock that can be enabled and disabled
trough a gpio output. The DT binding document for the clock is also
added. For EPROBE_DEFER handling the registering of the clock has to
be delayed until of_clk_get() call time.
Signed-off-by: Jyri Sarha jsa...@ti.com
cc:
Add machine driver support for BeagleBone-Black and other boards with
tilcdc support and NXP TDA998X HDMI transmitter connected to McASP
port in I2S mode. The 44100 Hz sample-rate and it's multiples can not
be supported on Beaglebone-Black because of limited clock-rate
support. The only supported
On Friday 20 December 2013 03:59 PM, Tero Kristo wrote:
On 12/20/2013 12:07 PM, Rajendra Nayak wrote:
On Friday 20 December 2013 12:32 AM, Tero Kristo wrote:
On 12/19/2013 08:26 PM, Tony Lindgren wrote:
* Tero Kristo t-kri...@ti.com [131219 03:26]:
Divider clock can now be registered to use
The referenced clock is used to get codec clock rate and the clock is
disabled and enabled in startup and shutdown snd_soc_ops call
backs. The change is also documented in DT bindigs document.
Signed-off-by: Jyri Sarha jsa...@ti.com
cc: bcous...@baylibre.com
---
Signed-off-by: Jyri Sarha jsa...@ti.com
cc: bcous...@baylibre.com
---
Documentation/devicetree/bindings/sound/hdmi.txt | 17 +
sound/soc/codecs/hdmi.c | 10 ++
2 files changed, 27 insertions(+)
create mode 100644
Adds configuration option for HDMI audio support for AM33XX based
boards with NXP TDA998x HDMI transmitter. The audio is connected to
NXP TDA998x trough McASP running in i2s mode.
Signed-off-by: Jyri Sarha jsa...@ti.com
---
sound/soc/davinci/Kconfig | 12
From: Peter Chen
Sent: 20 December 2013 07:52
Change high speed to HS
Change non-high speed to FS/LS
Implementation of notify_suspend and notify_resume will be different
according to mxs_phy_data-flags.
Signed-off-by: Peter Chen peter.c...@freescale.com
---
The configuration is needed for HDMI audio. The swap and mirr
parameters have to be correctly set in the configuration in order to
have proper colors in the HDMI picture.
Signed-off-by: Jyri Sarha jsa...@ti.com
cc: airl...@linux.ie
---
drivers/gpu/drm/tilcdc/tilcdc_slave.c | 24
This enables HDMI video support on Beaglebone-Black.
Signed-off-by: Jyri Sarha jsa...@ti.com
cc: t...@atomide.com
---
arch/arm/configs/omap2plus_defconfig |3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/omap2plus_defconfig
b/arch/arm/configs/omap2plus_defconfig
index
Select following:
CONFIG_SND_DAVINCI_SOC=m
CONFIG_SND_AM335X_SOC_NXPTDA_EVM=m
Signed-off-by: Jyri Sarha jsa...@ti.com
cc: t...@atomide.com
---
arch/arm/configs/omap2plus_defconfig |2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/omap2plus_defconfig
On Thu, 19 Dec 2013, Tero Kristo wrote:
From: Mike Turquette mturquet...@linaro.org
Is this E-mail address correct? It's one byte off of the Signed-off-by:
address.
clk_register_desc is the primary interface for populating the clock tree
with new clock nodes. In time, this will replace the
On Thu, 19 Dec 2013, Tero Kristo wrote:
New clk_register_desc() call can be used to register this clock type now.
Signed-off-by: Tero Kristo t-kri...@ti.com
...
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 82dfe84..9fa279d 100644
---
On Thu, 19 Dec 2013, Tero Kristo wrote:
New clk_register_desc() call can be used to register this clock type now.
Signed-off-by: Tero Kristo t-kri...@ti.com
...
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 9fa279d..7dd6842 100644
---
On Thu, 19 Dec 2013, Tero Kristo wrote:
New clk_register_desc() call can be used to register this clock type now.
Signed-off-by: Tero Kristo t-kri...@ti.com
...
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 7dd6842..27a9765 100644
---
On Thu, 19 Dec 2013, Tero Kristo wrote:
Low level register ops are needed for providing SoC or IP block specific
access routines to clock registers. Subsequent patches add support for
the low level ops for the individual clock drivers.
Signed-off-by: Tero Kristo t-kri...@ti.com
...
---
On Tue, 17 Dec 2013, Tero Kristo wrote:
On 12/17/2013 11:44 AM, Paul Walmsley wrote:
On Tue, 26 Nov 2013, Tero Kristo wrote:
This patch creates a unique node for each clock in the OMAP4 power,
reset and clock manager (PRCM). OMAP443x and OMAP446x have slightly
different clock tree
On 12/20/2013 01:00 PM, Paul Walmsley wrote:
On Thu, 19 Dec 2013, Tero Kristo wrote:
Low level register ops are needed for providing SoC or IP block specific
access routines to clock registers. Subsequent patches add support for
the low level ops for the individual clock drivers.
Hi,
Could someone help review and merge this DTS patch please ?
Thanks very much!
Best Regards,
Xiubo
Subject: [PATCHv4 3/4] ARM: dts: Enable SAI ALSA SoC DAI device for Vybrid
VF610 TOWER board.
This patch adds and enables the SAI device.
Signed-off-by: Xiubo Li
On Fri, Dec 20, 2013 at 12:36:56PM +0200, Jyri Sarha wrote:
Changes since the first RFC version of the patches:
Please don't bury your e-mails in the middle of old threads, that's a
good way of getting them missed.
signature.asc
Description: Digital signature
On Thursday 19 December 2013 10:03 PM, Tony Lindgren wrote:
* Balaji T K balaj...@ti.com [131219 04:40]:
@@ -485,6 +503,7 @@
dmas = sdma 61, sdma 62;
dma-names = tx, rx;
status = disabled;
+
On Thu, 19 Dec 2013, Tero Kristo wrote:
Some OMAP clocks require knowledge about their parent clockdomain for
book keeping purposes. This patch creates a new DT binding for TI
clockdomains, which act as a collection of device clocks.
At least on OMAP4 and 5, clockdomains can be either
On Thu, 19 Dec 2013, Tero Kristo wrote:
This patch provides top level functionality for the DT clock initialization.
Clock tree is initialized hierarchically starting from IP modules
(CM/PRM/PRCM)
going down towards individual clock nodes, and finally initializing
clockdomains once all the
On 12/20/2013 01:30 PM, Mark Brown wrote:
On Fri, Dec 20, 2013 at 12:36:56PM +0200, Jyri Sarha wrote:
Changes since the first RFC version of the patches:
Please don't bury your e-mails in the middle of old threads, that's a
good way of getting them missed.
I have done it for my own
This patch fixes a compilation warning.
warning: passing argument 5 of 'thermal_zone_device_register' discards 'const'
qualifier from pointer target type [enabled by default]
include/linux/thermal.h:270:29: note: expected 'struct thermal_zone_device_ops
*'
but argument is of type 'const struct
This patch adds the registers, bit fields and compatible strings
required to support for the 5 TMU channels on Exynos5260.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
---
This patch goes on top of the series (Reviewed and Acked)
On Wed, Dec 18, 2013 at 09:27:29AM -0700, Stephen Warren wrote:
On 12/18/2013 01:02 AM, Mark Zhang wrote:
On 12/12/2013 03:57 PM, Hiroshi Doyu wrote:
Create a header file to define the swgroup IDs used by the IOMMU(SMMU)
binding. swgroup is a group of H/W clients which a Tegra SoC
Many changes/fixes have been identified for clock file for exynos5420.
These include correct parents, bit fields, new clocks etc. Existing
files needs some correction in terms of names of the clock and
indentation. These issues are addressed in this patch series. It also
replaces the usage of
DT nodes contain clock numbers which are referred by drivers
to get the clocks. These numbers are replaced by MACROs
which are defined in the exynos5420-clk.h header file.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
arch/arm/boot/dts/exynos5420.dtsi | 47
On 12/20/2013 01:49 PM, Paul Walmsley wrote:
On Thu, 19 Dec 2013, Tero Kristo wrote:
This patch provides top level functionality for the DT clock initialization.
Clock tree is initialized hierarchically starting from IP modules (CM/PRM/PRCM)
going down towards individual clock nodes, and
On 12/20/2013 12:53 PM, Paul Walmsley wrote:
On Thu, 19 Dec 2013, Tero Kristo wrote:
From: Mike Turquette mturquet...@linaro.org
Is this E-mail address correct? It's one byte off of the Signed-off-by:
address.
No it is not, just my typo there. :P Will fix that for next rev.
Hi,
This is the fifth version of the patchset. It adds a new Exynos USB 2.0 PHY
driver. The driver uses the Generic PHY Framework.
I would like to thank everyone who contributed with comments and took the time
to read through the patches in the previous versions of this patchset.
We had a
Change the used phy driver to the new Exynos USB phy driver that uses the
generic phy framework.
Signed-off-by: Kamil Debski k.deb...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
.../devicetree/bindings/usb/samsung-hsotg.txt |4
Add support to PHY of USB2 of the Exynos 5250 SoC.
Signed-off-by: Kamil Debski k.deb...@samsung.com
---
arch/arm/boot/dts/exynos5250.dtsi | 33 ---
drivers/phy/phy-exynos5250-usb2.c | 64 +
2 files changed, 78 insertions(+), 19 deletions(-)
This the alternative version of the support for Exynos 421x USB 2.0 PHY
in the Generic PHY framework. In this version the support for Exynos
4210 and 4212 was joined into one file.
Signed-off-by: Kamil Debski k.deb...@samsung.com
---
Hi,
Me and Kishon were discussing for quite a long time the
This the alternative version of the support for Exynos 421x USB 2.0 PHY
in the Generic PHY framework. In this version the support for Exynos
4210 and 4212 was joined into one file.
Signed-off-by: Kamil Debski k.deb...@samsung.com
---
Hi,
This is the second alternative version. Please look at
Add support to PHY of USB2 of the Exynos 4 SoC.
Signed-off-by: Kamil Debski k.deb...@samsung.com
---
.../devicetree/bindings/arm/samsung/pmu.txt|2 ++
arch/arm/boot/dts/exynos4.dtsi | 31
arch/arm/boot/dts/exynos4210.dtsi |
Add support for Exynos 5250. This driver is to replace the old
USB 2.0 PHY driver.
Signed-off-by: Kamil Debski k.deb...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
.../devicetree/bindings/phy/samsung-phy.txt|1 +
drivers/phy/Kconfig
ams AS3722 device supports the power off by turning off its all rails.
Add dt node properties to enable this functionality on this device.
Signed-off-by: Laxman Dewangan ldewan...@nvidia.com
Tested-by: Stephen Warren swar...@nvidia.com
---
Changes form V1:
- Rephrase sentence and mention that
ams AS3722 supports the power off functionality to turn off
system.
Add power off driver for ams AS3722.
Signed-off-by: Laxman Dewangan ldewan...@nvidia.com
Tested-by: Stephen Warren swar...@nvidia.com
---
Changes from V1:
- Just added tested by.
drivers/power/reset/Kconfig |6
From: Mateusz Krawczuk mat.krawc...@gmail.com
Add support for the Samsung's S5PV210 SoC to the Exynos USB 2.0 PHY driver.
Signed-off-by: Mateusz Krawczuk m.krawc...@partner.samsung.com
[k.deb...@samsung.com: cleanup and commit description]
[k.deb...@samsung.com: make changes accordingly to the
Adding devm_of_phy_get will allow to get phys by supplying a
pointer to the struct device_node instead of struct device.
Signed-off-by: Kamil Debski k.deb...@samsung.com
---
drivers/phy/phy-core.c | 31 +++
include/linux/phy/phy.h |2 ++
2 files changed, 33
Previously the of_phy_get function took a struct device * and
was declared static. It was impossible to call it from
another driver and thus it was impossible to get phy defined
for a given node. The old function was renamed to _of_phy_get
and was left for internal use. of_phy_get function was
ams AS3722 device supports the power off by turning off its all rails.
Add dt node properties to enable this functionality on this device.
diff --git a/Documentation/devicetree/bindings/mfd/as3722.txt
b/Documentation/devicetree/bindings/mfd/as3722.txt
+functionality from ams
On Fri, 20 Dec 2013, Laxman Dewangan wrote:
ams AS3722 device supports the power off by turning off its all rails.
Add dt node properties to enable this functionality on this device.
Signed-off-by: Laxman Dewangan ldewan...@nvidia.com
Tested-by: Stephen Warren swar...@nvidia.com
I'm
On Thu, 19 Dec 2013, Stephen Warren wrote:
On 12/11/2013 02:24 AM, Lee Jones wrote:
From: Stephen Warren swar...@nvidia.com
mfd_add_device() assigns .of_node in the device objects it creates only
if the mfd_cell for the device has the .of_compatible field set and the
DT node for the
Hi Stephen,
Please let me know if this is suitable and I can keep your Ack.
mfd: Revert mfd: Always assign of_node in mfd_add_device()
This reverts commit 68044bee13770918e0b28dd44aa98c889ec7558f.
We've had confirmed reports of this patch causing unforeseen issues
with existing MFD
disable interrupts at runtime and use that as a state machine, while I was
wondering whether it wouldn't be simpler to keep all interrupts enabled at
all
time and handle the synchronization explicitly.
If I do this, I'll get another spurious interrupt telling me the transmit
register is
Hello,
While working on the OMAP3 ISP driver I've run into a failure to request a
memory region already requested by the pinctrl-single driver. This patch set
is an attempt to fix the problem.
Changes since v1:
- Rebased on top of Tony's master branch
- Handle IGEP LEDs
- Added Tony's PINCTRL
The omap3_pmx_core pinmux device in the device tree handles the system
controller module (SCM) PADCONFS fonction. Its control registers are
split in two distinct areas, with other SCM registers in-between. Those
other registers can't thus be requested by other drivers as the memory
region gets
From: Tony Lindgren t...@atomide.com
As we have one to three pinctrl-single instances for each SoC it is
a bit confusing to configure the padconf register offset from the
base of the padconf register base.
Let's add macros that allow using the physical address of the
padconf register directly,
It seems I forgot to add the vendor prefix for rockchip to the vendor-prefix
list. Therefore add it now.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
Documentation/devicetree/bindings/vendor-prefixes.txt |1 +
1 file changed, 1 insertion(+)
diff --git
* Balaji T K balaj...@ti.com [131220 01:49]:
On Thursday 19 December 2013 10:03 PM, Tony Lindgren wrote:
+static int pbias_regulator_enable(struct regulator_dev *rdev)
+{
+ struct pbias_regulator_data *data = rdev_get_drvdata(rdev);
+ const struct pbias_reg_info *info = data-info;
+
* Balaji T K balaj...@ti.com [131220 03:41]:
On Thursday 19 December 2013 10:03 PM, Tony Lindgren wrote:
* Balaji T K balaj...@ti.com [131219 04:40]:
@@ -485,6 +503,7 @@
dmas = sdma 61, sdma 62;
dma-names = tx, rx;
status =
On Friday 20 December 2013 09:28 PM, Tony Lindgren wrote:
* Balaji T K balaj...@ti.com [131220 03:41]:
On Thursday 19 December 2013 10:03 PM, Tony Lindgren wrote:
* Balaji T K balaj...@ti.com [131219 04:40]:
@@ -485,6 +503,7 @@
dmas = sdma 61, sdma 62;
On Fri, 20 Dec 2013, Tero Kristo wrote:
On 12/20/2013 01:00 PM, Paul Walmsley wrote:
On Thu, 19 Dec 2013, Tero Kristo wrote:
+/**
+ * clk_readl_default - default clock register read support function
+ * @reg: register to read
+ *
+ * Default implementation for reading a clock
On 12/20/2013 06:48 AM, Lee Jones wrote:
On Fri, 20 Dec 2013, Laxman Dewangan wrote:
ams AS3722 device supports the power off by turning off its all rails.
Add dt node properties to enable this functionality on this device.
Signed-off-by: Laxman Dewangan ldewan...@nvidia.com
Tested-by:
On Fri, Dec 20, 2013 at 07:57:21AM -0800, Tony Lindgren wrote:
* Balaji T K balaj...@ti.com [131220 01:49]:
But interrupt was never used/tested AFAIK, there is some settling time
before the generated interrupt status is truely valid, so pbias interrupt
is not
reliable.
OK. Do we need
On 12/20/2013 07:25 AM, Lee Jones wrote:
Hi Stephen,
Please let me know if this is suitable and I can keep your Ack.
Yes, that patch is good. Thanks.
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* Rajendra Nayak rna...@ti.com [131220 02:40]:
yeah, the crash was indeed when ll_ops was dereferenced despite being NULL.
Might be also worth checking if the gate and mux patches have a similar issue.
Regards,
Tony
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* Mark Brown broo...@kernel.org [131220 08:10]:
On Fri, Dec 20, 2013 at 07:57:21AM -0800, Tony Lindgren wrote:
* Balaji T K balaj...@ti.com [131220 01:49]:
But interrupt was never used/tested AFAIK, there is some settling time
before the generated interrupt status is truely valid, so
New clk_register_desc() call can be used to register this clock type now.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
drivers/clk/clk-mux.c| 37 +
include/linux/clk-provider.h | 20
2 files changed, 57 insertions(+)
diff
Hi,
Hopefully final post of this series. At least this is going to be the last
post this year as I will be going to x-mas vacation and won't be back before
Jan 2nd. This time I just sent the patches that have changes in them,
the missing ones are exactly the same as in v11.
Changes done:
- most
Gate clock can now be registered to use low level register access ops.
Preferred initialization method is via clock description.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
drivers/clk/clk-gate.c | 20 +---
include/linux/clk-provider.h |4
2 files changed, 21
Low level register ops are needed for providing SoC or IP block specific
access routines to clock registers. Subsequent patches add support for
the low level ops for the individual clock drivers.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
drivers/clk/clk.c| 28
From: Mike Turquette mturque...@linaro.org
clk_register_desc is the primary interface for populating the clock tree
with new clock nodes. In time, this will replace the various hardware-specific
registration functions (e.g. clk_register_gate).
Signed-off-by: Mike Turquette mturque...@linaro.org
ti_dt_clk_init_provider() can now be used to initialize the contents of
a single clock IP block. This parses all the clocks under the IP block
and calls the corresponding init function for them.
This patch also introduces a helper function for the TI clock drivers
to get register info from DT and
Divider clock can now be registered to use low level register access ops.
Preferred initialization method is via clock description.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
drivers/clk/clk-divider.c| 22 +++---
include/linux/clk-provider.h |4
2 files
New clk_register_desc() call can be used to register this clock type now.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
drivers/clk/clk-divider.c| 34 ++
include/linux/clk-provider.h | 22 ++
2 files changed, 56 insertions(+)
diff
New clk_register_desc() call can be used to register this clock type now.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
drivers/clk/clk-gate.c | 31 +++
include/linux/clk-provider.h | 18 ++
2 files changed, 49 insertions(+)
diff --git
Multiplexer clock can now be registered to use low level register access ops.
Preferred initialization method is via clock description.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
drivers/clk/clk-mux.c| 24 +---
include/linux/clk-provider.h |4
2 files
On 12/20/2013 06:16 PM, Tony Lindgren wrote:
* Rajendra Nayak rna...@ti.com [131220 02:40]:
yeah, the crash was indeed when ll_ops was dereferenced despite being NULL.
Might be also worth checking if the gate and mux patches have a similar issue.
Yea they had and I fixed those. v12 coming
This is a multipurpose clock node, which contains support for multiple
sub-clocks. Uses basic composite clock type to implement the actual
functionality, and TI specific gate, mux and divider clocks.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
.../devicetree/bindings/clock/ti/composite.txt
This patch adds support for TI specific gate clocks. These behave as basic
gate-clock, but have different ops / hw-ops for controlling the actual
gate, for example waiting until the clock is ready. Several sub-types
are supported:
- ti,gate-clock: basic gate clock with default ops/hwops
-
This patch provides top level functionality for the DT clock initialization.
Clock tree is initialized hierarchically starting from IP modules (CM/PRM/PRCM)
going down towards individual clock nodes, and finally initializing
clockdomains once all the clocks are ready.
Signed-off-by: Tero Kristo
The OMAP clock driver now supports DPLL clock type. This patch also
adds support for DT DPLL nodes.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
.../devicetree/bindings/clock/ti/dpll.txt | 75 +++
arch/arm/mach-omap2/clock.h| 164 +-
On Friday 20 December 2013 09:43 PM, Tony Lindgren wrote:
* Mark Brown broo...@kernel.org [131220 08:10]:
On Fri, Dec 20, 2013 at 07:57:21AM -0800, Tony Lindgren wrote:
* Balaji T K balaj...@ti.com [131220 01:49]:
But interrupt was never used/tested AFAIK, there is some settling time
before
Some OMAP clocks require knowledge about their parent clockdomain for
book keeping purposes. This patch creates a new DT binding for TI
clockdomains, which act as a collection of device clocks. Clockdomain
itself is rather misleading name for the hardware functionality, as at
least on OMAP4 /
On 12/19/2013 07:08 PM, Eric Brower wrote:
Modify Tegra30 default USB2 phy_type to UTMI; this matches
power-on-reset defaults and is expected to be the common case.
The current implementation is likely an incorrect
carry-over from Tegra20, where USB2 does default to ULPI.
The series,
On Dec 19, 2013, at 10:25 AM, Sebastian Andrzej Siewior bige...@linutronix.de
wrote:
This prefix is currently used for the musb driver.
Acked-by: Stephen Warren swar...@nvidia.com
Signed-off-by: Sebastian Andrzej Siewior bige...@linutronix.de
---
Balaji T K (7):
mmc: omap_hsmmc: use devm_regulator API
mmc: omap_hsmmc: handle vcc and vcc_aux independently
regulator: add pbias regulator support
mmc: omap_hsmmc: adapt hsmmc to use pbias regulator
ARM: dts: add pbias dt node
ARM: OMAP: enable SYSCON and REGULATOR_PBIAS in
Use devm_regulator API, while at it use
devm_regulator_get_optional for optional vmmc_aux supply
Signed-off-by: Balaji T K balaj...@ti.com
---
drivers/mmc/host/omap_hsmmc.c |6 ++
1 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/host/omap_hsmmc.c
handle vcc and vcc_aux independently to reduce indent.
Signed-off-by: Balaji T K balaj...@ti.com
---
drivers/mmc/host/omap_hsmmc.c | 54 +++--
1 files changed, 25 insertions(+), 29 deletions(-)
diff --git a/drivers/mmc/host/omap_hsmmc.c
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