Hi Bjorn,
On Fri, 2014-01-17 at 15:03 -0800, Bjorn Andersson wrote:
Continuing on Ivans i2c-qup series.
Do you plan to send v4 of this driver? I would like to address
the remaining errors and suggestions and send a new version.
Regards,
Ivan
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To unsubscribe from this list: send the line
This patch adds device tree support to the s5p-sss.c crypto driver.
Also, Documentation under devicetree/bindings added.
Signed-off-by: Naveen Krishna Ch ch.nav...@samsung.com
CC: Herbert Xu herb...@gondor.apana.org.au
CC: David S. Miller da...@davemloft.net
CC: Vladimir Zapolskiy
This patch adds new compatible and variant struct to support the SSS
module on Exynos4 (Exynos4210), Exynos5 (Exynos5420 and Exynos5250)
for which
1. AES register are at an offset of 0x200 and
2. hash interrupt is not available
Signed-off-by: Naveen Krishna Ch ch.nav...@samsung.com
CC: Herbert Xu
From: Naveen Krishna Ch ch.nav...@samsung.com
This patch modifies Kconfig such that ARCH_EXYNOS SoCs
which includes (Exynos4210, Exynos5250 and Exynos5420)
can also select Samsung SSS(Security SubSystem) driver.
Signed-off-by: Naveen Krishna Ch ch.nav...@samsung.com
CC: Herbert Xu
From: Naveen Krishna Ch ch.nav...@samsung.com
Currently, the driver enqueues a request only if the busy bit is
false. And every request initiates a dequeue. If 2 requests arrive
simultaneously, only one of them will be dequeued.
To avoid this senario, we will enqueue the next request
This patch set adds use of clk_prepare/clk_unprepare as
required by generic clock framework.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
Changes since v4:
Handle return value of clk_prepare_enable
Changes since v3:
None
This patch adds code to validate iv buffer before trying to
memcpy the contents
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
Changes since v4:
None
Changes since v3:
None
drivers/crypto/s5p-sss.c |3 ++-
1 file changed, 2
Signed-off-by: Jean-Francois Moine moin...@free.fr
---
.../devicetree/bindings/drm/i2c/tda998x.txt| 27 ++
1 file changed, 27 insertions(+)
create mode 100644 Documentation/devicetree/bindings/drm/i2c/tda998x.txt
diff --git
This patch adds the device tree node for SSS module
found on Exynos5420 and Exynos5250
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
TO: linux-samsung-...@vger.kernel.org
CC: Kukjin Kim kgene@samsung.com
CC:
This patch adds gating clock for SSS(Security SubSystem)
module on Exynos5250/5420.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
TO: linux-samsung-...@vger.kernel.org
TO: Tomasz Figa t.f...@samsung.com
CC: Kukjin Kim kgene@samsung.com
CC: linux-cry...@vger.kernel.org
---
On Wed, Jan 29, 2014 at 7:17 AM, Simon Horman ho...@verge.net.au wrote:
+static struct of_device_id rcar_pci_of_match[] = {
+{ .compatible = renesas,pci-r8a7790, },
Why only H2 SoC, if the driver is for both Gen2 SoCs?
I can add a renesas,pci-rcar-gen2 as a fallback match however
Hello Rob,
On 23/01/2014 16:22, Rob Herring wrote:
On Sat, Jan 11, 2014 at 7:38 AM, boris brezillon
b.brezil...@overkiz.com wrote:
On 08/01/2014 15:21, Boris BREZILLON wrote:
Hello,
This series add the sunxi NFC support with up to 8 NAND chip connected.
I'm still in the early stages drivers
Hello Brian,
On 23/01/2014 02:49, Brian Norris wrote:
+ Huang
Hi Boris,
On Wed, Jan 08, 2014 at 03:21:56PM +0100, Boris BREZILLON wrote:
The Hynix nand flashes store their ECC requirements in byte 4 of its id
(returned on READ ID command).
Signed-off-by: Boris BREZILLON
Hello.
On 29-01-2014 10:22, Simon Horman wrote:
[snip]
+static struct of_device_id rcar_gen2_usb_phy_ofmatch[] = {
+{ .compatible = renesas,usb-phy-r8a7790, },
+{ .compatible = renesas,rcar-gen2-usb-phy, },
Frankly speaking, I don't understand the need for the clearly
On Tuesday, 28. January 2014 19:20:49 Shawn Guo wrote:
On Tue, Jan 28, 2014 at 11:17:22AM +0100, Heiko Stübner wrote:
[... and so on for the other groups ... ]
I'm confused now :-) . Current linux-next [0] shows the pin-settings as
part of imx6sl.dtsi - a way a lot of other architectures
Hi,
Can I get some comments on below mails?
I want to create devicetree node for Xylon logiCVC DRM device driver, and get
comments and suggestions from community.
At the end I would send driver and devicetree binding to mainline.
Thank you,
Davor
Hi Mark,
On Mon, Jan 27, 2014 at
The module clocks in the A31 are still compatible with the A10 one. Add the SPI
module clocks and the PLL6 in the device tree to allow their use by the SPI
controllers.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/boot/dts/sun6i-a31.dtsi | 46
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/configs/sunxi_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
index 3e2259b..b5df4a5 100644
--- a/arch/arm/configs/sunxi_defconfig
+++
The Allwinner A31 has a new SPI controller IP compared to the older Allwinner
SoCs.
It supports DMA, but the driver only does PIO for now, and DMA will be
supported eventually.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
.../devicetree/bindings/spi/spi-sun6i.txt |
Hi everyone,
This patchset brings support for the SPI controller found in the
Allwinner A31 SoC.
Even though the controller supports DMA, the driver only supports PIO
mode for now. This driver will be used to bring up and test DMA on the
SoC, so support for the DMA will come eventually.
It
On Wed, Jan 29, 2014 at 11:06:42AM +0100, Geert Uytterhoeven wrote:
On Wed, Jan 29, 2014 at 7:17 AM, Simon Horman ho...@verge.net.au wrote:
+static struct of_device_id rcar_pci_of_match[] = {
+{ .compatible = renesas,pci-r8a7790, },
Why only H2 SoC, if the driver is for both Gen2
On Wed, Jan 29, 2014 at 02:41:58PM +0400, Sergei Shtylyov wrote:
Hello.
On 29-01-2014 10:22, Simon Horman wrote:
[snip]
+static struct of_device_id rcar_gen2_usb_phy_ofmatch[] = {
+{ .compatible = renesas,usb-phy-r8a7790, },
+{ .compatible = renesas,rcar-gen2-usb-phy, },
On Wed, Jan 29, 2014 at 12:10:48PM +0100, Maxime Ripard wrote:
+config SPI_SUN6I
+ tristate Allwinner A31 SPI controller
+ depends on ARCH_SUNXI || COMPILE_TEST
+ select PM_RUNTIME
+ help
+ This enables using the SPI controller on the Allwinner A31 SoCs.
+
A select
Hello.
On 29-01-2014 16:22, Simon Horman wrote:
[snip]
+static struct of_device_id rcar_gen2_usb_phy_ofmatch[] = {
+{ .compatible = renesas,usb-phy-r8a7790, },
+{ .compatible = renesas,rcar-gen2-usb-phy, },
Frankly speaking, I don't understand the need for the clearly
On Mon, Jan 27, 2014 at 03:59:37PM +, Dave Martin wrote:
On Fri, Jan 24, 2014 at 05:58:07PM +, Lorenzo Pieralisi wrote:
[...]
state0 {
index = 2;
compatible = arm,cpu-power-state;
latency = ...;
/*
* This means that when
On Wed, Jan 29, 2014 at 04:26:55PM +0400, Sergei Shtylyov wrote:
Hello.
On 29-01-2014 16:22, Simon Horman wrote:
[snip]
+static struct of_device_id rcar_gen2_usb_phy_ofmatch[] = {
+{ .compatible = renesas,usb-phy-r8a7790, },
+{ .compatible = renesas,rcar-gen2-usb-phy, },
On Tue, Jan 28, 2014 at 08:24:54AM +, Vincent Guittot wrote:
On 24 January 2014 18:58, Lorenzo Pieralisi lorenzo.pieral...@arm.com wrote:
[...]
Please look below, i have modified the rest of your example accordingly
}:
and then
state0 {
index = 2;
I suppose vendors of virtual hardware ought to be listed here as well.
Signed-off-by: Ian Campbell ian.campb...@citrix.com
Acked-by: Stefano Stabellini stefano.stabell...@eu.citrix.com
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc:
On 01/20/2014 10:43 AM, Nishanth Menon wrote:
Benoit,
On 12/18/2013 11:16 AM, Benoit Cousson wrote:
On 18/12/2013 18:02, Nishanth Menon wrote:
On 12/18/2013 10:57 AM, Benoit Cousson wrote:
On 17/12/2013 20:45, Nishanth Menon wrote:
On 12/09/2013 03:55 PM, Nishanth Menon wrote:
Craneboard
On Wed, Jan 29, 2014 at 12:25:20PM +, Mark Brown wrote:
On Wed, Jan 29, 2014 at 12:10:48PM +0100, Maxime Ripard wrote:
+config SPI_SUN6I
+ tristate Allwinner A31 SPI controller
+ depends on ARCH_SUNXI || COMPILE_TEST
+ select PM_RUNTIME
+ help
+ This enables using
On Tue, Jan 28, 2014 at 12:27 PM, Alexey Charkov alch...@gmail.com wrote:
2014/1/27 Rob Herring robherri...@gmail.com:
On Mon, Jan 27, 2014 at 5:51 AM, Alexey Charkov alch...@gmail.com wrote:
This should make the driver usable with VIA/WonderMedia ARM-based
Systems-on-Chip integrated Rhine III
Hello,
This series adds support for the sunxi NAND Flash Controller (NFC).
This controller supports up to 8 NAND chip connected.
I'm still in the early stages drivers development and some key features are
missing, but it's usable (I tested it on the cubietruck board).
Here's what's missing:
-
Add HW ECC support for the sunxi NAND Flash Controller.
Signed-off-by: Boris BREZILLON b.brezillon@gmail.com
---
drivers/mtd/nand/sunxi_nand.c | 279 +++--
1 file changed, 266 insertions(+), 13 deletions(-)
diff --git a/drivers/mtd/nand/sunxi_nand.c
Add the sunxi NAND Flash Controller dt bindings documentation.
Signed-off-by: Boris BREZILLON b.brezillon@gmail.com
---
.../devicetree/bindings/mtd/sunxi-nand.txt | 46
1 file changed, 46 insertions(+)
create mode 100644
Define the NAND pinctrl configs.
Signed-off-by: Boris BREZILLON b.brezillon@gmail.com
---
arch/arm/boot/dts/sun7i-a20.dtsi | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index
Signed-off-by: Boris BREZILLON b.brezillon@gmail.com
---
arch/arm/boot/dts/sun7i-a20-cubietruck.dts |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
index 031de97..5828923 100644
---
Enable the NFC and describe the NAND flash connected to this controller.
Signed-off-by: Boris BREZILLON b.brezillon@gmail.com
---
arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 31
1 file changed, 31 insertions(+)
diff --git
Add a function to retrieve NAND timing mode (ONFI timing mode) from a given
DT node.
Signed-off-by: Boris BREZILLON b.brezillon@gmail.com
---
drivers/of/of_mtd.c| 19 +++
include/linux/of_mtd.h |8
2 files changed, 27 insertions(+)
diff --git
The Hynix nand flashes store their ECC requirements in byte 4 of its id
(returned on READ ID command).
Signed-off-by: Boris BREZILLON b.brezillon@gmail.com
---
drivers/mtd/nand/nand_base.c | 37 +
1 file changed, 37 insertions(+)
diff --git
Some chip do not support automatic retrieval of ECC level requirements.
Provide an helper function to retrieve these requirements from DT.
Signed-off-by: Boris BREZILLON b.brezillon@gmail.com
---
drivers/of/of_mtd.c| 25 +
include/linux/of_mtd.h |7 +++
Add NAND Flash controller node definition to the A20 SoC.
Signed-off-by: Boris BREZILLON b.brezillon@gmail.com
---
arch/arm/boot/dts/sun7i-a20.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index
Define a struct containing the standard NAND timings as described in NAND
datasheets.
Signed-off-by: Boris BREZILLON b.brezillon@gmail.com
---
include/linux/mtd/nand.h | 49 ++
1 file changed, 49 insertions(+)
diff --git
Add a converter to retrieve NAND timings from an ONFI NAND timing mode.
This only support SDR NAND timings for now.
Signed-off-by: Boris BREZILLON b.brezillon@gmail.com
---
drivers/mtd/nand/Makefile |2 +-
drivers/mtd/nand/nand_timings.c | 248
Add support for the sunxi NAND Flash Controller (NFC).
Signed-off-by: Boris BREZILLON b.brezillon@gmail.com
---
drivers/mtd/nand/Kconfig |6 +
drivers/mtd/nand/Makefile |1 +
drivers/mtd/nand/sunxi_nand.c | 744 +
3 files changed, 751
Hi,
On Tue, Jan 28, 2014 at 10:30:36AM -0600, Felipe Balbi wrote:
On Tue, Jan 28, 2014 at 05:32:30PM +0200, Heikki Krogerus wrote:
On Mon, Jan 27, 2014 at 10:05:20AM -0600, Felipe Balbi wrote:
For the controller drivers the PHYs are just a resource like any
other. The controller drivers
Add documentation for the ONFI NAND timing mode property.
Signed-off-by: Boris BREZILLON b.brezillon@gmail.com
---
Documentation/devicetree/bindings/mtd/nand.txt |5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/mtd/nand.txt
nand-ecc-level property statically defines NAND chip's ECC requirements.
Signed-off-by: Boris BREZILLON b.brezillon@gmail.com
---
Documentation/devicetree/bindings/mtd/nand.txt |3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/mtd/nand.txt
On Tue, Jan 28, 2014 at 11:20 PM, Alexey Charkov alch...@gmail.com wrote:
2014/1/29 Tony Prisk li...@prisktech.co.nz:
On 29/01/14 07:27, Alexey Charkov wrote:
2014/1/27 Rob Herring robherri...@gmail.com:
On Mon, Jan 27, 2014 at 5:51 AM, Alexey Charkov alch...@gmail.com
wrote:
This should
On Tuesday 28 January 2014 12:16:56 Russell King - ARM Linux wrote:
On Tue, Jan 28, 2014 at 01:08:47PM +0100, Arnd Bergmann wrote:
On balance, I think the virtual channel approach makes client drivers
more elegant and simpler, and makes the DMA engine API easier to use,
and gives greater
On Friday 24 January 2014 15:16:32 Marc C wrote:
What's wrong with having a system clock unit binding, that the kernel
can decompose as appropriate?
From what I understand, the arm-soc maintainers want to reduce (and perhaps
even
eliminate) these board-specific constructs, and try to
On 1/17/2014 5:08 AM, Andreas Herrmann wrote:
arm-smmu driver uses of_parse_phandle_with_args when parsing DT
information to determine stream IDs for a master device.
Thus the number of stream IDs per master device is bound by
MAX_PHANDLE_ARGS.
To support Calxeda ECX-2000 hardware arm-smmu
On Tue, Jan 28, 2014 at 9:56 AM, Sergei Shtylyov
sergei.shtyl...@cogentembedded.com wrote:
On 01/28/2014 04:38 PM, Rob Herring wrote:
This patch is an attempt to gather the Ethernet related bindings in one
file,
like it's done in the MMC and some other subsystems. It should save some
of
the
On Wed, Jan 29, 2014 at 02:32:27PM +0100, Maxime Ripard wrote:
On Wed, Jan 29, 2014 at 12:25:20PM +, Mark Brown wrote:
A select of PM_RUNTIME is both surprising and odd - why is that there?
The usual idiom is that the device starts out powered up (flagged using
pm_runtime_set_active())
On Wed, Jan 29, 2014 at 10:11 AM, Suravee Suthikulanit
suravee.suthikulpa...@amd.com wrote:
On 1/17/2014 5:08 AM, Andreas Herrmann wrote:
arm-smmu driver uses of_parse_phandle_with_args when parsing DT
information to determine stream IDs for a master device.
Thus the number of stream IDs per
On 1/29/2014 10:57 AM, Rob Herring wrote:
diff --git a/include/linux/of.h b/include/linux/of.h
index 276c546..24e1b28 100644
--- a/include/linux/of.h
+++ b/include/linux/of.h
@@ -67,7 +67,7 @@ struct device_node {
#endif
};
-#define MAX_PHANDLE_ARGS 8
+#define MAX_PHANDLE_ARGS 16
Since
On Wed, Jan 29, 2014 at 8:34 AM, Boris BREZILLON
b.brezillon@gmail.com wrote:
Add the sunxi NAND Flash Controller dt bindings documentation.
Signed-off-by: Boris BREZILLON b.brezillon@gmail.com
---
.../devicetree/bindings/mtd/sunxi-nand.txt | 46
1
On Wed, Jan 29, 2014 at 11:11 AM, Rob Herring robherri...@gmail.com wrote:
On Wed, Jan 29, 2014 at 8:34 AM, Boris BREZILLON
b.brezillon@gmail.com wrote:
Add the sunxi NAND Flash Controller dt bindings documentation.
[snip]
+- onfi,nand-timing-mode : mandatory if the chip does not
On Wed, Jan 29, 2014 at 11:59:12AM -0500, Suravee Suthikulanit wrote:
On 1/29/2014 10:57 AM, Rob Herring wrote:
diff --git a/include/linux/of.h b/include/linux/of.h
index 276c546..24e1b28 100644
--- a/include/linux/of.h
+++ b/include/linux/of.h
@@ -67,7 +67,7 @@ struct device_node {
On Tue, Jan 28, 2014 at 5:36 PM, Peter De Schrijver
pdeschrij...@nvidia.com wrote:
Add efuse bindings for Tegra20, Tegra30, Tegra114 and Tegra124.
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
Acked-by: Rob Herring r...@kernel.org
Rob
---
On 1/29/2014 11:16 AM, Andreas Herrmann wrote:
On Wed, Jan 29, 2014 at 11:59:12AM -0500, Suravee Suthikulanit wrote:
On 1/29/2014 10:57 AM, Rob Herring wrote:
diff --git a/include/linux/of.h b/include/linux/of.h
index 276c546..24e1b28 100644
--- a/include/linux/of.h
+++ b/include/linux/of.h
Hi,
This is the sixth version of the patchset. It adds a new Exynos USB 2.0 PHY
driver. The driver uses the Generic PHY Framework.
Again, I would like to thank everyone who commented and read through the fifth
version of the patchset. Your input is very much appreciated. The last version
had two
Previously the of_phy_get function took a struct device * and
was declared static. It was impossible to call it from
another driver and thus it was impossible to get phy defined
for a given node. The old function was renamed to _of_phy_get
and was left for internal use. of_phy_get function was
Change the phy provider used from the old one using the USB phy
framework to a new one using the Generic phy framework.
Signed-off-by: Kamil Debski k.deb...@samsung.com
---
.../devicetree/bindings/usb/exynos-usb.txt | 13 +++
drivers/usb/host/ehci-exynos.c | 97
Add support to PHY of USB2 of the Exynos 4 SoC.
Signed-off-by: Kamil Debski k.deb...@samsung.com
---
.../devicetree/bindings/arm/samsung/pmu.txt|2 ++
arch/arm/boot/dts/exynos4.dtsi | 31
arch/arm/boot/dts/exynos4210.dtsi |
Adding devm_of_phy_get will allow to get phys by supplying a
pointer to the struct device_node instead of struct device.
Signed-off-by: Kamil Debski k.deb...@samsung.com
---
drivers/phy/phy-core.c | 31 +++
include/linux/phy/phy.h |8
2 files changed,
On Wed, Jan 29, 2014 at 05:26:35PM +, Suravee Suthikulanit wrote:
On 1/29/2014 11:16 AM, Andreas Herrmann wrote:
On Wed, Jan 29, 2014 at 11:59:12AM -0500, Suravee Suthikulanit wrote:
Actually, we are using 32 on the AMD system. So, do you think we can set
this to 32 instead?
I think
From: Mateusz Krawczuk mat.krawc...@gmail.com
Add support for the Samsung's S5PV210 SoC to the Exynos USB PHY driver.
Signed-off-by: Mateusz Krawczuk m.krawc...@partner.samsung.com
[k.deb...@samsung.com: cleanup and commit description]
[k.deb...@samsung.com: make changes accordingly to the
Add support to PHY of USB2 of the Exynos 5250 SoC.
Signed-off-by: Kamil Debski k.deb...@samsung.com
---
arch/arm/boot/dts/exynos5250.dtsi | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index
On Mon, Jan 27, 2014 at 05:33:51PM +, Davor Joja wrote:
Hi Mark,
On Mon, Jan 27, 2014 at 03:47:42PM +, Davor Joja wrote:
Hi,
Hi,
Can I please get comments about adding new vendor prefix xylon, and on
following devicetree binding for Xylon configurable video
Add support for Exynos 5250. This driver is to replace the old
USB 2.0 PHY driver.
Signed-off-by: Kamil Debski k.deb...@samsung.com
---
.../devicetree/bindings/phy/samsung-phy.txt|1 +
drivers/phy/Kconfig| 11 +
drivers/phy/Makefile
On Wed, Jan 29, 2014 at 03:34:13PM +0100, Boris BREZILLON wrote:
nand-ecc-level property statically defines NAND chip's ECC requirements.
Signed-off-by: Boris BREZILLON b.brezillon@gmail.com
---
Documentation/devicetree/bindings/mtd/nand.txt |3 +++
1 file changed, 3 insertions(+)
On Wed, Jan 29, 2014 at 03:34:18PM +0100, Boris BREZILLON wrote:
+static int sunxi_nand_chip_init_timings(struct sunxi_nand_chip *chip,
+ struct device_node *np)
+{
+ const struct nand_sdr_timings *timings;
+ u32 min_clk_period = 0;
+ int ret;
On 1/29/2014 11:29 AM, Will Deacon wrote:
On Wed, Jan 29, 2014 at 05:26:35PM +, Suravee Suthikulanit wrote:
On 1/29/2014 11:16 AM, Andreas Herrmann wrote:
On Wed, Jan 29, 2014 at 11:59:12AM -0500, Suravee Suthikulanit wrote:
Actually, we are using 32 on the AMD system. So, do you think we
On Tue, Jan 28, 2014 at 10:21:38AM +0100, Geert Uytterhoeven wrote:
From: Geert Uytterhoeven geert+rene...@linux-m68k.org
Applied, thanks. I was expecting your last patch to be resubmitted as
well?
signature.asc
Description: Digital signature
Hello Rob,
Le 29/01/2014 18:11, Rob Herring a écrit :
On Wed, Jan 29, 2014 at 8:34 AM, Boris BREZILLON
b.brezillon@gmail.com wrote:
Add the sunxi NAND Flash Controller dt bindings documentation.
Signed-off-by: Boris BREZILLON b.brezillon@gmail.com
---
On Wed, Jan 29, 2014 at 05:57:16PM +, Suravee Suthikulanit wrote:
On 1/29/2014 11:29 AM, Will Deacon wrote:
On Wed, Jan 29, 2014 at 05:26:35PM +, Suravee Suthikulanit wrote:
On 1/29/2014 11:16 AM, Andreas Herrmann wrote:
On Wed, Jan 29, 2014 at 11:59:12AM -0500, Suravee Suthikulanit
Dear Rob, and other DT maintainers,
From: Rob Herring
[...]
+- onfi,nand-timing-mode : mandatory if the chip does not support the ONFI
+ standard.
Add to generic nand binding.
+- allwinner,rb : shall contain the native Ready/Busy ids.
+ or
+- rb-gpios : shall contain the gpios used as R/B
cpu0 clock node has no functionality, since cpufreq-cpu0 is already
capable of picking up the clock from dts.
Signed-off-by: Nishanth Menon n...@ti.com
---
drivers/clk/ti/clk-33xx.c |1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/clk/ti/clk-33xx.c b/drivers/clk/ti/clk-33xx.c
index
OMAP34xx, AM3517 and OMAP36xx platforms use dpll1 clock.
OMAP443x, OMAP446x, OMAP447x, OMAP5, DRA7, AM43xx platforms use
dpll_mpu clock.
Latency used is the generic latency defined in omap-cpufreq
driver.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/boot/dts/am33xx.dtsi |4
Add clock nodes for all existing OMAP platforms where cpufreq-cpu0
can be used.
Sanity tested with linux next-20140128 tag, applies on
master 0e47c96 Merge tag 'for-linus-20140127' of
git://git.infradead.org/linux-mtd
Ofcourse, I have send 7 different versions[1] previously, so I will start
On Mon, Jan 27, 2014 at 12:27:00PM -0300, Ezequiel Garcia wrote:
A new round, mostly fixing some minor nitpicks.
If anyone wants to give this a test, here's a public branch:
https://github.com/MISL-EBU-System-SW/mainline-public/tree/wdt_for_v3.14_v5
I'll be resending a new v6 adressing
Le 29/01/2014 19:02, Gupta, Pekon a écrit :
Dear Rob, and other DT maintainers,
From: Rob Herring
[...]
+- onfi,nand-timing-mode : mandatory if the chip does not support the ONFI
+ standard.
Add to generic nand binding.
+- allwinner,rb : shall contain the native Ready/Busy ids.
+ or
+-
Dear Rob, and other DT maintainers,
(apologies, fixed typos in earlier mail)
From: Rob Herring
[...]
+- onfi,nand-timing-mode : mandatory if the chip does not support the ONFI
+ standard.
Add to generic nand binding.
+- allwinner,rb : shall contain the native Ready/Busy ids.
+ or
+-
Hello Ezequiel
Le 29/01/2014 18:53, Ezequiel Garcia a écrit :
On Wed, Jan 29, 2014 at 03:34:13PM +0100, Boris BREZILLON wrote:
nand-ecc-level property statically defines NAND chip's ECC requirements.
Signed-off-by: Boris BREZILLON b.brezillon@gmail.com
---
On Wed, Jan 29, 2014 at 10:56:42AM -0700, Jason Gunthorpe wrote:
On Wed, Jan 29, 2014 at 03:34:18PM +0100, Boris BREZILLON wrote:
[..]
+static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
[..]
+ ret = sunxi_nand_chip_init_timings(chip, np);
+ if
Le 29/01/2014 18:56, Jason Gunthorpe a écrit :
On Wed, Jan 29, 2014 at 03:34:18PM +0100, Boris BREZILLON wrote:
+static int sunxi_nand_chip_init_timings(struct sunxi_nand_chip *chip,
+ struct device_node *np)
+{
+ const struct nand_sdr_timings
On Wed, Jan 29, 2014 at 03:46:20PM -0300, Ezequiel Garcia wrote:
After CE# has been pulled high and then transitioned low again, the host
should issue a Set Features to select the appropriate asynchronous timing
mode.
Oh, I had forgot you should do a set feature too
Boris, I think the
Hi Mark,
On Wed, Jan 29, 2014 at 7:00 PM, Mark Brown broo...@kernel.org wrote:
On Tue, Jan 28, 2014 at 10:21:38AM +0100, Geert Uytterhoeven wrote:
From: Geert Uytterhoeven geert+rene...@linux-m68k.org
Applied, thanks. I was expecting your last patch to be resubmitted as
Thanks!
well?
As
On Wed, Jan 29, 2014 at 12:19 PM, Nishanth Menon n...@ti.com wrote:
OMAP34xx, AM3517 and OMAP36xx platforms use dpll1 clock.
OMAP443x, OMAP446x, OMAP447x, OMAP5, DRA7, AM43xx platforms use
dpll_mpu clock.
Latency used is the generic latency defined in omap-cpufreq
driver.
Signed-off-by:
On Monday 27 January 2014, Tanmay Inamdar wrote:
On Sat, Jan 25, 2014 at 12:11 PM, Arnd Bergmann a...@arndb.de wrote:
On Friday 24 January 2014 13:28:22 Tanmay Inamdar wrote:
On Thu, Jan 16, 2014 at 5:10 PM, Tanmay Inamdar tinam...@apm.com wrote:
On Wed, Jan 15, 2014 at 4:39 AM, Arnd
On Mon, Jan 27, 2014 at 12:27:16PM -0300, Ezequiel Garcia wrote:
In order to support multiplatform builds the watchdog devicetree binding
was modified and now the 'reg' property is specified to need two
entries. This commit adds the second entry as-per the new specification.
Tested-by:
On Wed, 29 Jan 2014, Kamil Debski wrote:
Change the phy provider used from the old one using the USB phy
framework to a new one using the Generic phy framework.
Signed-off-by: Kamil Debski k.deb...@samsung.com
---
.../devicetree/bindings/usb/exynos-usb.txt | 13 +++
On Wed, Jan 29, 2014 at 9:29 AM, Kamil Debski k.deb...@samsung.com wrote:
Add support to PHY of USB2 of the Exynos 4 SoC.
Signed-off-by: Kamil Debski k.deb...@samsung.com
---
.../devicetree/bindings/arm/samsung/pmu.txt|2 ++
arch/arm/boot/dts/exynos4.dtsi |
Adds support for capturing PWM signals using the TI ECAP peripheral.
This driver supports triggered buffer capture of pulses on multiple
ECAP instances. In addition, the driver supports configurable polarity
of the signal to be captured.
Signed-off-by: Matt Porter mpor...@linaro.org
---
The IIO TI ECAP driver depends on the TI PWMSS management
driver in this subsystem. Enable PWMSS when the IIO TI ECAP
driver is selected.
Signed-off-by: Matt Porter mpor...@linaro.org
---
drivers/pwm/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pwm/Kconfig
Add missing interrupt properties to the ecap0, ecap1, and ecap2
nodes.
Signed-off-by: Matt Porter mpor...@linaro.org
---
arch/arm/boot/dts/am33xx.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 6d95d3d..b4139ba
Hello.
On 01/29/2014 10:43 AM, David Miller wrote:
Though described as required, couple more properties in the DaVinci EMAC
binding are actually optional, as the driver will happily function without them.
The patchset is against DaveM's 'net.git' tree this time.
[1/2] DT: net:
Hello.
On 01/29/2014 07:16 PM, Rob Herring wrote:
This patch is an attempt to gather the Ethernet related bindings in one
file,
like it's done in the MMC and some other subsystems. It should save some
of
the trouble of documenting several properties over and over in each
binding
document,
ons 2014-01-29 klockan 11:11 -0600 skrev Rob Herring:
Isn't allwinner,rb implied by a lack of rb-gpios property. Or no R/B
pin is an option? If so, don't you need some fixed time delay
properties like max erase time?
rb-gpios could be added to the generic nand binding as well.
The
On 01/29/2014 01:29 PM, Robert Nelson wrote:
On Wed, Jan 29, 2014 at 12:19 PM, Nishanth Menon n...@ti.com wrote:
OMAP34xx, AM3517 and OMAP36xx platforms use dpll1 clock.
OMAP443x, OMAP446x, OMAP447x, OMAP5, DRA7, AM43xx platforms use
dpll_mpu clock.
Latency used is the generic latency
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