Hi Daniel, Thierry and Rob,
Currently, the following boards are working fine with the bridge chip series:
- snow
- spring
- peach_pit
- peach_pi
And, I did change my original patchset based on your comments here:
(1) [RFC V2 0/3] drm/bridge: panel and chaining
On Tuesday 08 July 2014, Bjorn Helgaas wrote:
On Tue, Jul 8, 2014 at 1:00 AM, Arnd Bergmann a...@arndb.de wrote:
On Tuesday 08 July 2014, Bjorn Helgaas wrote:
On Tue, Jul 01, 2014 at 07:43:28PM +0100, Liviu Dudau wrote:
+static LIST_HEAD(io_range_list);
+
+/*
+ * Record the PCI IO
On Tuesday 08 July 2014, Liviu Dudau wrote:
Here's what these look like in /proc/iomem and /proc/ioports (note that
there are two resource structs for each memory-mapped IO port space: one
IORESOURCE_MEM for the memory-mapped area (used only by the host bridge
driver), and one
On Wednesday 09 July 2014, Liviu Dudau wrote:
Maybe that assumption is guaranteed by OF, but it doesn't hold for ACPI;
ACPI can describe several I/O port apertures for a single bridge, each
associated with a different CPU physical memory region.
That is actually a good catch, I've
On 30-Jun-14 10:03, Zhou Wang wrote:
Signed-off-by: Zhou Wang wangzhou@gmail.com
---
arch/arm/boot/dts/hip04.dtsi | 31 +++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi
index abb42ca..e63fc61
Hi Matt,
On Tue, 8 Jul 2014 16:51:24 -0700
Matt Roper matthew.d.ro...@intel.com wrote:
Hi Boris.
I haven't really looked at any of your driver in depth, but from a quick
glance it looks like you're registering a cursor drm_plane (i.e., making
use of the new universal plane infrastructure),
Hi,
On 07/08/2014 03:40 PM, Tejun Heo wrote:
(Cc'ing Hans.)
Thanks for adding me to the loop.
I've been reading the entire thread sofar, and here are my 2 cents:
1) I think overall this is a good idea, and I like the suggested dt
representation
2) I agree with Tejun that it would be better
Dear Kukjin Kim,
This patch modified Exynos3250 dtsi to support ADC with IIO.
Could you please reivew this patchset about exynos3250.dtsi?
Best Regards,
Chanwoo Choi
On 06/30/2014 10:51 AM, Chanwoo Choi wrote:
Dear Kukjin,
On 06/29/2014 08:50 PM, Jonathan Cameron wrote:
On 27/06/14 05:30,
On Wed, Jul 2, 2014 at 5:41 PM, Tomasz Figa t.f...@samsung.com wrote:
One of remaining limitations of current pinctrl-samsung driver was
the inability to parse multiple pinmux/pinconf group nodes grouped
inside a single device tree node. It made defining groups of pins for
single purpose, but
On Sat, Jul 05, 2014 at 07:10:38PM +0800, jianqun wrote:
From: Jianqun Xu x...@rock-chips.com
Add devicetree bindings for i2s controller found on
rk3066, rk3188 and rk3288 processors from rockchip.
Applied both, thanks.
signature.asc
Description: Digital signature
On 08/07/14 21:00, Stephen Boyd wrote:
Hi,
On MSM chips we have some efuses (called qfprom) where we store things
like calibration data, speed bins, etc. We need to read out data from
the efuses in various drivers like the cpufreq, thermal, etc. This
essentially boils down to a bunch of
Hi everyone,
This is PRCM subset v4 of the sun8i A23 bring-up series. This subset
includes clock and reset controller support for the PRCM (power,
reset and clock module) on the A23 SoC. It is based on my previous
series for basic sun8i A23 clocks [1].
Patch 1 modifies tha sun6i-a31-apb0-gates
The Allwinner A23 SoC has a PRCM unit like the previous A31 SoC.
The differences are the AR100 clock can no longer be modified,
the APB0 clock has different divisors, and some clock gates are
gone.
This patch adds a compatible with a modified subdevice list for
the A23.
Signed-off-by: Chen-Yu
This patch adds allwinner,sun8i-a23-apb0-gates-clk, a A23 specific
compatible to the sun6i-a31-apb0-gates clock driver, along with the
gate bitmap.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
drivers/clk/sunxi/clk-sun6i-apb0-gates.c
With sun8i PRCM support available, we can add the PRCM clock and
reset controller nodes to the DTSI. Also update R_UART's clock
phandle and add it's reset control phandle.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun8i-a23.dtsi | 47 +++-
The 8250_dw driver fails to probe if the specified clock isn't
registered at probe time. Even if a clock frequency is given,
the required clock might be gated because it wasn't properly
enabled.
This happened to me when the device is registered through DT,
and the clock was part of an MFD, the
On Tue, Jul 8, 2014 at 3:26 AM, Bjorn Andersson
bjorn.anders...@sonymobile.com wrote:
Most status bits, e.g. for GPIO and MPP input, is retrieved by reading
the interrupt status registers, so this needs to be exposed to clients.
Signed-off-by: Bjorn Andersson bjorn.anders...@sonymobile.com
On Fri, Jul 04, 2014 at 02:23:00PM +0530, Tushar Behera wrote:
snd_soc_of_parse_card_name() may be called before card-dev has been
set, which results in a kernel panic.
Applied, thanks.
signature.asc
Description: Digital signature
Hi Tejun,
On Tue, Jul 08, 2014 at 05:40:10PM -0400, Tejun Heo wrote:
Hey,
On Tue, Jul 08, 2014 at 07:49:00PM +0200, Antoine Ténart wrote:
So, yeah, it's being used both as input and output and we also have
the arguments which affect port_map, right? It does seem confusing.
I do
* Suman Anna s-a...@ti.com [140708 10:57]:
Hi Tony, Pavel,
On 07/04/2014 03:23 AM, Tony Lindgren wrote:
* Pavel Machek pa...@ucw.cz [140704 01:07]:
Hi!
The non-DT support has to be maintained for now to not break
OMAP3 legacy boot, and the legacy-style code will be cleaned
up once
* Keerthy j-keer...@ti.com [140708 22:40]:
The patch series adds the device tree nodes and the corresponding
documentation. The series also enabled tps65218 config options
in the omap2plus_defconfig.
The series is boot tested on both AM43x-epos-evm and AM437x-gp-evm.
Are the .dts changes
On Tuesday 08 July 2014, Liviu Dudau wrote:
On Mon, Jul 07, 2014 at 10:22:00PM +0100, Arnd Bergmann wrote:
I looked at the other drivers briefly, and I think you indeed fix the Tegra
driver with this but break the integrator driver as mentioned above.
The other callers of
On Fri, Jul 04, 2014 at 03:13:44PM +0200, Sylwester Nawrocki wrote:
Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
Applied both, thanks. Please use subject lines consistent with the
subsystem style.
signature.asc
Description: Digital signature
Add node for RTC.
And also making RTC regulator always-on, as RTC should be powered
always.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
[n...@ti.com: update with rtc crossbar number]
Signed-off-by: Nishanth Menon n...@ti.com
---
This patch depends on the crossbar dt patch series by Sricharan:
Add hwmod data for RTC
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: Sekhar Nori nsek...@ti.com
Reviewed-by: Rajendra Nayak rna...@ti.com
---
Changes since V1:
Rebased on top of linux-next 20140708.
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 41 +
Hi Stephen,
On Tue, Jul 08, 2014 at 01:00:23PM -0700, Stephen Boyd wrote:
Hi,
On MSM chips we have some efuses (called qfprom) where we store things
like calibration data, speed bins, etc. We need to read out data from
the efuses in various drivers like the cpufreq, thermal, etc. This
The ADC is a 3-channel signal-ended 10-bit Successive Approximation
Register (SAR) A/D Converter. It uses the supply and ground as its reference
and converts the analog input signal into 10-bit binary digital codes.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
changes since v1:
- address
On Tue, Jul 8, 2014 at 3:26 AM, Bjorn Andersson
bjorn.anders...@sonymobile.com wrote:
This introduced the device tree bindings for the gpio block found in
pm8018, pm8038, pm8058, pm8917 and pm8921 pmics from Qualcomm.
Signed-off-by: Bjorn Andersson bjorn.anders...@sonymobile.com
(...)
+-
Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
Cc: Tony Lindgren t...@atomide.com
Cc: Russell King li...@arm.linux.org.uk
Cc: Paul Walmsley p...@pwsan.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Tested-by: Kishon Vijay Abraham I kis...@ti.com
---
Changes from
This serires adds devicetree support for extcon-gpio driver.
Patch 1 - Addreses minor cleanups
Patch 2 - Adds devicetree support for esxtcon-gpio driver.
George Cherian (2):
extcon: gpio: Minor cleanups
extcon: gpio: Add dt support for the driver.
Minor Cleanups
- Order the include files in alphabetical order.
- Fix description of state_off in extcon_gpio.h
- Add a descrition for check_on_resume in extcon_gpio.h
Signed-off-by: George Cherian george.cher...@ti.com
---
drivers/extcon/extcon-gpio.c | 10 +-
Add device tree support to extcon-gpio driver.
Add devicetree binding documentation
Signed-off-by: George Cherian george.cher...@ti.com
---
.../devicetree/bindings/extcon/extcon-gpio.txt | 21
drivers/extcon/extcon-gpio.c | 28 ++
2
Hi,
Can you please check the comments below so we don't have to
add duplicate data just to remove it later on.
* Sebastian Andrzej Siewior bige...@linutronix.de [140708 11:43]:
+
+static struct omap_hwmod_irq_info dra7xx_gmac_irqs[] = {
+ { .name = c0_rx_thresh_pend, .irq = 50 +
* Lokesh Vutla lokeshvu...@ti.com [140709 01:37]:
Add node for RTC.
And also making RTC regulator always-on, as RTC should be powered
always.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
[n...@ti.com: update with rtc crossbar number]
Signed-off-by: Nishanth Menon n...@ti.com
---
This
On Wed, Jul 09, 2014 at 07:32:37AM +0100, Arnd Bergmann wrote:
On Wednesday 09 July 2014, Liviu Dudau wrote:
Maybe that assumption is guaranteed by OF, but it doesn't hold for ACPI;
ACPI can describe several I/O port apertures for a single bridge, each
associated with a different CPU
On Wed, Jul 09, 2014 at 07:20:49AM +0100, Arnd Bergmann wrote:
On Tuesday 08 July 2014, Bjorn Helgaas wrote:
On Tue, Jul 8, 2014 at 1:00 AM, Arnd Bergmann a...@arndb.de wrote:
On Tuesday 08 July 2014, Bjorn Helgaas wrote:
On Tue, Jul 01, 2014 at 07:43:28PM +0100, Liviu Dudau wrote:
On Wed, Jul 09, 2014 at 11:06:27AM +0530, Keerthy wrote:
Add fixed_uV fields for dcdc5 and dcdc6.
This doesn't apply against current code, can you please check and
resend? There were some cleanups from Felipe that just went in, it
looks like a collision with them.
signature.asc
Description:
On Wed, Jul 09, 2014 at 09:31:50AM +0100, Arnd Bergmann wrote:
On Tuesday 08 July 2014, Liviu Dudau wrote:
On Mon, Jul 07, 2014 at 10:22:00PM +0100, Arnd Bergmann wrote:
I looked at the other drivers briefly, and I think you indeed fix the
Tegra
driver with this but break the
On Tue, Jul 8, 2014 at 3:26 AM, Bjorn Andersson
bjorn.anders...@sonymobile.com wrote:
This introduces a pinctrl, pinconf, pinmux and gpio driver for the gpio
block found in pm8018, pm8038, pm8058, pm8917 and pm8921 pmics from
Qualcomm.
Signed-off-by: Bjorn Andersson
When running with device-tree, we no longer have a board file
that can set up the platform data for wlcore.
Allow this data to be passed from DT.
For now, parse only the irq used. Other (optional) properties
can be added later on.
Signed-off-by: Ido Yariv i...@wizery.com
Signed-off-by: Eliad
Hi Tony,
On Wednesday 09 July 2014 02:42 PM, Tony Lindgren wrote:
* Lokesh Vutla lokeshvu...@ti.com [140709 01:37]:
Add node for RTC.
And also making RTC regulator always-on, as RTC should be powered
always.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
[n...@ti.com: update with rtc crossbar
On Wednesday 09 July 2014 02:44 PM, Mark Brown wrote:
On Wed, Jul 09, 2014 at 11:06:27AM +0530, Keerthy wrote:
Add fixed_uV fields for dcdc5 and dcdc6.
This doesn't apply against current code, can you please check and
resend? There were some cleanups from Felipe that just went in, it
looks
Hi Jingoo,
On Tuesday 08 July 2014 06:47 PM, Jingoo Han wrote:
On Tuesday, July 08, 2014 9:31 PM, Kishon Vijay Abraham I wrote:
Hi Mohit, Jingoo,
On Wednesday 25 June 2014 11:26 PM, Kishon Vijay Abraham I wrote:
In DRA7, the cpu sees 32bit address, but the pcie controller can see only
On Wednesday 09 July 2014 12:10 AM, Sebastian Andrzej Siewior wrote:
Adding hwmod data for CPSW and MDIO which is present in DRA7xx SoC
Signed-off-by: Mugunthan V N mugunthan...@ti.com
Signed-off-by: Praveen Rao p...@ti.com
Signed-off-by: Sebastian Andrzej Siewior bige...@linutronix.de
---
On Wednesday 09 July 2014 12:10 AM, Sebastian Andrzej Siewior wrote:
From: Mugunthan V N mugunthan...@ti.com
Adding CPSW phy-id, CPSW and MDIO pinmux configuration for active
and sleep states and enable them in board evm dts file.
Signed-off-by: Mugunthan V N mugunthan...@ti.com
[Resolved
On Mon, Jul 7, 2014 at 5:11 PM, Ivan T. Ivanov iiva...@mm-sol.com wrote:
This set of patches adds pin control drivers for Multi-purpose
pin (MPP) and General-purpose pin (GPIO) controllers found
in Qualcomm PMIC chips.
MPP's are enhanced GPIO's with analog circuits, which support
following
On Thu, Jul 03, 2014 at 10:19:48AM +0800, Sean Cross wrote:
Add a codec driver for the Everest ES8328. It supports two separate audio
outputs and two separate audio inputs.
Signed-off-by: Sean Cross x...@kosagi.com
---
snip
+
+static int es8328_codec_probe(struct snd_soc_codec *codec)
On 2014-07-08 18:46:39 [+0530], Mugunthan V N wrote:
Adding hwmod data for CPSW and MDIO which is present in DRA7xx SoC
I reverted my patch, applied this one and after boot I got:
|platform 48485000.mdio: Cannot lookup hwmod 'davinci_mdio'
|cpsw 48484000.ethernet: _od_fail_runtime_resume:
On 2014-07-09 11:55:52 [+0200], Sebastian Andrzej Siewior wrote:
On 2014-07-08 18:46:39 [+0530], Mugunthan V N wrote:
Adding hwmod data for CPSW and MDIO which is present in DRA7xx SoC
I reverted my patch, applied this one and after boot I got:
Oh me dum dum. I had --dry-run…
Acked-by:
Hi,
On Wednesday 09 July 2014 12:10 AM, Sebastian Andrzej Siewior wrote:
The core complains that the number 343 is too large. The older code has
here 124. This avoids the warning, the driver hasn't been tested.
Signed-off-by: Sebastian Andrzej Siewiorbige...@linutronix.de
---
On 4 June 2014 18:07, Peter Griffin peter.grif...@linaro.org wrote:
The second controller is only present on the stih416 SoC. Also
mark this as non-removeable as its eMMC.
Signed-off-by: Giuseppe Cavallaro peppe.cavall...@st.com
Signed-off-by: Peter Griffin peter.grif...@linaro.org
Acked-by:
* Keerthy a0393...@ti.com [140709 02:36]:
On Wednesday 09 July 2014 02:42 PM, Tony Lindgren wrote:
* Lokesh Vutla lokeshvu...@ti.com [140709 01:37]:
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -249,6 +249,7 @@
* Sebastian Andrzej Siewior sebast...@breakpoint.cc [140709 03:03]:
On 2014-07-09 11:55:52 [+0200], Sebastian Andrzej Siewior wrote:
On 2014-07-08 18:46:39 [+0530], Mugunthan V N wrote:
Adding hwmod data for CPSW and MDIO which is present in DRA7xx SoC
I reverted my patch, applied this
not hitting
the bug on my board ATM). 3/3 has already been merged through a
different patchset.
I'm sending as an attachment my complete boot log when booting today's
next (20140709) until it hangs and my u-boot env vars. I hope that
helps.
--
Tushar Behera
--
Best regards,
Javier
boot_log
On 07/09/2014 12:07 PM, sourav wrote:
Hi,
Hello, Sourav,
The number is correct and is complaining just because the crossbar stuff
is not
put in. I had already posted a patch[1] to remove interrupt binding as
of now.
Hence, NAK for this patch.
Thank you for explanation. What is the
On Mon, Jul 07, 2014 at 05:50:09PM +, Paul Walmsley wrote:
On Mon, 7 Jul 2014, Andre Heider wrote:
On Sun, Jun 29, 2014 at 06:21:34PM +0200, Andre Heider wrote:
this series adds PRUv2 support to uio_pruss through devicetree, makes the
device usable on am33xx and enables it on
The ADC is a 3-channel signal-ended 10-bit Successive Approximation
Register (SAR) A/D Converter. It uses the supply and ground as its reference
and converts the analog input signal into 10-bit binary digital codes.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
changes since v2:
- address
Add fixed_uV fields for dcdc5 and dcdc6.
Signed-off-by: Keerthy j-keer...@ti.com
---
Changes from V3:
* Rebased to Latest for/tps65218 branch.
drivers/regulator/tps65218-regulator.c | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git
* Sebastian Andrzej Siewior bige...@linutronix.de [140709 03:20]:
On 07/09/2014 12:07 PM, sourav wrote:
Hi,
Hello, Sourav,
The number is correct and is complaining just because the crossbar stuff
is not
put in. I had already posted a patch[1] to remove interrupt binding as
of now.
+Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala
On Tuesday 08 July 2014 06:04 PM, Kishon Vijay Abraham I wrote:
Hi Arnd, Tony, other dt guys,
On Wednesday 25 June 2014 11:26 PM, Kishon Vijay Abraham I wrote:
Added support for pcie controller in dra7xx. This driver re-uses
Hi Ulf,
Many thanks for looking at this.
+
+ mmc1: sdhci@fe81f000 {
+ status = okay;
+ bus-width= 8;
+ non-removable;
+ };
};
Hi Peter,
I was trying to apply this
On Wednesday 09 July 2014 03:39 PM, Tony Lindgren wrote:
* Keerthy a0393...@ti.com [140709 02:36]:
On Wednesday 09 July 2014 02:42 PM, Tony Lindgren wrote:
* Lokesh Vutla lokeshvu...@ti.com [140709 01:37]:
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -249,6
On Wednesday 09 July 2014 04:20 PM, Tony Lindgren wrote:
* Keerthy a0393...@ti.com [140709 03:39]:
On Wednesday 09 July 2014 03:39 PM, Tony Lindgren wrote:
* Keerthy a0393...@ti.com [140709 02:36]:
On Wednesday 09 July 2014 02:42 PM, Tony Lindgren wrote:
* Lokesh Vutla lokeshvu...@ti.com
On Wed, Jul 09, 2014 at 02:07:38AM +0100, Olav Haugan wrote:
On 6/30/2014 2:52 AM, Will Deacon wrote:
On Fri, Jun 27, 2014 at 11:23:27PM +0100, Olav Haugan wrote:
Lets say I have an IOMMU with 2 masters and 2 SMRn slots with the
following stream IDs coming from the masters:
Master 1:
On Wed, Jul 9, 2014 at 11:31 AM, Eliad Peller el...@wizery.com wrote:
When running with device-tree, we no longer have a board file
that can set up the platform data for wlcore.
Allow this data to be passed from DT.
For now, parse only the irq used. Other (optional) properties
can be added
Hi Ulf, Peter,
I will queue the DT patches to my pull request for v3.17.
Peter, I will need it to be rebased anyway.
Thanks,
Maxime
On 07/09/2014 12:30 PM, Peter Griffin wrote:
Hi Ulf,
Many thanks for looking at this.
+
+ mmc1: sdhci@fe81f000 {
+
* Keerthy a0393...@ti.com [140709 03:59]:
On Wednesday 09 July 2014 04:20 PM, Tony Lindgren wrote:
* Keerthy a0393...@ti.com [140709 03:39]:
On Wednesday 09 July 2014 03:39 PM, Tony Lindgren wrote:
* Keerthy a0393...@ti.com [140709 02:36]:
On Wednesday 09 July 2014 02:42 PM, Tony Lindgren
On Wednesday 09 July 2014 02:01 PM, Tony Lindgren wrote:
* Keerthy j-keer...@ti.com [140708 22:40]:
The patch series adds the device tree nodes and the corresponding
documentation. The series also enabled tps65218 config options
in the omap2plus_defconfig.
The series is boot tested on both
On Wednesday 09 July 2014 02:32 PM, Kishon Vijay Abraham I wrote:
Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
Cc: Tony Lindgren t...@atomide.com
Cc: Russell King li...@arm.linux.org.uk
Cc: Paul Walmsley p...@pwsan.com
Signed-off-by: Kishon Vijay Abraham I
On Wednesday 09 July 2014 04:30 PM, Tony Lindgren wrote:
* Keerthy a0393...@ti.com [140709 03:59]:
On Wednesday 09 July 2014 04:20 PM, Tony Lindgren wrote:
* Keerthy a0393...@ti.com [140709 03:39]:
On Wednesday 09 July 2014 03:39 PM, Tony Lindgren wrote:
* Keerthy a0393...@ti.com [140709
Hi,
On Wed, 2014-07-09 at 11:43 +0200, Linus Walleij wrote:
On Mon, Jul 7, 2014 at 5:11 PM, Ivan T. Ivanov iiva...@mm-sol.com wrote:
This set of patches adds pin control drivers for Multi-purpose
pin (MPP) and General-purpose pin (GPIO) controllers found
in Qualcomm PMIC chips.
Hi Tomasz,
On 8 July 2014 21:04, Tomasz Figa t.f...@samsung.com wrote:
Hi Rahul,
On 07.07.2014 15:37, Rahul Sharma wrote:
Hi Andrej, Inki,
On 18 June 2014 12:06, Rahul Sharma rahul.sha...@samsung.com wrote:
Hi Andrej,
On 18 June 2014 11:46, Andrzej Hajda a.ha...@samsung.com wrote:
On
* Ash Charles ashchar...@gmail.com [140610 15:24]:
This adds the Gumstix Pepper[1] single-board computer based on the
TI AM335x processor. Schematics are available [2].
[1] https://store.gumstix.com/index.php/products/344/
[2] https://pubs.gumstix.com/boards/PEPPER/
Applying into
On Wed, Jul 9, 2014 at 2:00 PM, Yegor Yefremov
yegorsli...@googlemail.com wrote:
On Wed, Jul 9, 2014 at 11:31 AM, Eliad Peller el...@wizery.com wrote:
When running with device-tree, we no longer have a board file
that can set up the platform data for wlcore.
Allow this data to be passed from
On Wed, Jul 9, 2014 at 1:13 PM, Ivan T. Ivanov iiva...@mm-sol.com wrote:
On Wed, 2014-07-09 at 11:43 +0200, Linus Walleij wrote:
On Mon, Jul 7, 2014 at 5:11 PM, Ivan T. Ivanov iiva...@mm-sol.com wrote:
This set of patches adds pin control drivers for Multi-purpose
pin (MPP) and
On Wed, Jul 9, 2014 at 6:59 AM, Bjorn Andersson
bjorn.anders...@sonymobile.com wrote:
Signed-off-by: Bjorn Andersson bjorn.anders...@sonymobile.com
---
Changes since v2:
This v3 version applied.
BTW: does this cover the 8660 too or does that chip need a separate
subdriver? I'm told that the
* Keerthy a0393...@ti.com [140709 04:03]:
On Wednesday 09 July 2014 02:01 PM, Tony Lindgren wrote:
* Keerthy j-keer...@ti.com [140708 22:40]:
The patch series adds the device tree nodes and the corresponding
documentation. The series also enabled tps65218 config options
in the
On Tue, 24 Jun 2014, Lee Jones wrote:
I'm re-sending this set, as one of the maintainers' email addresses
is incorrect in the MAINTAINERS file.
This patchset adds full support for 2 types of Thermal Controllers
produced by STMicroelectronics. One is a more traditional memory
mapped
the right approach to fix Kevin's issue (unfortunately, I am not hitting
the bug on my board ATM). 3/3 has already been merged through a
different patchset.
I'm sending as an attachment my complete boot log when booting today's
next (20140709) until it hangs and my u-boot env vars. I hope
On 9 July 2014 13:00, Maxime Coquelin maxime.coque...@st.com wrote:
Hi Ulf, Peter,
I will queue the DT patches to my pull request for v3.17.
Peter, I will need it to be rebased anyway.
Okay.
I will apply patch1 and patch 2 for next.
You can add my ack for patch 9 and 10,
On 4 June 2014 18:30, Peter Griffin peter.grif...@linaro.org wrote:
This platform driver adds initial support for the SDHCI host controller
found on STMicroelectronics SoCs.
It has been tested on STiH41x b2020 platforms currently.
Signed-off-by: Giuseppe Cavallaro peppe.cavall...@st.com
On 4 June 2014 18:30, Peter Griffin peter.grif...@linaro.org wrote:
This patch adds the device tree binding documentation for the ST
SDHCI driver. It documents the differences between the core properties
described by mmc.txt and the properties used by the sdhci-st driver.
Signed-off-by:
The documentation only mentioned the generic fallback compatible property.
Add the missing SoC-specific compatible properties, which are already in
use.
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
Cc: Thomas Gleixner t...@linutronix.de
---
This patch series aims to improvide the shmobile DT bindings, DT binding
documentation, and the actual device trees.
It reduces the number of checkpatch warnings about un-documented compatible
strings in the DTSes by 50%.
The last 4 patches contain compatible strings for new R-Car Gen2 SoCs,
This patch allows to create PHYs from DT in case
if they are explicitly defined. The of_mdiobus_register() is
used for such purposes.
For backward compatibility, call of_mdiobus_register() only in case
if at least one PHY's child is defined in DT, otherwise rollback to
mdiobus_register().
The similar MDIO HW blocks is used by keystone 2 SoCs as
in Davinci SoCs:
- one in Gigabit Ethernet (GbE) Switch Subsystem
See http://www.ti.com/lit/ug/sprugv9d/sprugv9d.pdf
- one in 10 Gigabit Ethernet Subsystem
See http://www.ti.com/lit/ug/spruhj5/spruhj5.pdf
Hence, reuse Davinci MDIO
Add Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings
Documentation, listing supported SoCs and boards.
This allows to use checkpatch to validate DTSes referring to Renesas
shmobile SoCs, and boards containing those SoCs.
Signed-off-by: Geert Uytterhoeven
- r8a7792 (R-Car V2H)
- r8a7793 (R-Car M2-N)
- r8a7794 (R-Car E2)
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
---
Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 3 +++
drivers/mmc/host/sh_mobile_sdhi.c | 3 +++
2 files changed, 6 insertions(+)
diff
The similar MDIO HW blocks is used by keystone 2 SoCs as
in Davinci SoCs:
- one in Gigabit Ethernet (GbE) Switch Subsystem
See http://www.ti.com/lit/ug/sprugv9d/sprugv9d.pdf
- one in 10 Gigabit Ethernet Subsystem
See http://www.ti.com/lit/ug/spruhj5/spruhj5.pdf
Hence, reuse Davinci MDIO
The driver already supports the r8a7791 SoC, and renesas,sdhi-r8a7791
is already in use.
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
Cc: Ian Molton ian.mol...@codethink.co.uk
Cc: Chris Ball ch...@printf.net
Cc: linux-...@vger.kernel.org
---
The documentation only mentioned the generic fallback compatible property.
Add the missing SoC-specific compatible properties, some of which are
already in use.
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
Cc: Zhang Rui rui.zh...@intel.com
Cc: Eduardo Valentin eduardo.valen...@ti.com
- r8a7792 (R-Car V2H)
- r8a7793 (R-Car M2-N)
- r8a7794 (R-Car E2)
r8a7791 is now called R-Car M2-W.
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
---
Documentation/devicetree/bindings/thermal/rcar-thermal.txt | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff
The driver already supports the r8a7791 SoC, and renesas,pfc-r8a7791
is already in use.
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Laurent Pinchart laurent.pinchart+rene...@ideasonboard.com
---
- r8a7792 (R-Car V2H)
- r8a7793 (R-Car M2-N)
- r8a7794 (R-Car E2)
r8a7791 is now called R-Car M2-W.
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
---
.../devicetree/bindings/interrupt-controller/renesas,irqc.txt| 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
The thermal node used the generic compatible property only.
Add the SoC-specific one, to make it future proof.
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
---
arch/arm/boot/dts/r8a73a4.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
The Keystone 2 has MDIO HW block which are compatible
to Davinci SoCs:
See Gigabit Ethernet (GbE) Switch Subsystem
See http://www.ti.com/lit/ug/sprugv9d/sprugv9d.pdf
Hence, add corresponding DT entry for Keystone 2.
Signed-off-by: Grygorii Strashko grygorii.stras...@ti.com
---
Add DT definitions for Keystone 2 MDIO module and Ethernet PHYs for Keystone
EVMK2HX evm. And enable MDIO support for Keystone 2 SoCs.
Grygorii Strashko (3):
ARM: dts: keystone: add mdio devices entries
ARM: dts: keystone-evm: add 1g ethernet phys nodes
ARM: keystone_defconfig: enable mdio
The thermal node used the generic compatible property only.
Add the SoC-specific one, to make it future proof.
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
---
arch/arm/boot/dts/r8a7779.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Enable MDIO support for Keystone 2 SoCs and also
enable Marvell Ethernet PHYs support for Keystone 2 K2H EVM
which has two 1G Marvell 88E-B2 PHYs installed.
For more information see:
- http://www.advantech.com/Support/TI-EVM/EVMK2HX.aspx
Signed-off-by: Grygorii Strashko
The interrupt controller used the generic compatible property only.
Add the SoC-specific one, to make it future proof.
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
---
arch/arm/boot/dts/r8a73a4.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
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