The CRG11 clock controller is managed by remote f/w.
This driver simply maps Linux CLK ops onto mailbox api.
Signed-off-by: Jassi Brar jaswinder.si...@linaro.org
Cc: Arnd Bergmann a...@arndb.de
Cc: Olof o...@lixom.net
Cc: Russell King li...@arm.linux.org.uk
Signed-off-by: Tetsuya Takinishi
This patch adds new host controller driver for
Fujitsu SDHCI controller f_sdh30.
Signed-off-by: Vincent Yang vincent.y...@tw.fujitsu.com
Cc: Arnd Bergmann a...@arndb.de
Cc: Olof o...@lixom.net
Cc: Russell King li...@arm.linux.org.uk
Signed-off-by: Tetsuya Takinishi t.takini...@jp.fujitsu.com
The mb86s70 and mb86s73 Fujitsu SoCs differ in that the latter provide a pinmux.
GPIOs are supported on top of Pinctrl api.
Signed-off-by: Jassi Brar jaswinder.si...@linaro.org
Cc: Linus Walleij linus.wall...@linaro.org
Signed-off-by: Tetsuya Takinishi t.takini...@jp.fujitsu.com
Signed-off-by:
Add 'fujitsu' as the vendor prefix for Fujitsu Semiconductor Ltd.
Signed-off-by: Tetsuya Takinishi t.takini...@jp.fujitsu.com
Signed-off-by: Mollie Wu mollie...@linaro.org
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
On Sat, Jul 12, 2014 at 01:57:31PM +0100, Rob Clark wrote:
On Sat, Jul 12, 2014 at 8:22 AM, Arnd Bergmann a...@arndb.de wrote:
On Saturday 12 July 2014, Rob Clark wrote:
Was there actually a good reason for having the device link to the
iommu rather than the other way around? How much
The ADC is a 3-channel signal-ended 10-bit Successive Approximation
Register (SAR) A/D Converter. It uses the supply and ground as its reference
and converts the analog input signal into 10-bit binary digital codes.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
changes since v3:
- address
This add the necessary binding documentation for the saradc found in all recent
processors from Rockchip.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
changes since v1:
- fix typos found by Hartmut Knaack
.../bindings/iio/adc/rockchip-saradc.txt | 28 ++
1
On Sun, Jul 13, 2014 at 5:43 AM, Will Deacon will.dea...@arm.com wrote:
On Sat, Jul 12, 2014 at 01:57:31PM +0100, Rob Clark wrote:
On Sat, Jul 12, 2014 at 8:22 AM, Arnd Bergmann a...@arndb.de wrote:
On Saturday 12 July 2014, Rob Clark wrote:
Was there actually a good reason for having the
Heiko Stübner schrieb:
The ADC is a 3-channel signal-ended 10-bit Successive Approximation
Register (SAR) A/D Converter. It uses the supply and ground as its reference
and converts the analog input signal into 10-bit binary digital codes.
Is there a datasheet available anywhere, or just under
Am Sonntag, 13. Juli 2014, 14:09:48 schrieb Hartmut Knaack:
Heiko Stübner schrieb:
The ADC is a 3-channel signal-ended 10-bit Successive Approximation
Register (SAR) A/D Converter. It uses the supply and ground as its
reference and converts the analog input signal into 10-bit binary digital
Hi all,
On 10th of May I submitted 2 patches
http://thread.gmane.org/gmane.linux.drivers.devicetree/73577
of which 1 adds documentation for DT bindings for a dmaengine driver. The
driver doesn't add any new bindings, only standard bindings are used and
the respective generic document is
Suravee,
On Wed, Jul 09, 2014 at 06:05:03PM -0500, suravee.suthikulpa...@amd.com wrote:
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
ARM GICv2m specification extends GICv2 to support MSI(-X) with
a new set of register frames. This patch introduces support for
the non-secure
Suravee,
If you need to respin this series, please change the subject line to
irqchip: gic-v2m: ... If there are no other changes needed, It can be
fixed up when applied.
thx,
Jason.
On Wed, Jul 09, 2014 at 06:05:04PM -0500, suravee.suthikulpa...@amd.com wrote:
From: Suravee Suthikulpanit
Suravee,
On Wed, Jul 09, 2014 at 06:05:00PM -0500, suravee.suthikulpa...@amd.com wrote:
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
This patch set introduces support for MSI(-X) in GICv2m specification,
which is implemented in some variation of GIC400.
This depends on and
On 07/10/2014 12:36 PM, Amit Kachhap wrote:
On Wed, Jul 9, 2014 at 8:30 AM, Chanwoo Choi cw00.c...@samsung.com wrote:
On 07/01/2014 09:33 AM, Chanwoo Choi wrote:
This patch add registers, bit fields and compatible strings for Exynos3250
TMU
(Thermal Management Unit). Exynos3250 uses the
Dear Eduardo,
Could you please review or pick this patch?
Best Regards,
Chanwoo Choi
On 07/10/2014 12:36 PM, Amit Kachhap wrote:
On Wed, Jul 9, 2014 at 8:30 AM, Chanwoo Choi cw00.c...@samsung.com wrote:
On 07/01/2014 09:33 AM, Chanwoo Choi wrote:
This patch add registers, bit fields and
Correct the typo error for the second uhphs_clk.
Signed-off-by: Bo Shen voice.s...@atmel.com
---
arch/arm/boot/dts/at91sam9x5.dtsi | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi
b/arch/arm/boot/dts/at91sam9x5.dtsi
index 2ebc421..727d3a4
On Fri, Jul 11, 2014 at 04:11:03PM +0530, Varka Bhadram wrote:
On 07/11/2014 03:59 PM, Dong Aisheng wrote:
add M_CAN device tree binding documentation
Cc: Wolfgang Grandegger w...@grandegger.com
Cc: Marc Kleine-Budde m...@pengutronix.de
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Oliver
On 11 July 2014 17:16, Ashwin Chaugule ashwin.chaug...@linaro.org wrote:
Hi Jassi,
Other than a few nits, this looks good to me.
Thanks for the nits. I will club them together with other feedback on
the patchset.
Hopefully you've run this through checkpatch as well? Also, were you
able to
On 07/14/2014 08:54 AM, Dong Aisheng wrote:
On Fri, Jul 11, 2014 at 04:11:03PM +0530, Varka Bhadram wrote:
On 07/11/2014 03:59 PM, Dong Aisheng wrote:
add M_CAN device tree binding documentation
Cc: Wolfgang Grandegger w...@grandegger.com
Cc: Marc Kleine-Budde m...@pengutronix.de
Cc: Mark
On 12 July 2014 03:39, Markus Mayer markus.ma...@linaro.org wrote:
On 11 July 2014 02:35, Jassi Brar jaswinder.si...@linaro.org wrote:
Introduce common framework for client/protocol drivers and
controller drivers of Inter-Processor-Communication (IPC).
Client driver developers should have a
On Mon, Jul 14, 2014 at 10:07:06AM +0530, Varka Bhadram wrote:
On 07/14/2014 08:54 AM, Dong Aisheng wrote:
On Fri, Jul 11, 2014 at 04:11:03PM +0530, Varka Bhadram wrote:
On 07/11/2014 03:59 PM, Dong Aisheng wrote:
add M_CAN device tree binding documentation
Cc: Wolfgang Grandegger
On 11 July 2014 22:56, Arnd Bergmann a...@arndb.de wrote:
On Friday 11 July 2014, Jassi Brar wrote:
+
+ This document aims to help developers write client and controller
+drivers for the API. But before we start, let us note that the
+client (especially) and controller drivers are likely
This patch replaces the cs-gpio from controller-data node
as was specified in the old binding and use the standard
cs-gpios property expected by the SPI core as is defined in
the new binding.
Respective changes are preposed to spi-s3c64xx.c driver.
@
Use controller_data structure only for the Non Device tree platforms.
For Device tree platforms, always derive the chipselect info from
DT node.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Reviewed-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Tested-by: Doug
Since, (3146bee spi: s3c64xx: Added provision for dedicated cs pin)
spi-s3c64xx.c driver expects
1. chip select gpios from cs-gpio(singular) under the
controller-data node of the client/slave device of the SPI.
2. cs-gpio(singular) entry to be present in the SPI device node.
Eg of current
Currently, spi-s3c64xx.c needs cs-gpio chip select GPIO to be
defined under controller-data node under each slave node.
spi_x {
cs-gpios ;
...
slave_node {
controller-data {
cs-gpio = ;
...
};
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