On Mon, 14 Jul 2014 11:08:14 +0800
Bo Shen voice.s...@atmel.com wrote:
Correct the typo error for the second uhphs_clk.
Signed-off-by: Bo Shen voice.s...@atmel.com
Acked-by: Boris Brezillon boris.brezil...@free-electrons.com
sam9n12 dtsi has the same bug, I'll fix it
And sorry for the mess
On Sat, Jul 12, 2014 at 02:22:01PM +0200, Arnd Bergmann wrote:
On Saturday 12 July 2014, Rob Clark wrote:
Was there actually a good reason for having the device link to the
iommu rather than the other way around? How much would people hate it
if I just ignore the generic bindings and
On Sat, Jul 12, 2014 at 08:57:31AM -0400, Rob Clark wrote:
On Sat, Jul 12, 2014 at 8:22 AM, Arnd Bergmann a...@arndb.de wrote:
[...]
The way that Thierry's binding does that is the obvious solution to this,
and it mirrors what we do in practically every other subsystem. I definitely
want
On Sun, Jul 13, 2014 at 10:43:41AM +0100, Will Deacon wrote:
On Sat, Jul 12, 2014 at 01:57:31PM +0100, Rob Clark wrote:
On Sat, Jul 12, 2014 at 8:22 AM, Arnd Bergmann a...@arndb.de wrote:
On Saturday 12 July 2014, Rob Clark wrote:
Was there actually a good reason for having the device
On Fri, Jul 11, 2014 at 02:54:00PM +0200, Marc Kleine-Budde wrote:
On 07/11/2014 12:29 PM, Dong Aisheng wrote:
add M_CAN device tree binding documentation
Cc: Wolfgang Grandegger w...@grandegger.com
Cc: Marc Kleine-Budde m...@pengutronix.de
Cc: Mark Rutland mark.rutl...@arm.com
Cc:
Hi Mark,
My mail seems to have missed the below reply.
Anyway, please find my answer below:
-Original Message-
From: Punnaiah Choudary Kalluri
Sent: Monday, July 14, 2014 12:03 PM
To: Harini Katakam
Subject: FW: [RFC PATCH 1/2] spi: Add support for Zynq QSPI controller
Hi Mark,
On Fri, Jul 11, 2014 at 7:08 PM, Mark Brown broo...@kernel.org wrote:
On Thu, Jul 10, 2014 at 02:20:06PM +0530, Harini Katakam wrote:
This patch adds support for QSPI controller used by Zynq.
The driver looks pretty clean but there are a couple of issues below,
including a little
Hi everyone,
This series adds support for the RTC in A31 and A23 SoCs. The series
applies to sunxi-next, with the sun8i patch based on my sun8i PRCM
series.
The A31 has a new RTC block that is separate from the timer block.
It has separate interrupts for each of the alarms, and a different
Now that we have a driver for sun6i's rtc hardware, add a device node
for it so we can use it.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun6i-a31.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi
Now that we have Kconfig options for individual sunxi platforms, let
the rtc-sunxi driver depend on the platforms that actually have this
hardware, sun4i and sun7i.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/rtc/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
sun8i shares the same rtc hardware as sun6i. Now that we have a driver
for it, add a device node to the DTSI for it so we can use it.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun8i-a23.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git
This patch introduces the driver for the RTC in the Allwinner A31 and
A23 SoCs.
Unlike the RTC found in A10/A20 SoCs, which was part of the timer, the
RTC in A31/A23 are a separate hardware block, which also contain a few
controls for the RTC block hardware (a regulator and RTC block GPIO pin
Use recently introduced of_reserved_mem_device_init() function to
automatically assign respective reserved memory region to the newly created
platform and amba device.
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
drivers/of/platform.c | 7 +++
1 file changed, 7 insertions(+)
Hello,
This is one more respin of the patches which add support for creating
reserved memory regions defined in device tree. The last attempt
(http://lists.linaro.org/pipermail/linaro-mm-sig/2014-February/003738.html)
ended in merging only half of the code, so right now we have complete
Add a function to create CMA region from previously reserved memory
and add support for handling 'shared-dma-pool' reserved-memory device
tree nodes.
Based on previous code provided by Josh Cartwright jo...@codeaurora.org
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
This patch adds code for automated assignment of reserved memory regions
to struct device. reserved_mem-ops-device_init()/device_cleanup()
callbacks are called to perform reserved memory driver specific
initialization and cleanup
Based on previous code provided by Josh Cartwright
On Fri, Jul 11, 2014 at 05:43:19PM +0530, Varka Bhadram wrote:
On 07/11/2014 05:33 PM, Marc Kleine-Budde wrote:
On 07/11/2014 01:13 PM, Varka Bhadram wrote:
On 07/11/2014 03:59 PM, Dong Aisheng wrote:
(...)
+/* m_can private data structure */
+struct m_can_priv {
+struct can_priv
Hello,
On 14 July 2014 05:17, Jassi Brar jaswinder.si...@linaro.org wrote:
On 11 July 2014 17:16, Ashwin Chaugule ashwin.chaug...@linaro.org wrote:
Hi Jassi,
Other than a few nits, this looks good to me.
Thanks for the nits. I will club them together with other feedback on
the patchset.
Hello,
(please ignore previous patchset, I've attached wrong version of patches)
This is one more respin of the patches which add support for creating
reserved memory regions defined in device tree. The last attempt
(http://lists.linaro.org/pipermail/linaro-mm-sig/2014-February/003738.html)
This patch adds code for automated assignment of reserved memory regions
to struct device. reserved_mem-ops-device_init()/device_cleanup()
callbacks are called to perform reserved memory driver specific
initialization and cleanup
Based on previous code provided by Josh Cartwright
Add a function to create CMA region from previously reserved memory
and add support for handling 'shared-dma-pool' reserved-memory device
tree nodes.
Based on previous code provided by Josh Cartwright jo...@codeaurora.org
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
Use recently introduced of_reserved_mem_device_init() function to
automatically assign respective reserved memory region to the newly created
platform and amba device.
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
drivers/of/platform.c | 7 +++
1 file changed, 7 insertions(+)
Initialization procedure of dma coherent pool has been split into two
parts, so memory pool can now be initialized without assigning to
particular struct device. Then initialized region can be assigned to
more than one struct device. To protect from concurent allocations from
different devices, a
On Mon, Jul 14, 2014 at 01:05:55PM +0530, Varka Bhadram wrote:
On 07/14/2014 12:51 PM, Dong Aisheng wrote:
+dev_dbg(pdev-dev, mram_base %p sidf 0x%x %d xidf 0x%x %d rxf0
0x%x %d rxf1 0x%x %d rxb 0x%x %d txe 0x%x %d txb 0x%x %d\n,
+priv-mram_base,
+
On Fri, 11 Jul 2014, Alan Stern wrote:
On Fri, 11 Jul 2014, Peter Griffin wrote:
On Thu, 10 Jul 2014, Alan Stern wrote:
On Thu, 10 Jul 2014, Peter Griffin wrote:
This driver adds support for the USB HCD present in STi
SoC's from STMicroelectronics. It has been tested on the
On Fri, Jul 11, 2014 at 08:21:27PM +0300, Tuomas Tynkkynen wrote:
On 11/07/14 20:08, Andrew Bresticker wrote:
On Fri, Jul 11, 2014 at 9:48 AM, Tuomas Tynkkynen ttynkky...@nvidia.com
wrote:
On 11/07/14 19:28, Andrew Bresticker wrote:
On Thu, Jul 10, 2014 at 2:42 PM, Tuomas Tynkkynen
On 07/14/2014 01:54 PM, Dong Aisheng wrote:
On Mon, Jul 14, 2014 at 01:05:55PM +0530, Varka Bhadram wrote:
On 07/14/2014 12:51 PM, Dong Aisheng wrote:
+dev_dbg(pdev-dev, mram_base %p sidf 0x%x %d xidf 0x%x %d rxf0
0x%x %d rxf1 0x%x %d rxb 0x%x %d txe 0x%x %d txb 0x%x %d\n,
+
On 2014-07-13 at 08:31:47 +0200, Mollie Wu mollie...@linaro.org wrote:
This driver adds support for ogma, a Fujitsu Semiconductor Ltd IP Gigabit
Ethernet + PHY IP used in a variety of their ARM-based ASICs.
This is being sent as part of a series including the arch support that uses
it,
Hi Kukjin,
Please consider this patch for your branch. This patch is important
for Display for Exynos5 boards.
Regards,
Rahul Sharma.
On 9 July 2014 17:00, Rahul Sharma rahul.sha...@samsung.com wrote:
Hi Tomasz,
On 8 July 2014 21:04, Tomasz Figa t.f...@samsung.com wrote:
Hi Rahul,
On
On Mon, Jul 14, 2014 at 10:38:56AM +0200, Thierry Reding wrote:
On Fri, Jul 11, 2014 at 08:21:27PM +0300, Tuomas Tynkkynen wrote:
I don't think we can assume that each selector maps to a concrete register
value, though I'm not sure. include/linux/regulator/driver.h documents for
Hi Thierry,
Thank you for comment.
On 07/10/2014 04:38 PM, Thierry Reding wrote:
On Thu, Jul 10, 2014 at 10:06:07AM +0900, YoungJun Cho wrote:
On 07/10/2014 12:22 AM, Thierry Reding wrote:
On Tue, Jul 08, 2014 at 09:39:38AM +0900, YoungJun Cho wrote:
To support LCD I80 interface, the DSI
On Mon, Jul 14, 2014 at 10:12:33AM +0100, Mark Brown wrote:
On Mon, Jul 14, 2014 at 10:38:56AM +0200, Thierry Reding wrote:
On Fri, Jul 11, 2014 at 08:21:27PM +0300, Tuomas Tynkkynen wrote:
I don't think we can assume that each selector maps to a concrete register
value, though I'm not
On Mon, Jul 14, 2014 at 06:22:39PM +0900, YoungJun Cho wrote:
Hi Thierry,
Thank you for comment.
On 07/10/2014 04:38 PM, Thierry Reding wrote:
On Thu, Jul 10, 2014 at 10:06:07AM +0900, YoungJun Cho wrote:
On 07/10/2014 12:22 AM, Thierry Reding wrote:
On Tue, Jul 08, 2014 at 09:39:38AM
On Thu, Jul 10, 2014 at 06:12:48PM +0300, Tuomas Tynkkynen wrote:
Thierry,
Since Stephen's on a vacation, I'd like to double-check with you that the DT
changes looks good. Greg has applied these to the USB tree today.
Yes, looks sane to me. Not sure how much people will like to see the DTS
On Tue, Jul 8, 2014 at 9:24 PM, Stanimir Varbanov svarba...@mm-sol.com wrote:
From: Josh Cartwright jo...@codeaurora.org
The Qualcomm QPNP PMIC chips are components used with the
Snapdragon 800 series SoC family. This driver exists
largely as a glue mfd component, it exists to be an owner
On Fri, Jul 11, 2014 at 04:19:49PM +0100, Jacek Anaszewski wrote:
JPEG IP on Exynos3250 SoC requires enabling two clock
gates for its operation. This patch documents this
requirement.
Signed-off-by: Jacek Anaszewski j.anaszew...@samsung.com
Signed-off-by: Kyungmin Park
Hi Thierry,
On Mon, Jul 14, 2014 at 07:44:53AM +0100, Thierry Reding wrote:
On Sun, Jul 13, 2014 at 10:43:41AM +0100, Will Deacon wrote:
My plan for the ARM SMMU driver is:
(1) Change -probe() to walk the device-tree looking for all masters with
phandles back to the SMMU
On Mon, Jul 14, 2014 at 2:24 AM, Thierry Reding
thierry.red...@gmail.com wrote:
On Sat, Jul 12, 2014 at 08:57:31AM -0400, Rob Clark wrote:
On Sat, Jul 12, 2014 at 8:22 AM, Arnd Bergmann a...@arndb.de wrote:
[...]
The way that Thierry's binding does that is the obvious solution to this,
and
On Mon, Jul 07, 2014 at 06:42:59PM +0200, Boris BREZILLON wrote:
The Atmel HLCDC (HLCD Controller) IP available on some Atmel SoCs (i.e.
at91sam9n12, at91sam9x5 family or sama5d3 family) provides a display
controller device.
The HLCDC block provides a single RGB output port, and only
On Fri, Jul 11, 2014 at 02:00:25PM +0200, Boris BREZILLON wrote:
On Fri, 11 Jul 2014 12:37:46 +0200 Laurent Pinchart
laurent.pinch...@ideasonboard.com wrote:
On Thursday 10 July 2014 14:56:26 Boris BREZILLON wrote:
[...]
BTW, is there any reason for not defining an RGB connector type (I'm
Hi Mark,
thanks a lot for your feedback! Much appreciated.
On 07/14/2014 11:52 AM, Mark Rutland wrote:
On Fri, Jul 11, 2014 at 11:06:33AM +0100, Daniel Mack wrote:
+++ b/Documentation/devicetree/bindings/input/cap1106.txt
@@ -0,0 +1,63 @@
+Device tree bindings for Microchip CAP1106, 6
On Wednesday 09 July 2014 04:32 PM, Rajendra Nayak wrote:
On Wednesday 09 July 2014 02:32 PM, Kishon Vijay Abraham I wrote:
Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
Cc: Tony Lindgren t...@atomide.com
Cc: Russell King li...@arm.linux.org.uk
Cc: Paul Walmsley
On 14 July 2014 17:06, Tobias Klauser tklau...@distanz.ch wrote:
On 2014-07-13 at 08:31:47 +0200, Mollie Wu mollie...@linaro.org wrote:
This driver adds support for ogma, a Fujitsu Semiconductor Ltd IP Gigabit
Ethernet + PHY IP used in a variety of their ARM-based ASICs.
This is being sent as
From: Keerthy j-keer...@ti.com
Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck
from dpll_pcie_ref_ck.
Figure 26-22. DPLL_PCIE_REF Functional Block Diagram in vE of DRA7xx ES1.0 TRM
shows the signal name for the output of post divider (M2) is CLKOUTLDO.
Figure 26-21. PCIe PHY
Added missing clocks used by second instance of PCIe PHY.
The documention for this nodes can be found @ ../bindings/clock/ti/gate.txt.
Cc: Rajendra Nayak rna...@ti.com
Cc: Tero Kristo t-kri...@ti.com
Cc: Paul Walmsley p...@pwsan.com
Cc: Tony Lindgren t...@atomide.com
Cc: Rob Herring
There are two instances of PCIe PHY in DRA7xx. So renamed
optfclk_pciephy_32khz, optfclk_pciephy_clk and optfclk_pciephy_div_clk to
optfclk_pciephy1_32khz, optfclk_pciephy1_clk and optfclk_pciephy1_div_clk
respectively. This is needed for adding the clocks for second PCIe PHY
instance.
Cc:
Added dt data for PCIe PHY as a child node of ocp2scp3.
The documention for this node can be found @ ../bindings/phy/ti-phy.txt.
26.3.3 PCIe Shared PHY Subsystem Integration in vE of DRA7xx ES1.0
describes the PCIe PHY subsystem-related components integrated in the device.
Cc: Tony Lindgren
Added missing 32KHz clock used by PCIe PHY.
Figure 26-19. PCIe PHY Subsystem Integration in vE of DRA7xx ES1.0 TRM shows
32KHz is used by PCIe PHY.
Cc: Rajendra Nayak rna...@ti.com
Cc: Tero Kristo t-kri...@ti.com
Cc: Paul Walmsley p...@pwsan.com
Cc: Tony Lindgren t...@atomide.com
Cc: Rob Herring
Added dt data for PCIe controller. This node contains dt data for
both the DRA7 part of designware controller and for the designware core.
The documention for this node can be found @ ../bindings/pci/ti-pci.txt.
Cc: Tony Lindgren t...@atomide.com
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll
Added dt data for PCIe PHY control module used by PCIe PHY.
The documention for this node can be found @ ../bindings/phy/ti-phy.txt
Cc: Tony Lindgren t...@atomide.com
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Kumar Gala
[1] is split into separate series in order for individual subsystem
Maintainers to pick up the patches. This series handles the PCIe
dt data for DRA7.
This series has better commit logs than the previous one modified as
suggested by Tero.
[1] - https://lkml.org/lkml/2014/5/29/258
Keerthy (2):
Hi Thierry,
On 07/14/2014 06:41 PM, Thierry Reding wrote:
On Mon, Jul 14, 2014 at 06:22:39PM +0900, YoungJun Cho wrote:
Hi Thierry,
Thank you for comment.
On 07/10/2014 04:38 PM, Thierry Reding wrote:
On Thu, Jul 10, 2014 at 10:06:07AM +0900, YoungJun Cho wrote:
On 07/10/2014 12:22 AM,
From: Keerthy j-keer...@ti.com
Add divider table to optfclk_pciephy_div clock. The 8th bit of
CM_CLKMODE_APLL_PCIE can be programmed to either 0x0 or 0x1
based on if the divider value is 0x2 or 0x1.
Figure 26-21. PCIe PHY Clock Generator Overview in vE of DRA7xx ES1.0 shows the
block diagram of
On Mon, Jul 14, 2014 at 07:45:28PM +0900, YoungJun Cho wrote:
On 07/14/2014 06:41 PM, Thierry Reding wrote:
[...]
That said, I've been doing some research and it seems like we have a
somewhat similar feature on Tegra. What happens there is that there are
three GPIO pins that can be repurposed
On 30/06/14 20:46, Mark Brown wrote:
On Wed, Jun 18, 2014 at 06:22:30PM +0200, Sylwester Nawrocki wrote:
+struct odroidx2_drv_data odroidx2_drvdata = {
+.dapm_widgets = odroidx2_dapm_widgets,
+.num_dapm_widgets = ARRAY_SIZE(odroidx2_dapm_widgets),
+};
+
+struct
On Mon, Jul 14, 2014 at 01:27:53PM +0200, Sylwester Nawrocki wrote:
Too bad, I noticed this comment only just now. I'll consider this and
will try again and see how simple-card could be used. There is also the
samsung-i2s-sec secondary 'overlay' CPU DAI that would need to be handled,
and we
This series are based on drivers added by Simon Glass to the Chrome OS
kernel and adds support for the Maxim 77802 Power Management IC, their
regulators, clocks, RTC and i2c interface.
This is a v8 of the patch-set that addresses issues pointed out in v7.
Individual changes are added on each
Add Device Tree binding documentation for Maxim 77802 PMIC.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Changes since v7:
- Remove information about DVS since that will be added as a follow up.
Changes since v6: None
Changes since v5:
- Use max77686,*
Maxim MAX77802 is a power management chip that contains 10 high
efficiency Buck regulators, 32 Low-dropout (LDO) regulators used
to power up application processors and peripherals, a 2-channel
32kHz clock outputs, a Real-Time-Clock (RTC) and a I2C interface
to program the individual regulators,
The MAX7802 PMIC has a Real-Time-Clock (RTC) with two alarms.
This patch adds support for the RTC and is based on a driver
added by Simon Glass to the Chrome OS kernel 3.8 tree.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Reviewed-by: Krzysztof Kozlowski
The cases should comes before default in a switch.
Even if we want the case and default to share same code.
Its good to define the case first followed by default.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: gre...@linuxfoundation.org
---
drivers/tty/serial/samsung.c |2
This patch set does the following
1: Get fifosize from DT node. But, not mandating it.
2. Corrects the case and default order in a switch
3. Defines a variable to simply the code.
Console messages on Exynos5420 based peach pit and pi works fine.
Naveen Krishna Chatradhi (3):
serial: samsung:
UART modules on some SoCs only differ in the fifosize of each
UART channel. Its useless to duplicate the drv_data structure
or create a compatible name for such a change.
We can get fifosize via the device tree nodes (not mandating it).
Also updates the documentation.
Signed-off-by: Naveen
The of_node is derived from pdev for every usage, define a
device_node variable instead.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: gre...@linuxfoundation.org
---
drivers/tty/serial/samsung.c |9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git
From: Doug Anderson diand...@chromium.org
The max77686 includes an RTC that keeps power during suspend. It's
convenient to be able to use it as a wakeup source.
NOTE: due to wakeup ordering problems this patch alone doesn't work so
well on exynos5250-snow. You also need something that brings
This patch adds a dt-binding include for Maxim 77686
PMIC clock IDs that can be used by both the max77686
clock driver and Device Tree source files.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Reviewed-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Reviewed-by: Mike
The MAX77686 RTC chip has two features called SMPL (Sudden Momentary
Power Loss) and WTSR (Watchdog Timeout and Software Resets).
Support for these features seems to be implemented in the driver but
compilation is disabled using a C pre-processor conditional.
This code has been disabled since the
The MAX77802 PMIC has 10 high-efficiency Buck and 32 Low-dropout
(LDO) regulators. This patch adds support for all these regulators
found on the MAX77802 PMIC and is based on a driver added by Simon
Glass to the Chrome OS kernel 3.8 tree.
Signed-off-by: Javier Martinez Canillas
add M_CAN device tree binding documentation
Cc: Wolfgang Grandegger w...@grandegger.com
Cc: Marc Kleine-Budde m...@pengutronix.de
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Oliver Hartkopp socket...@hartkopp.net
Cc: Varka Bhadram varkabhad...@gmail.com
Signed-off-by: Dong Aisheng
Like most clock drivers, the Maxim 77686 PMIC clock binding
follows the convention that the #clock-cells property is
used to specify the number of cells in a clock provider.
But the binding document is not clear enough that it shall
be set to 1 since the PMIC support multiple clocks outputs.
Clocks drivers for Maxim PMIC are very similar so they can
be converted to use the generic Maxim clock driver.
Also, while being there use module_platform_driver() helper
macro to eliminate more boilerplate code.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Maxim Integrated Power Management ICs are very similar with
regard to their clock outputs. Most of the clock drivers for
these chips are duplicating code and are simpler enough that
can be converted to use a generic driver to consolidate code
and avoid duplication.
Signed-off-by: Javier Martinez
The patch adds the basic CAN TX/RX function support for Bosch M_CAN controller.
For TX, only one dedicated tx buffer is used for sending data.
For RX, RXFIFO 0 is used for receiving data to avoid overflow.
Rx FIFO 1 and Rx Buffers are not used currently, as well as Tx Event FIFO.
Due to the
The MAX77802 PMIC has two 32.768kHz Buffered Clock Outputs with
Low Jitter Mode. This patch adds support for these two clocks.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Reviewed-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
Changes since v6: None
Changes
This partly reverts the following commits to get the wifi working on
the Pandaboard OMAP4430 ES2.2.
0e8e5c34cf1a8beaaf0a6a05c053592693bf8cb4 regulator: twl: Remove references to
32kHz clock from DT bindings
d1924519fe1dada0cfd9a228bf2ff1ea15840c84 regulator: twl: Remove
TWL6030_FIXED_RESOURCE
On Mon, Jul 14, 2014 at 01:50:55PM +0200, Stefan Assmann wrote:
This partly reverts the following commits to get the wifi working on
the Pandaboard OMAP4430 ES2.2.
0e8e5c34cf1a8beaaf0a6a05c053592693bf8cb4 regulator: twl: Remove references to
32kHz clock from DT bindings
On 07/14/2014 01:40 PM, Dong Aisheng wrote:
add M_CAN device tree binding documentation
Cc: Wolfgang Grandegger w...@grandegger.com
Cc: Marc Kleine-Budde m...@pengutronix.de
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Oliver Hartkopp socket...@hartkopp.net
Cc: Varka Bhadram
On 14.07.2014 14:00, Mark Brown wrote:
On Mon, Jul 14, 2014 at 01:50:55PM +0200, Stefan Assmann wrote:
This partly reverts the following commits to get the wifi working on
the Pandaboard OMAP4430 ES2.2.
0e8e5c34cf1a8beaaf0a6a05c053592693bf8cb4 regulator: twl: Remove references to
32kHz
Add cadence-wdt bindings documentation.
Signed-off-by: Harini Katakam hari...@xilinx.com
---
v3 changes:
- Change reset property type and improve description.
- Improve description of clocks and interrupts.
- Use watchdog@ in the example.
- Use only cdns compatible string for now.
v2:
No
Add Cadence WDT driver. This is used by Xilinx Zynq.
Signed-off-by: Harini Katakam hari...@xilinx.com
---
v3 changes:
- Make rst a boolean and use of_property_read_boolean.
- Use only cdns compatible string. If customization is required in the
future, xlnx compatible string can be added.
v2
On 07/14/2014 05:10 PM, Dong Aisheng wrote:
(...)
diff --git a/drivers/net/can/m_can/Makefile b/drivers/net/can/m_can/Makefile
new file mode 100644
index 000..a6aae67
--- /dev/null
+++ b/drivers/net/can/m_can/Makefile
@@ -0,0 +1,7 @@
+#
+# Makefile for the Bosch M_CAN controller drivers.
On 07/14/2014 02:47 PM, Varka Bhadram wrote:
On 07/14/2014 05:10 PM, Dong Aisheng wrote:
(...)
diff --git a/drivers/net/can/m_can/Makefile
b/drivers/net/can/m_can/Makefile
new file mode 100644
index 000..a6aae67
--- /dev/null
+++ b/drivers/net/can/m_can/Makefile
@@ -0,0 +1,7 @@
On Wed, 09 Jul 2014, Lee Jones wrote:
On Wed, 09 Jul 2014, Zhang Rui wrote:
On Wed, 2014-07-09 at 13:08 +0100, Lee Jones wrote:
On Tue, 24 Jun 2014, Lee Jones wrote:
I'm re-sending this set, as one of the maintainers' email addresses
is incorrect in the MAINTAINERS file.
On 07/14/2014 06:31 PM, Marc Kleine-Budde wrote:
On 07/14/2014 02:47 PM, Varka Bhadram wrote:
On 07/14/2014 05:10 PM, Dong Aisheng wrote:
(...)
diff --git a/drivers/net/can/m_can/Makefile
b/drivers/net/can/m_can/Makefile
new file mode 100644
index 000..a6aae67
--- /dev/null
+++
On Wed, 2014-07-09 at 14:18 -0700, Bjorn Andersson wrote:
On Wed, Jul 9, 2014 at 1:53 AM, Linus Walleij linus.wall...@linaro.org
wrote:
On Tue, Jul 8, 2014 at 3:26 AM, Bjorn Andersson
bjorn.anders...@sonymobile.com wrote:
[...]
+
+ pm8921_gpio: gpio@150 {
+
On Sunday 13 July 2014 14:28:31 Mollie Wu wrote:
The MB86S7X is a bigLITTLE configuration of 2xCA7 2xCA15 under Linux.
And the remote master firmware (called SCB) running on CM3. Linux asks
for things to be done over Mailbox API, to SCB which controls most of
the important things. variations
On 07/14/2014 02:16 PM, Harini Katakam wrote:
Add cadence-wdt bindings documentation.
Signed-off-by: Harini Katakam hari...@xilinx.com
---
v3 changes:
- Change reset property type and improve description.
- Improve description of clocks and interrupts.
- Use watchdog@ in the example.
-
Hi Lee,
On 07/11/2014 12:07 PM, Lee Jones wrote:
On Thu, 10 Jul 2014, Stanimir Varbanov wrote:
The Qualcomm QPNP PMIC chips are components used with the
Snapdragon 800 series SoC family. This driver exists
largely as a glue mfd component, it exists to be an owner
of an SPMI regmap for
Hi,
I forgot to address one of the comments.
From: Guenter Roeck [mailto:groe...@gmail.com] On Behalf Of Guenter
Roeck
Sent: Wednesday, July 09, 2014 6:58 PM
To: Kamil Debski
Cc: devicetree@vger.kernel.org; linux-ker...@vger.kernel.org; lm-
sens...@lm-sensors.org; t.f...@samsung.com;
On Fri, 2014-07-11 at 18:56 -0700, Stephen Boyd wrote:
On 07/10/14 02:53, Linus Walleij wrote:
On Wed, Jul 9, 2014 at 11:18 PM, Bjorn Andersson bj...@kryo.se wrote:
On Wed, Jul 9, 2014 at 1:53 AM, Linus Walleij linus.wall...@linaro.org
wrote:
On Tue, Jul 8, 2014 at 3:26 AM, Bjorn
On Sunday 13 July 2014 14:30:52 Mollie Wu wrote:
---
.../bindings/clock/fujitsu,mb86s7x_clk.txt | 32 ++
drivers/clk/Makefile | 1 +
drivers/clk/clk-mb86s7x.c | 352
+
3 files changed, 385 insertions(+)
On Sunday 13 July 2014 22:00:11 Guennadi Liakhovetski wrote:
Hi all,
On 10th of May I submitted 2 patches
http://thread.gmane.org/gmane.linux.drivers.devicetree/73577
of which 1 adds documentation for DT bindings for a dmaengine driver. The
driver doesn't add any new bindings, only
On 2014-07-14 at 15:50:35 +0200, Kamil Debski k.deb...@samsung.com wrote:
The pwm-fan driver enables control of fans connected to PWM lines.
This driver uses the PWM framework, so it is compatible with all
PWM devices that provide drivers through the PWM framework.
Signed-off-by: Kamil
On Mon, 14 Jul 2014, Zhang Rui wrote:
On Mon, 2014-07-14 at 14:08 +0100, Lee Jones wrote:
On Wed, 09 Jul 2014, Lee Jones wrote:
On Wed, 09 Jul 2014, Zhang Rui wrote:
On Wed, 2014-07-09 at 13:08 +0100, Lee Jones wrote:
On Tue, 24 Jun 2014, Lee Jones wrote:
I'm
This patch adds a driver for Microchips CAP1106, an I2C driven, 6-channel
capacitive touch sensor.
For now, only the capacitive buttons are supported, and no specific
settings that can be tweaked for individual channels, except for the
device-wide sensitivity gain. The defaults seem to work just
Hi Thierry,
I'm pretty sure all of your review comments have been tended to
now. Some have been fixed-up by myself and re-rolled into the
original set. The larger changes have been fixed as subsequent
patches for ease of review and history tracking on the internal
kernel.
Kind regards,
Lee
Supply top level nodes for the STiH416 based development boards.
The Pinctrl configuration has already been applied, so the only
missing piece of the DT puzzle is for a board's DTB to enable
the nodes.
Signed-off-by: Ajit Pal Singh ajitpal.si...@st.com
Signed-off-by: Lee Jones
Supply the Pinctrl configuration to enable PWM{0,1} lines on STiH416
based development boards.
Signed-off-by: Ajit Pal Singh ajitpal.si...@st.com
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
arch/arm/boot/dts/stih416-pinctrl.dtsi | 50 ++
1 file changed, 50
All the infrastructure is now in place for ST's PWM controller. This
patch takes the final step and enables the IP on the 2020 Rev-E
development platform.
Signed-off-by: Ajit Pal Singh ajitpal.si...@st.com
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
arch/arm/boot/dts/stih416-b2020e.dts |
Supply top level nodes for the STiH407 based development boards.
The Pinctrl configuration has already been applied, so the only
missing piece of the DT puzzle is for a board's DTB to enable
the nodes.
Signed-off-by: Ajit Pal Singh ajitpal.si...@st.com
Signed-off-by: Lee Jones
1 - 100 of 198 matches
Mail list logo
