Hi Fabio,
Am 10.09.2014 20:54, schrieb Fabio Estevam:
Hi Stefan,
On Wed, Sep 10, 2014 at 2:32 PM, Stefan Wahren i...@lategoodbye.de wrote:
Hi Mark,
Am 10.09.2014 17:13, schrieb Mark Brown:
On Wed, Sep 10, 2014 at 03:18:53PM +0100, Mark Rutland wrote:
On Tue, Sep 09, 2014 at 08:17:17PM
On Wednesday 10 September 2014 07:31 PM, Nishanth Menon wrote:
On 09/10/2014 08:37 AM, Mugunthan V N wrote:
Adding device tree entry for CPSW to make it work in Dual EMAC mode.
These patches were tested with DRA7 hwmod patches on top of linux-next.
Patches are tested on top of Nishanth's PM
On Thursday 11 September 2014 07:08 AM, Lennart Sorensen wrote:
On Wed, Sep 10, 2014 at 07:07:26PM +0530, Mugunthan V N wrote:
Add CPSW and MDIO related device tree data for DRA7XX and made as status
disabled. Phy-id, pinmux for active and sleep state needs to be added in
board dts files and
On Wednesday 10 September 2014 07:20 PM, Nishanth Menon wrote:
On 09/10/2014 08:37 AM, Mugunthan V N wrote:
Add CPSW and MDIO related device tree data for DRA7XX and made as status
disabled. Phy-id, pinmux for active and sleep state needs to be added in
board dts files and enable the CPSW
On 09/11/2014 06:08 AM, Keith Lugsden wrote:
I was asked by Freescale to post this kernel BUG to you and your email
address appears in the kernel documentation, so please accept my
apologies if you did not wish to see this.
Thanks for the bug report.
A kernel BUG is triggered during a CAN
On Thu, Sep 04, 2014 at 06:43:05PM +0200, Markus Niebel wrote:
From: Markus Niebel markus.nie...@tq-group.com
using LVDS channel 1 on an i.MX53 leads to following error:
imx-ldb 53fa8008.ldb: unable to set di0 parent clock to ldb_di1
This comes from imx_ldb_set_clock with mux = 0. Mux
On Wed, 2014-09-10 at 14:11 -0500, atull wrote:
[]
static int dwapb_gpio_probe(struct platform_device *pdev)
{
+ int i;
struct resource *res;
struct dwapb_gpio *gpio;
- struct device_node *np;
int err;
- unsigned int offs = 0;
+ struct device *dev =
On Wed, Sep 10, 2014 at 01:30:12PM +0800, Robin Gong wrote:
There is one weird data in rxfifo after one full rx/tx transfer
done sometimes. It looks a design issue and hard to workaround
totally, so disable dma functhion here. And will re-enable it
once the root cause found.
Signed-off-by:
-Original Message-
From: Arnd Bergmann [mailto:a...@arndb.de]
Sent: Tuesday, September 09, 2014 7:50 PM
To: linux-arm-ker...@lists.infradead.org
Cc: Lu Jingchang-B35083; Guo Shawn-R65073; devicetree@vger.kernel.org;
Zhao Chenhui-B35336; Fu Chao-B44548; Leekha Shaveta-B20052; Gupta Suresh-
-Original Message-
From: Arnd Bergmann [mailto:a...@arndb.de]
Sent: Tuesday, September 09, 2014 7:53 PM
To: linux-arm-ker...@lists.infradead.org
Cc: Lu Jingchang-B35083; Guo Shawn-R65073; devicetree@vger.kernel.org;
Zhao Chenhui-B35336; Fu Chao-B44548; Leekha Shaveta-B20052; Gupta Suresh-
On 09/05/2014 05:34 PM, Lorenzo Pieralisi wrote:
On Fri, Sep 05, 2014 at 10:21:20AM +0100, Will Deacon wrote:
On Thu, Sep 04, 2014 at 06:29:10PM +0100, Lorenzo Pieralisi wrote:
On Thu, Sep 04, 2014 at 05:03:20PM +0100, Catalin Marinas wrote:
On Wed, Sep 03, 2014 at 06:37:40PM +0100, Lorenzo
On Wed, 10 Sep 2014 18:28:39 +0200
Arnd Bergmann a...@arndb.de wrote:
On Wednesday 10 September 2014 17:59:41 Alban Bedel wrote:
On Wed, 10 Sep 2014 17:51:36 +0200
Arnd Bergmann a...@arndb.de wrote:
On Wednesday 10 September 2014 17:43:42 Alban Bedel wrote:
+- #pwm-cells: should be
When I have time yes for sure...:D
Denis
On 09/10/14 15:36, Pavel Machek wrote:
Hi!
I'm sorry but I was in business trip. I think that current lis3lv02d
supports more things, I want to support everything in the current IIO
drivers but always I have no time.
Ok then, can you add hwmon
On 9 September 2014 08:58, kg...@kernel.org wrote:
Naveen Krishna Chatradhi wrote:
Add initial device tree nodes for EXYNOS7 SoC and board dts file
to support Espresso board based on Exynos7 SoC.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Rob Herring r...@kernel.org
On 09/10/2014 01:14 AM, Mike Turquette wrote:
Quoting Jyri Sarha (2014-09-05 05:21:34)
The added gpio-gate-clock is a basic clock that can be enabled and
disabled trough a gpio output. The DT binding document for the clock
is also added. For EPROBE_DEFER handling the registering of the clock
Am Mittwoch, den 10.09.2014, 16:46 +0300 schrieb Dmitry Lavnikevich:
Since pins and frequency are specific to module (pfla02), not base board
(pbab02), it is better to be initialized in corresponding dts file.
Signed-off-by: Dmitry Lavnikevich d.lavnikev...@sam-solutions.com
I have seen
Add of_match_table to the existing driver so that rtc nodes defined in at91
DTs can be attached to this driver.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
---
drivers/rtc/rtc-at91sam9.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/rtc/rtc-at91sam9.c
The RTT block is using the slow clock which is accessible through the clk
API.
Use the clk API to retrieve, enable and get the slow clk rate instead of
the AT91_SLOW_CLOCK macro (which hardcodes the slow clk rate).
Doing this allows us to reference the clk thus preventing the CCF from
disabling it
-Original Message-
From: Gupta Suresh-B42813
Sent: Thursday, September 11, 2014 4:42 PM
To: Lu Jingchang-B35083; Guo Shawn-R65073
Cc: linux-arm-ker...@lists.infradead.org; devicetree@vger.kernel.org; Lu
Jingchang-B35083; Badola Nikhil-B46172; Zhao Chenhui-B35336; Leekha
Shaveta-B20052;
First export the clk32k clk.
Then add clk_lookup entries for RTT devices so that rtc-at91sam9 driver
can retrieve and manipulate the slow clk.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
---
arch/arm/mach-at91/at91sam9260.c | 2 ++
arch/arm/mach-at91/at91sam9261.c | 2 ++
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
---
.../devicetree/bindings/rtc/atmel,at91sam9-rtc.txt | 24 ++
1 file changed, 24 insertions(+)
create mode 100644 Documentation/devicetree/bindings/rtc/atmel,at91sam9-rtc.txt
diff --git
Hello,
This patch series adds DT support to the atmel at91sam9 RTC driver.
It also removes any machine specific inclusions to prepare the migration
to multi platform kernel support, and retain the slow clock to prevent
the CCF from disabling it at the end of boot.
Johan, let me know if this
In order to support multi platform kernel drivers should not include
machine specific headers.
Copy RTT macros in the driver code and remove any machine specific
headers.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
---
drivers/rtc/rtc-at91sam9.c | 22 ++
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
---
drivers/rtc/rtc-at91sam9.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/rtc/rtc-at91sam9.c b/drivers/rtc/rtc-at91sam9.c
index 51f0038..74a9ca0 100644
--- a/drivers/rtc/rtc-at91sam9.c
+++
The GPBR registers are not part of the RTT block and thus should not be
defined in the reg property of the rtt node.
Use syscon to provide a proper DT representation and reference the GPBR
syscon device in a new atmel,time-reg property which store both the
syscon device phandle and the register
On Mon, Aug 25, 2014 at 6:19 PM, Jonathan Cameron ji...@kernel.org wrote:
On 23/08/14 18:31, Linus Walleij wrote:
This adds support for the LIS3LV02 accelerometer found in the
ST Microelectronics Nomadik board series.
Cc: devicetree@vger.kernel.org
Cc: Denis CIOCCA denis.cio...@st.com
Cc:
-Original Message-
From: Jingchang Lu [mailto:jingchang...@freescale.com]
Sent: Tuesday, September 09, 2014 2:42 PM
To: Guo Shawn-R65073
Cc: linux-arm-ker...@lists.infradead.org; devicetree@vger.kernel.org; Lu
Jingchang-B35083; Badola Nikhil-B46172; Zhao Chenhui-B35336; Gupta
On 11 Sep 2014 12:30, Doug Anderson writes:
We should be able to talk to the PMIC at 400kHz. No need to talk at
the slow 100kHz.
As measured by ftrace (with a bunch of extra patches, since cpufreq
for rk808 hasn't landed yet):
before this change: cpu0_set_target() = ~500us
after this
Am Mittwoch, 10. September 2014, 21:30:15 schrieb Doug Anderson:
We should be able to talk to the PMIC at 400kHz. No need to talk at
the slow 100kHz.
As measured by ftrace (with a bunch of extra patches, since cpufreq
for rk808 hasn't landed yet):
before this change: cpu0_set_target() =
On 09/11/2014 10:57 AM, Lorenzo Pieralisi wrote:
On Thu, Sep 11, 2014 at 09:28:06AM +0100, Daniel Lezcano wrote:
On 09/05/2014 05:34 PM, Lorenzo Pieralisi wrote:
On Fri, Sep 05, 2014 at 10:21:20AM +0100, Will Deacon wrote:
On Thu, Sep 04, 2014 at 06:29:10PM +0100, Lorenzo Pieralisi wrote:
On
On Thursday 11 September 2014 10:36:21 Alban Bedel wrote:
On Wed, 10 Sep 2014 18:28:39 +0200
Arnd Bergmann a...@arndb.de wrote:
On Wednesday 10 September 2014 17:59:41 Alban Bedel wrote:
On Wed, 10 Sep 2014 17:51:36 +0200
Arnd Bergmann a...@arndb.de wrote:
On Wednesday 10
On Thu, Sep 11, 2014 at 10:56:07AM +0200, Boris BREZILLON wrote:
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
---
.../devicetree/bindings/rtc/atmel,at91sam9-rtc.txt | 24
++
1 file changed, 24 insertions(+)
create mode 100644
-Original Message-
From: Arnd Bergmann [mailto:a...@arndb.de]
Sent: Wednesday, September 10, 2014 3:42 PM
To: Lu Jingchang-B35083
Cc: linux-arm-ker...@lists.infradead.org; Guo Shawn-R65073;
devicetree@vger.kernel.org
Subject: Re: [PATCHv3 5/6] ARM: imx: Add initial support for Freescale
On Thu, 11 Sep 2014 11:41:00 +0200
Johan Hovold jo...@kernel.org wrote:
On Thu, Sep 11, 2014 at 10:56:04AM +0200, Boris BREZILLON wrote:
The GPBR registers are not part of the RTT block and thus should not be
defined in the reg property of the rtt node.
Use syscon to provide a proper DT
On Thu, 11 Sep 2014 11:42:13 +0200
Johan Hovold jo...@kernel.org wrote:
On Thu, Sep 11, 2014 at 10:56:07AM +0200, Boris BREZILLON wrote:
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
---
.../devicetree/bindings/rtc/atmel,at91sam9-rtc.txt | 24
++
-Original Message-
From: Arnd Bergmann [mailto:a...@arndb.de]
Sent: Wednesday, September 10, 2014 3:42 PM
To: Lu Jingchang-B35083
Cc: linux-arm-ker...@lists.infradead.org; Guo Shawn-R65073;
devicetree@vger.kernel.org
Subject: Re: [PATCHv3 5/6] ARM: imx: Add initial support for Freescale
On Thu, 11 Sep 2014 11:39:42 +0200
Johan Hovold jo...@kernel.org wrote:
On Thu, Sep 11, 2014 at 10:55:59AM +0200, Boris BREZILLON wrote:
Johan, let me know if this version addresses part of your concerns.
Looks good to me. I just have a few minor comments on two of the patches.
I'm
-Original Message-
From: Jingchang Lu [mailto:jingchang...@freescale.com]
Sent: Tuesday, September 09, 2014 2:42 PM
To: Guo Shawn-R65073
Cc: linux-arm-ker...@lists.infradead.org; devicetree@vger.kernel.org; Lu
Jingchang-B35083; Badola Nikhil-B46172; Zhao Chenhui-B35336; Gupta Suresh-
On Thu, Sep 11, 2014 at 12:06:59PM +0200, Boris BREZILLON wrote:
On Thu, 11 Sep 2014 11:39:42 +0200
Johan Hovold jo...@kernel.org wrote:
On Thu, Sep 11, 2014 at 10:55:59AM +0200, Boris BREZILLON wrote:
Johan, let me know if this version addresses part of your concerns.
Looks good
This patchset supports new Exynos7 Samsung SoC based on Cortex-A57.
Exynos7 is a System-On-Chip (SoC) that is based on 64-bit
ARMv8 RISC processor.
The following patches are tested based on Kgene's for-next tree.
https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=for-next
While adding clock support for Exynos5260, the infrastructure to
register multiple clock controllers was introduced. Factor out the
support for registering multiple clock controller from Exynos5260
clock code to common samsung clock code so that it can be used by
other Exynos SoC which have
From: Alim Akhtar alim.akh...@samsung.com
This patch adds the necessary Kconfig entries to enable
support for the ARMv8 based Exynos7 SoC.
Signed-off-by: Alim Akhtar alim.akh...@samsung.com
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Rob Herring r...@kernel.org
Cc: Catalin
Add initial device tree nodes for EXYNOS7 SoC and board dts file
to support Espresso board based on Exynos7 SoC.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Rob Herring r...@kernel.org
Cc: Catalin Marinas catalin.mari...@arm.com
---
arch/arm64/boot/dts/Makefile
Add the fields fixed_factor_clks and nr_fixed_factor_clks to
struct exynos_cmu_info to allow registering of fixed factor
clocks as well with exynos_cmu_register_one().
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Cc: Mike Turquette
Add initial clock support for Exynos7 SoC which is required
to bring up platforms based on Exynos7.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Cc: Mike Turquette mturque...@linaro.org
---
.../devicetree/bindings/clock/exynos7-clock.txt
Allow Samsung serial driver to be usable on Exynos 64-bit SoC based
platforms.
Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Greg Kroah-Hartman gre...@linuxfoundation.org
---
drivers/tty/serial/Kconfig |2 +-
1 file
On Thu, Sep 11, 2014 at 12:36:50PM +0200, Arnd Bergmann wrote:
On Thursday 11 September 2014 08:21:58 Jingchang Lu wrote:
One more thing: these should all go into the board specific files.
The installed memory is almost always a property of the board, not the SoC,
and a lot of boards
cc'ing: devicetree
Am Dienstag, 9. September 2014, 16:54:30 schrieb Wolfram Sang:
From: Wolfram Sang wsa+rene...@sang-engineering.com
Not for upstream!
Signed-off-by: Wolfram Sang wsa+rene...@sang-engineering.com
---
arch/arm/boot/dts/r8a7790-lager.dts | 15 ++-
1 file
On Thursday 11 September 2014 08:18:43 Eduardo Valentin wrote:
As what we want is to make thermal driver have a chance to configure the
hardware shutdown registers, I'm thinking if we can do this without
representing the hardware shutdown value as a trip point.
Say,
1. parse DT, and get
Hi,
On 11/09/14 09:40, Markus Pargmann wrote:
On Wed, Sep 10, 2014 at 11:14:15AM -0700, Nicolin Chen wrote:
On Wed, Sep 10, 2014 at 7:27 AM, Markus Pargmann m...@pengutronix.de wrote:
Hi,
On Wed, Sep 10, 2014 at 04:46:46PM +0300, Dmitry Lavnikevich wrote:
This is driver for i.MX6 boards
Hello Mark,
We found an issue with module auto-loading on an I2C driver [0] and it turned
out to be a problem on how the I2C subsystem reports the module alias to
user-space. It always report modalias as i2c:dev_id even when the driver
is probed via DT. The problem with this particular driver is
In order to support multi platform kernel drivers should not include
machine specific headers.
Copy RTT macros in the driver code and remove any machine specific
headers.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
Acked-by: Alexandre Belloni
First export the clk32k clk.
Then add clk_lookup entries for RTT devices so that rtc-at91sam9 driver
can retrieve and manipulate the slow clk.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
Acked-by: Alexandre Belloni alexandre.bell...@free-electrons.com
---
The RTT block is using the slow clock which is accessible through the clk
API.
Use the clk API to retrieve, enable and get the slow clk rate instead of
the AT91_SLOW_CLOCK macro (which hardcodes the slow clk rate).
Doing this allows us to reference the clk thus preventing the CCF from
disabling it
The GPBR block provides a set of battery-backed registers that can be used
to save data which need to be kept when the system is powered down and
VDD-core is maintained by an external battery.
A typical usage is the RTT block (when used as an RTC) which needs one of
those registers to save the
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
---
.../devicetree/bindings/rtc/atmel,at91sam9-rtc.txt | 23 ++
1 file changed, 23 insertions(+)
create mode 100644 Documentation/devicetree/bindings/rtc/atmel,at91sam9-rtc.txt
diff --git
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
Acked-by: Alexandre Belloni alexandre.bell...@free-electrons.com
---
drivers/rtc/rtc-at91sam9.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/rtc/rtc-at91sam9.c b/drivers/rtc/rtc-at91sam9.c
Add of_match_table to the existing driver so that rtc nodes defined in at91
DTs can be attached to this driver.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
Acked-by: Alexandre Belloni alexandre.bell...@free-electrons.com
---
drivers/rtc/rtc-at91sam9.c | 9 +
1 file
Replace devm_ioremap calls by devm_ioremap_resource which already check
resource consistency (resource != NULL) and print an error in case of
failure.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
---
drivers/rtc/rtc-at91sam9.c | 29 ++---
1 file
The GPBR registers are not part of the RTT block and thus should not be
defined in the reg property of the rtt node.
Use syscon to provide a proper DT representation and reference the GPBR
syscon device in a new atmel,time-reg property which store both the
syscon device phandle and the register
Hello,
This patch series adds DT support to the atmel at91sam9 RTC driver.
It also removes any machine specific inclusions to prepare the migration
to multi platform kernel support, and retain the slow clock to prevent
the CCF from disabling it at the end of boot.
Best Regards,
Boris
On Thu, 11 Sep 2014 15:18:41 +0200
Boris BREZILLON boris.brezil...@free-electrons.com wrote:
The GPBR registers are not part of the RTT block and thus should not be
defined in the reg property of the rtt node.
Use syscon to provide a proper DT representation and reference the GPBR
syscon
The GPBR registers are not part of the RTT block and thus should not be
defined in the reg property of the rtt node.
Use syscon to provide a proper DT representation and reference the GPBR
syscon device in a new atmel,time-reg property which store both the
syscon device phandle and the register
Hi,
On 10 September 2014 19:20, Arnd wrote:
On Tuesday 09 September 2014 12:20:54 Catalin Marinas wrote:
We can assume that if a domain is not specified and there is a single
top level PCIe node, the domain defaults to 0. Are there any arm32
platforms that require multiple domains (and
On Thu, Sep 11, 2014 at 02:17:16PM +0200, Marc Dietrich wrote:
cc'ing: devicetree
Thanks, I forgot that!
-iic1 {
+i2c1 {
status = ok;
- pinctrl-0 = iic1_pins;
+ pinctrl-0 = i2c1_pins;
pinctrl-names = default;
+
+ eeprom@64 {
+ compatible =
Hi all,
I had a discussion with Heiko on IRC few days ago about adding
shutdown support in act8865 pmic for Rockchip SoCs. While browsing on
LXR in order to understand how other pmic handles this support I found
that most of the time there is a custom property of the following form
Hi Caesar,
Am Mittwoch, 10. September 2014, 10:49:05 schrieb Caesar Wang:
Hi Heiko,
在 2014年09月09日 19:37, Heiko Stübner 写道:
Am Mittwoch, 3. September 2014, 10:10:38 schrieb Caesar Wang:
Signed-off-by: Caesar Wang caesar.w...@rock-chips.com
---
arch/arm/boot/dts/rk3288.dtsi | 18
b) could be seen as a configuration thing since the functionality
backend could be changed at runtime even.
Come to think of it, not only the functionality, also the address can be
changed at runtime. This makes me think it should really not be in DT
after all.
People will probably find out
On Thursday 11 September 2014 14:11:05 Phil Edworthy wrote:
On 10 September 2014 19:20, Arnd wrote:
On Tuesday 09 September 2014 12:20:54 Catalin Marinas wrote:
We can assume that if a domain is not specified and there is a single
top level PCIe node, the domain defaults to 0. Are
Am Donnerstag, 11. September 2014, 16:12:58 schrieb Wolfram Sang:
On Thu, Sep 11, 2014 at 02:17:16PM +0200, Marc Dietrich wrote:
+ reg = 0x64;
we had some discussions in the past how to represent i2c master devices in
device tree. The outcome was to use to a special
Am Donnerstag, 11. September 2014, 16:40:04 schrieb Wolfram Sang:
b) could be seen as a configuration thing since the functionality
backend could be changed at runtime even.
Come to think of it, not only the functionality, also the address can be
changed at runtime. This makes me think it
Here is version 2.
Changes since v1:
- the review comments from Peter Meerwald and Hartmut Knaack are taken into
account
- the driver private sysfs attributes are dropped out.
- dt binding document is changed in the section of adc channel nodes - now the
adc channel number is represented
Document DT binding for Qualcomm SPMI PMIC voltage ADC
driver.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
.../devicetree/bindings/iio/adc/qcom,spmi-vadc.txt | 123
1 files changed, 123 insertions(+), 0
The voltage ADC is peripheral of Qualcomm SPMI PMIC chips. It has
15bits resolution and register space inside PMIC accessible across
SPMI bus.
The vadc driver registers itself through IIO interface.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
Signed-off-by: Ivan T. Ivanov
Hi,
Any updates on this patch series?
On Monday 25 August 2014 11:31 PM, Shreyas B. Prabhu wrote:
Fast sleep is an idle state, where the core and the L1 and L2
caches are brought down to a threshold voltage. This also means that
the communication between L2 and L3 caches have to be fenced.
On Wednesday 10 September 2014 07:33 AM, Jamal Hadi Salim wrote:
On 09/09/14 11:19, Santosh Shilimkar wrote:
All the documentation is open including packet accelerator offload
in ti.com.
Very nice.
Would you do me a kindness and point to the switch interface
documentation (and other ones
Peter,
On Thu, Sep 11, 2014 at 09:07:10AM +0800, Peter Chen wrote:
On Wed, Sep 03, 2014 at 09:48:26AM +0200, Antoine Tenart wrote:
+
+static int ci_hdrc_usb2_dt_probe(struct device *dev,
+struct ci_hdrc_platform_data *ci_pdata)
+{
+ ci_pdata-phy =
Dave,
On Monday 08 September 2014 10:41 AM, Santosh Shilimkar wrote:
Hi Dave,
On 8/22/14 3:45 PM, Santosh Shilimkar wrote:
Hi David,
On Thursday 21 August 2014 07:36 PM, David Miller wrote:
From: Santosh Shilimkar santosh.shilim...@ti.com
Date: Fri, 15 Aug 2014 11:12:39 -0400
Update
Hi Doug,
On 09/11/2014 11:52 AM, Doug Anderson wrote:
Some 32-bit (ARMv7) systems are architected like this:
* The firmware doesn't know and doesn't care about hypervisor mode and
we don't want to add the complexity of hypervisor there.
* The firmware isn't involved in SMP bringup or
Christopher,
On Thu, Sep 11, 2014 at 8:58 AM, Christopher Covington
c...@codeaurora.org wrote:
Hi Doug,
On 09/11/2014 11:52 AM, Doug Anderson wrote:
Some 32-bit (ARMv7) systems are architected like this:
* The firmware doesn't know and doesn't care about hypervisor mode and
we don't want
From: Mathieu Poirier mathieu.poir...@linaro.org
Coresight IP blocks allow for the support of HW assisted tracing
on ARM SoCs. Bindings for the currently available blocks are
presented herein.
Signed-off-by: Pratik Patel prat...@codeaurora.org
Signed-off-by: Panchaxari Prasannamurthy
On 09/11/2014 10:58 AM, Christopher Covington wrote:
On 09/11/2014 11:52 AM, Doug Anderson wrote:
diff --git a/drivers/clocksource/arm_arch_timer.c
b/drivers/clocksource/arm_arch_timer.c
index 5163ec1..8ca07a9 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++
On Thu, Sep 11, 2014 at 05:04:11PM +0100, Doug Anderson wrote:
On Thu, Sep 11, 2014 at 8:58 AM, Christopher Covington
c...@codeaurora.org wrote:
On 09/11/2014 11:52 AM, Doug Anderson wrote:
diff --git a/drivers/clocksource/arm_arch_timer.c
b/drivers/clocksource/arm_arch_timer.c
index
Some 32-bit (ARMv7) systems are architected like this:
* The firmware doesn't know and doesn't care about hypervisor mode and
we don't want to add the complexity of hypervisor there.
* The firmware isn't involved in SMP bringup or resume.
* The ARCH timer come up with an uninitialized offset
On Thursday 11 September 2014 11:40 AM, Murali Karicheri wrote:
Fix incorrect clock names for usb1, pcie1 and domain register
offset for pcie1 clock nodes on K2E EVM
Signed-off-by: Murali Karicheri m-kariche...@ti.com
---
Thanks Murali. I will queue this up.
On 09/11/2014 12:04 PM, Doug Anderson wrote:
Christopher,
On Thu, Sep 11, 2014 at 8:58 AM, Christopher Covington
c...@codeaurora.org wrote:
Hi Doug,
On 09/11/2014 11:52 AM, Doug Anderson wrote:
Some 32-bit (ARMv7) systems are architected like this:
* The firmware doesn't know and
On September 11, 2014 10:13:24 AM GMT+01:00, Linus Walleij
linus.wall...@linaro.org wrote:
On Mon, Aug 25, 2014 at 6:19 PM, Jonathan Cameron ji...@kernel.org
wrote:
On 23/08/14 18:31, Linus Walleij wrote:
This adds support for the LIS3LV02 accelerometer found in the
ST Microelectronics
Will,
On Thu, Sep 11, 2014 at 9:47 AM, Will Deacon will.dea...@arm.com wrote:
On Thu, Sep 11, 2014 at 05:16:44PM +0100, Doug Anderson wrote:
Some 32-bit (ARMv7) systems are architected like this:
* The firmware doesn't know and doesn't care about hypervisor mode and
we don't want to add
Some 32-bit (ARMv7) systems are architected like this:
* The firmware doesn't know and doesn't care about hypervisor mode and
we don't want to add the complexity of hypervisor there.
* The firmware isn't involved in SMP bringup or resume.
* The ARCH timer come up with an uninitialized offset
On Tue, 9 Sep 2014, Weike Chen wrote:
struct dwapb_gpio;
+struct dwapb_context;
struct dwapb_gpio_port {
struct bgpio_chip bgc;
boolis_registered;
struct dwapb_gpio *gpio;
+ struct dwapb_context*ctx;
Alvin,
Will this build
This is the generic phy driver for the picoPHY ports used by the
USB2 and USB3 Host controllers when controlling usb2/1.1 devices. It
is found on STiH407 SoC family from STMicroelectronics.
Signed-off-by: Giuseppe Cavallaro peppe.cavall...@st.com
Signed-off-by: Peter Griffin
This series adds support for the picoPHY usb phy which is used by the usb2
and usb3 host controllers when controlling usb2/1.1 devices. It is found on
stih407 family SoC's from the consumer electronics devision of
STMicroelectronics.
Changes since v2:
- Remove .data and hardcode phy ops in
This patch enables the picoPHY usb phy which is used by
the usb2 and usb3 host controllers when controlling usb2/1.1
devices. It is found in stih407 family SoC's from STMicroelectronics.
Signed-off-by: Peter Griffin peter.grif...@linaro.org
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file
On Thu, Sep 11, 2014 at 05:59:53PM +0100, Doug Anderson wrote:
On Thu, Sep 11, 2014 at 9:47 AM, Will Deacon will.dea...@arm.com wrote:
I'd say `Only supported for ARM' to better match what we've done. Probably
also worth mentioning that this relies on the hypervisor/firmware having set
Hi,
On Thu, Sep 11, 2014 at 10:00 AM, Marc Zyngier marc.zyng...@arm.com wrote:
On 11/09/14 17:47, Will Deacon wrote:
On Thu, Sep 11, 2014 at 05:16:44PM +0100, Doug Anderson wrote:
Some 32-bit (ARMv7) systems are architected like this:
* The firmware doesn't know and doesn't care about
* Suman Anna s-a...@ti.com [140909 09:16]:
Hi Tony,
On 09/08/2014 09:52 PM, Tony Lindgren wrote:
* Tony Lindgren t...@atomide.com [140908 16:21]:
* Suman Anna s-a...@ti.com [140729 17:37]:
Hi,
This is an updated version of the OMAP Mailbox framework adoption
DT support series,
Will,
On Thu, Sep 11, 2014 at 10:07 AM, Will Deacon will.dea...@arm.com wrote:
On Thu, Sep 11, 2014 at 05:59:53PM +0100, Doug Anderson wrote:
On Thu, Sep 11, 2014 at 9:47 AM, Will Deacon will.dea...@arm.com wrote:
I'd say `Only supported for ARM' to better match what we've done. Probably
On Wed, Sep 10, 2014 at 03:03:33PM +0300, Dmitry Lifshitz wrote:
Hi,
On 09/08/2014 04:24 PM, Felipe Balbi wrote:
Hi,
On Mon, Sep 08, 2014 at 02:34:33PM +0300, Dmitry Lifshitz wrote:
Hi Felipe, Roger
On 04/16/2014 07:16 PM, Felipe Balbi wrote:
On Fri, Oct 11, 2013 at 05:46:12PM +0300,
On Thu, Sep 11, 2014 at 05:16:44PM +0100, Doug Anderson wrote:
Some 32-bit (ARMv7) systems are architected like this:
* The firmware doesn't know and doesn't care about hypervisor mode and
we don't want to add the complexity of hypervisor there.
* The firmware isn't involved in SMP
On 11/09/14 18:11, Doug Anderson wrote:
Hi,
On Thu, Sep 11, 2014 at 10:00 AM, Marc Zyngier marc.zyng...@arm.com wrote:
On 11/09/14 17:47, Will Deacon wrote:
On Thu, Sep 11, 2014 at 05:16:44PM +0100, Doug Anderson wrote:
Some 32-bit (ARMv7) systems are architected like this:
* The firmware
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