Hello Doug,
On 10 June 2014 23:56, Doug Anderson diand...@chromium.org wrote:
Naveen,
Not a full review, but a few quick things I happened to notice:
On Tue, Jun 10, 2014 at 3:08 AM, Naveen Krishna Chatradhi
ch.nav...@samsung.com wrote:
@@ -94,7 +93,6 @@ Example:
Hello Tomasz,
On 11 June 2014 01:19, Tomasz Figa tomasz.f...@gmail.com wrote:
Hi Naveen,
On 10.06.2014 12:08, Naveen Krishna Chatradhi wrote:
Currently, spi-s3c64xx.c needs cs-gpio chip select GPIO to be
defined under controller-data node under each slave node.
[snip]
@@ -85,6 +83,7 @@
On 10/06/14 22:32, Rob Herring wrote:
On Tue, Jun 10, 2014 at 1:09 PM, Doug Anderson diand...@chromium.org wrote:
Naveen / Sylwester,
On Tue, Jun 10, 2014 at 4:00 AM, Naveen Krishna Ch
naveenkrishna...@gmail.com wrote:
Can we support both cs-gpio and cs-gpios for backward compatibility ?
Currently, spi-s3c64xx.c needs cs-gpio chip select GPIO to be
defined under controller-data node under each slave node.
spi_x {
cs-gpios ;
...
slave_node {
controller-data {
cs-gpio = ;
...
};
On 10/06/14 12:08, Naveen Krishna Chatradhi wrote:
Currently, spi-s3c64xx.c needs cs-gpio chip select GPIO to be
defined under controller-data node under each slave node.
spi_x {
cs-gpios ;
...
slave_node {
controller-data {
cs-gpio
Hello Sylwester,
Thanks for the review.
On 10 June 2014 16:09, Sylwester Nawrocki s.nawro...@samsung.com wrote:
On 10/06/14 12:08, Naveen Krishna Chatradhi wrote:
Currently, spi-s3c64xx.c needs cs-gpio chip select GPIO to be
defined under controller-data node under each slave node.
spi_x {
Naveen / Sylwester,
On Tue, Jun 10, 2014 at 4:00 AM, Naveen Krishna Ch
naveenkrishna...@gmail.com wrote:
Can we support both cs-gpio and cs-gpios for backward compatibility ?
After your change all DTBs using the original pattern will not work with
new kernels any more. At least I would expect
Naveen,
Not a full review, but a few quick things I happened to notice:
On Tue, Jun 10, 2014 at 3:08 AM, Naveen Krishna Chatradhi
ch.nav...@samsung.com wrote:
@@ -94,7 +93,6 @@ Example:
spi-max-frequency = 1;
controller-data {
-
On 10.06.2014 20:26, Doug Anderson wrote:
Naveen,
Not a full review, but a few quick things I happened to notice:
On Tue, Jun 10, 2014 at 3:08 AM, Naveen Krishna Chatradhi
ch.nav...@samsung.com wrote:
@@ -94,7 +93,6 @@ Example:
spi-max-frequency = 1;
On 10.06.2014 20:09, Doug Anderson wrote:
Naveen / Sylwester,
On Tue, Jun 10, 2014 at 4:00 AM, Naveen Krishna Ch
naveenkrishna...@gmail.com wrote:
Can we support both cs-gpio and cs-gpios for backward compatibility ?
After your change all DTBs using the original pattern will not work with
Hi Naveen,
On 10.06.2014 12:08, Naveen Krishna Chatradhi wrote:
Currently, spi-s3c64xx.c needs cs-gpio chip select GPIO to be
defined under controller-data node under each slave node.
[snip]
@@ -85,6 +83,7 @@ Example:
#size-cells = 0;
pinctrl-names = default;
Tomasz,
On Tue, Jun 10, 2014 at 12:49 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
This is wrong. The cs-gpios property is supposed to be an array,
indexed by chip select number of SPI devices (indicated by their reg
properties).
Moreover, is there a need to parse this manually in this
On 10.06.2014 21:58, Doug Anderson wrote:
Tomasz,
On Tue, Jun 10, 2014 at 12:49 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
This is wrong. The cs-gpios property is supposed to be an array,
indexed by chip select number of SPI devices (indicated by their reg
properties).
Moreover, is
Tomasz,
On Tue, Jun 10, 2014 at 12:59 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
On 10.06.2014 21:58, Doug Anderson wrote:
Tomasz,
On Tue, Jun 10, 2014 at 12:49 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
This is wrong. The cs-gpios property is supposed to be an array,
indexed by chip
On Tue, Jun 10, 2014 at 1:09 PM, Doug Anderson diand...@chromium.org wrote:
Naveen / Sylwester,
On Tue, Jun 10, 2014 at 4:00 AM, Naveen Krishna Ch
naveenkrishna...@gmail.com wrote:
Can we support both cs-gpio and cs-gpios for backward compatibility ?
After your change all DTBs using the
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