Drivers shouldn't use NO_IRQ. This driver is used
by Microblaze and PPC. PPC defines NO_IRQ as 0
and Microblaze has removed it.
Signed-off-by: Michal Simek mon...@monstr.eu
CC: Alan Stern st...@rowland.harvard.edu
CC: Greg Kroah-Hartman gre...@suse.de
CC: Grant Likely grant.lik...@secretlab.ca
-Original Message-
From: Stephen Warren [mailto:swar...@nvidia.com]
Sent: Thursday, January 12, 2012 4:18 AM
To: Dong Aisheng-B29396; Dong Aisheng
Cc: linux-ker...@vger.kernel.org; linus.wall...@stericsson.com;
s.ha...@pengutronix.de; rob.herr...@calxeda.com; linux-arm-
On Wed, Jan 11, 2012 at 09:46:58PM -0700, Grant Likely wrote:
On Tue, Jan 10, 2012 at 2:33 PM, Jamie Iles ja...@jamieiles.com wrote:
On Mon, Dec 12, 2011 at 03:02:04PM -0700, Grant Likely wrote:
+- clock-output-names : From common clock binding
+
+Example:
+ clock {
+
On Thu, Jan 12, 2012 at 02:17:14PM +1100, David Gibson wrote:
On Wed, Jan 11, 2012 at 01:38:12PM +, Jamie Iles wrote:
On Wed, Jan 11, 2012 at 11:19:41PM +1100, David Gibson wrote:
On Mon, Jan 09, 2012 at 08:07:30AM -0600, Jon Loeliger wrote:
Jon, I was hoping I'd get some comment on
Stephen Warren wrote:
Mitch Bradley wrote at Wednesday, January 11, 2012 4:16 PM:
Perhaps I'm missing something, but it appears to me that the model is to
set the correct GPIO state before each use, instead of a
save-set-use-restore model.
That's true, but the select action happens
Stephen Warren wrote:
Timur Tabi wrote at Wednesday, January 11, 2012 1:33 PM:
Stephen Warren wrote:
Well, the EDID needs to be read on every hotplug event, so it's certainly
not a one-time thing.
What is the hotplug event that triggers an EDID read?
For monitors attached to
On Wed, Jan 11, 2012 at 08:29:58AM -0600, Jon Loeliger wrote:
On Tue, Jan 10, 2012 at 10:12:48AM -0700, Stephen Warren wrote:
This will allow callers to rebuild .dtb files when any of the /include/d
.dtsi files are modified, not just the top-level .dts file.
Signed-off-by:
I find it ironic that the very first device tree implementation, dating
back to 1989, was built around a Turing complete language.
...and that my uncle wrote one of the very first
books about that language. :-)
jdl
___
devicetree-discuss mailing
I'm not saying he didn't do the worl, nor am I saying he
didn't post such a past. I'm saying *I* don't have it!
Yeeesh.
s/worl/work/
s/past/patch/
jdl
___
devicetree-discuss mailing list
devicetree-discuss@lists.ozlabs.org
Jamie,
On 12/19/2011 04:22 PM, Jamie Iles wrote:
Commit 6d274309d (irq: support domains with non-zero hwirq base)
introduced a WARN_ON() for an invalid hwirq in irq_domain_to_irq() but
doesn't include linux/bug.h resulting in:
include/linux/irqdomain.h: In function 'irq_domain_to_irq':
On Thu, Jan 12, 2012 at 08:35:12AM -0600, Rob Herring wrote:
Jamie,
On 12/19/2011 04:22 PM, Jamie Iles wrote:
Commit 6d274309d (irq: support domains with non-zero hwirq base)
introduced a WARN_ON() for an invalid hwirq in irq_domain_to_irq() but
doesn't include linux/bug.h resulting in:
Adding devicetree-discuss since we are talking bindings...
On 01/12/2012 10:00 AM, Marc Zyngier wrote:
On 12/01/12 15:42, Rob Herring wrote:
On 01/12/2012 08:36 AM, Marc Zyngier wrote:
Hi Rob,
On 11/01/12 21:05, Rob Herring wrote:
On 01/11/2012 07:08 AM, Marc Zyngier wrote:
Add bindings to
Mitch Bradley wrote at Wednesday, January 11, 2012 5:39 PM:
On 1/11/2012 2:15 PM, Stephen Warren wrote:
Mitch Bradley wrote at Wednesday, January 11, 2012 4:16 PM:
...
In any case, if there is a good way to instantiate the GPIO mux device
from the device tree, it certainly provides a
Jamie Lokier wrote at Thursday, January 12, 2012 5:24 AM:
...
For all the above reasons I think the DDC/EDID support in the kernel
should be moving gently towards a (very small) DDC/EDID mini-subsystem
shared by video drivers. I.e. it should be exposed as a well-known
I2C bus name, and if
This will allow callers to rebuild .dtb files when any of the /include/d
.dtsi files are modified, not just the top-level .dts file.
Signed-off-by: Stephen Warren swar...@nvidia.com
Acked-by: David Gibson da...@gibson.dropbear.id.au
---
v2: Replaced fputs/fputc with fprintf.
v2 repost: Add
On 12/01/12 16:27, Rob Herring wrote:
Adding devicetree-discuss since we are talking bindings...
On 01/12/2012 10:00 AM, Marc Zyngier wrote:
On 12/01/12 15:42, Rob Herring wrote:
On 01/12/2012 08:36 AM, Marc Zyngier wrote:
Hi Rob,
On 11/01/12 21:05, Rob Herring wrote:
On 01/11/2012 07:08
On Fri, Nov 18, 2011 at 11:10 AM, Rob Herring rob.herr...@calxeda.com wrote:
On 11/18/2011 09:09 AM, Wojciech Baranowski wrote:
While looking up linux name for platform device, check the address only if it
has been supplied in lookup table.
And the reason you want to do this is?
Name lookup
Since the application of the commit below the PATA OF platform driver
may now be built on x86 systems:
ata: Make pata_of_platform.c compile again and work on non-PPC platforms
This leads to the following build failure on 32bit x86 builds:
.../drivers/ata/pata_of_platform.c: In function
On 11/4/2011 6:40 AM, Jamie Iles wrote:
Now that there is a generic IRQ handler for multiple VIC devices use it
for spear to help building multi platform kernels.
Cc: Viresh Kumar viresh.ku...@st.com
Cc: Rajeev Kumar rajeev-dlh.ku...@st.com
Signed-off-by: Jamie Iles ja...@jamieiles.com
---
On Wed, 2011-11-16 at 17:30 +, Pawel Moll wrote:
On Wed, 2011-11-16 at 17:28 +, Dave Martin wrote:
Is there anything else blocking the building of legacy and RS1 memory
maps into a single kernel?
(I'm still hazy on how all the remapping stuff works, myself.)
This works
This patchset adds support for the tegra30 SoC and the cardhu development
board.
Pathset is on top of Will Deacon's ARM reset work, my patch to convert tegra20
to GIC devicetree binding and my patch to make clk_get not fatal.
Most important changes in v5:
* use devicetree binding for GIC
*
Add new fields to struct tegra_pingroup_desc to support new hardware features
introduced in the tegra30 SoC. The pinmux driver won't use those fields yet,
but the tegra30 pinmux tables will already provide the necessary data.
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---
This patch adds the initial device tree for tegra30
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---
Documentation/devicetree/bindings/arm/tegra.txt | 18 +++
arch/arm/boot/dts/tegra30.dtsi | 128 +++
2 files changed, 146 insertions(+), 0
Rework the tegra20 clock code to support multiple tegra variants :
* remove tegra2_periph_reset_assert/tegra2_periph_reset_deassert. This
functionality should be in clock.c.
* compile tegra_sdmmc_tap_delay only on tegra20 as this feature will not
be available in future variants.
* don't
This patch modifies the pinmux code to be useable for multiple tegra variants.
Some tegra20 specific constants will be replaced by variables which will be
initialized to the appropriate value at runtime.
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---
This patch splits the early init code in a common and a tegra20 specific part.
L2 cache initialization is generalized and discovers the cache associativity
at runtime. Also use arm_pm_restart instead of arm_arch_reset and reset the
the system using the PMC reset feature rather then the CAR system
Add support for tegra30 SoC. This includes a device tree compatible type for
this SoC (nvidia,tegra30) and adds L2 cache initialization for this new SoC.
The clock framework is still missing, which prevents most drivers from working.
The basic IRQs are the same, so remove the dependency on
Define the pinmuxing and pindrive tables for tegra30. The pinmux table defines
the available functions for each pinmux group. The pindrive table defines the
default pullup or pulldowns for each group.
Derived from code by Scott Williams (scwilli...@nvidia.com)
Signed-off-by: Peter De Schrijver
Rename pinmux-t2.h and pinmux-t2-tables.c to the new tegra naming. This file
will be reworked somewhat in the next patch to support multiple tegra SoC
types.
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---
arch/arm/mach-tegra/Makefile |2 +-
On Thu, Nov 17, 2011 at 05:19:14PM +0100, Peter De Schrijver wrote:
This patchset adds support for the tegra30 SoC and the cardhu development
board.
Pathset is on top of Will Deacon's ARM reset work, my patch to convert tegra20
to GIC devicetree binding and my patch to make clk_get not
Stephen beat me to it. Look at how our other drivers do HW manipulation w/o
bitfields and mimic them if you get stuck (SPI, MMC, etc.).
My take is that we'd be better off pushing a Harmony dts file first, since that
seems to be the most used/available Tegra2 board out there AFAIK. And getting
On Fri, Nov 18, 2011 at 08:06:49PM +0100, Olof Johansson wrote:
Hi,
A nit and two comments below.
On Thu, Nov 17, 2011 at 06:19:17PM +0200, Peter De Schrijver wrote:
Rework the tegra20 clock code to support multiple tegra variants :
* remove
On Fri, Nov 18, 2011 at 10:41:16PM +0100, Olof Johansson wrote:
On Thu, Nov 17, 2011 at 06:19:20PM +0200, Peter De Schrijver wrote:
This patch modifies the pinmux code to be useable for multiple tegra
variants.
Some tegra20 specific constants will be replaced by variables which will be
On Tue, Nov 22, 2011 at 08:01:46PM +0100, Olof Johansson wrote:
On Mon, Nov 21, 2011 at 04:29:19PM +0200, Peter De Schrijver wrote:
On Fri, Nov 18, 2011 at 10:41:16PM +0100, Olof Johansson wrote:
On Thu, Nov 17, 2011 at 06:19:20PM +0200, Peter De Schrijver wrote:
This patch modifies the
But the WM8903 still has the same interrupt-parent as everything else,
since it's inherited from /interrupt-parent and doesn't define its own.
Perhaps this is a mistake?
Yes. I think this is a mistake. If we want the device tree to reflect the
hardware, I think the WM8903 node
Op 22 nov. 2011, om 18:54 heeft Tony Lindgren het volgende geschreven:
* Linus Walleij linus.wall...@linaro.org [22 03:30]:
On Tue, Nov 22, 2011 at 12:09 PM, Thomas Abraham
thomas.abra...@linaro.org wrote:
On 17 November 2011 19:27, Linus Walleij linus.wall...@linaro.org wrote:
Maybe
Hello,
On Tuesday, November 01, 2011 2:01 AM Thomas Abraham wrote:
ioremap() request for statically remapped regions are intercepted and the
statically assigned virtual address is returned. For requests for which
there are no statically remapped regions, the requests are let through.
Cc:
On 17:47 Wed 30 Nov , Stephen Warren wrote:
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/wm8903.txt
@@ -0,0 +1,44 @@
+WM89033 audio CODEC
Just a nitpick. s/WM89033/WM8903/
--
Best regards,
Dmitry MAD Artamonow
___
On 11/28/2011 01:41 PM, Stephen Warren wrote:
On 11/23/2011 08:54 PM, Simon Glass wrote:
Add a function to lookup a property which is a phandle in a node, and
another to read a fixed-length integer array from an fdt property.
Also add a function to read boolean properties.
Signed-off-by: Simon
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
.../bindings/sound/soc/omap/omap-dmic.txt | 13 +
sound/soc/omap/omap-dmic.c |8
2 files changed, 21 insertions(+), 0 deletions(-)
create mode 100644
If dtb is provided of will create the needed devices dynamically so there
is no need to create the platform device for McPDM here.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
arch/arm/mach-omap2/devices.c |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
.../bindings/sound/soc/omap/omap-mcpdm.txt | 13 +
sound/soc/omap/omap-mcpdm.c|8
2 files changed, 21 insertions(+), 0 deletions(-)
create mode 100644
If dtb is provided of will create the needed devices dynamically so there
is no need to create the platform device for DMIC here.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
arch/arm/mach-omap2/devices.c |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git
Hello,
The following series adds device tree support for omap-dmic, omap-mcpdm ASoC
DAI drivers.
The OMAP4 platform patches have dependency on the DMIC driver series:
http://www.mail-archive.com/linux-omap@vger.kernel.org/msg59161.html
Regards,
Peter
---
Peter Ujfalusi (5):
ASoC: omap-dmic:
On 12/01/2011 11:58 PM, Simon Glass wrote:
Hi Jerry,
On Thu, Dec 1, 2011 at 7:33 PM, Jerry Van Barengvb.ub...@gmail.com wrote:
[snip]
FDT helper functions have been accumulating in common/fdt_support.c rather
than a separate file. Simon, what is the history of lib/fdtdec.c? Is it a
On Fri, Dec 2, 2011 at 11:26 AM, Dave Martin dave.mar...@linaro.org wrote:
This is now broken on ARM where, for good or bad, NO_IRQ currently is
used and is -1.
How do we resolve it? If we are ready to eliminate NO_IRQ from
drivers/of/irq.c (or indeed, all code that uses it) and just use 0
On Fri, Dec 02, 2011 at 07:19:17PM +, Dave Martin wrote:
[...]
Drivers should not use NO_IRQ; moreover, some architectures don't
have it nowadays. '0' is the 'no irq' case.
Signed-off-by: Anton Vorontsov cbouatmai...@gmail.com
Acked-by: Alan Cox a...@linux.intel.com
On Sat, Dec 03, 2011 at 02:34:02AM +0400, Anton Vorontsov wrote:
On Fri, Dec 02, 2011 at 07:19:17PM +, Dave Martin wrote:
[...]
Drivers should not use NO_IRQ; moreover, some architectures don't
have it nowadays. '0' is the 'no irq' case.
Signed-off-by: Anton Vorontsov
On Fri, Dec 2, 2011 at 2:34 PM, Anton Vorontsov
anton.voront...@linaro.org wrote:
One option is to test this patch on a board that is now broken:
http://lkml.org/lkml/2011/11/10/290
That seems broken.
Spot the trouble:
+ ret = irq_create_of_mapping(oirq.controller, oirq.specifier,
+
On Sat, Dec 03, 2011 at 02:40:18AM +0400, Anton Vorontsov wrote:
On Sat, Dec 03, 2011 at 02:34:02AM +0400, Anton Vorontsov wrote:
On Fri, Dec 02, 2011 at 07:19:17PM +, Dave Martin wrote:
[...]
Drivers should not use NO_IRQ; moreover, some architectures don't
have it nowadays.
The advantage of kcalloc is, that will prevent integer overflows which could
result from the multiplication of number of elements and size and it is also
a bit nicer to read.
The semantic patch that makes this change is available
in https://lkml.org/lkml/2011/11/25/107
Signed-off-by: Thomas
This driver implements a character device with major number 10 and minor
number 130. It is a software abstraction of the hardware watchdog
with two different APIs. While the driver periodically triggers the
hardware watchdog, the software can setup independent timeout periods.
REGULAR API
hi,
some comments inline
El Sun, Dec 04, 2011 at 10:45:21AM +0100 Heiko Schocher ha dit:
This driver implements the Linux kernel half of the boot count feature -
the boot counter can only be reset after it is clear that the
application has been started and is running correctly, which usually
On 04/12/11 20:45, Heiko Schocher wrote:
This driver implements the Linux kernel half of the boot count feature -
the boot counter can only be reset after it is clear that the
application has been started and is running correctly, which usually
can only be determined by the application code
On 12/03/2011 01:22 PM, Mark Brown wrote:
On Fri, Dec 02, 2011 at 11:52:56AM +0200, Peter Ujfalusi wrote:
@@ -0,0 +1,13 @@
+* Texas Instruments OMAP4 Digital Microphone Module
+
+Required properties:
+ - compatible : ti,omap4-dmic
+ - ti,hwmods : List of hwmod names associated with
On Mon, 2011-12-05 at 18:45 +, Alan Cox wrote:
But as you illustrated, there is a large number of drivers that already
assume no IRQ is 0, even if they don't use any IRQ #0 themselves.
That is a much bigger problem to fix.
And a much larger number assuming the reverse is true
The register set used in the bq20z75 is really just the set
defined by the SBS spec. With that in mind, this patch is intended
to generalize the driver to in name support any SBS compliant
gas gauge.
-Rename source files to sbs-battery.*
-Rename internals with sbs
Change-Id:
This driver for the bq20z75 implemented the register spec defined
by the SBS standard. As this is not unique to this the TI part this
was originally written for, we can generalize this driver to
show its support for any SBS compliant battery.
Signed-off-by: Rhyland Klein rkl...@nvidia.com
---
This driver for the bq20z75 implemented the register spec defined
by the SBS standard. As this is not unique to this the TI part this
was originally written for, we can generalize this driver to
show its support for any SBS compliant battery.
Signed-off-by: Rhyland Klein rkl...@nvidia.com
---
On Mon, Dec 05, 2011 at 03:58:03PM -0800, Rhyland Klein wrote:
+config BATTERY_SBS
+tristate SBS Compliant gas gauge
This could potentially be confusing with the ACPI SBS code - I guess the
long term ideal would be to merge them?
--
Matthew Garrett | mj...@srcf.ucam.org
On Tue, Dec 6, 2011 at 2:46 AM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
But.. let's make one thing clear: Alan Cox and Linus have been going on
about how IRQ0 should not be used. Let's be crystal clear: even x86
uses IRQ0.
Not for any device driver, though.
It's used entirely
On Tue, Dec 6, 2011 at 1:22 PM, Rob Herring robherri...@gmail.com wrote:
This warning code is really ugly. Can we just drop it? In my searching
of in kernel dts files, there's only 1 instance I have found (Versatile
AB watchdog) that would hit this.
I do agree. Especially since we never got
PPC32/64 defines NO_IRQ to zero, so no problems expected.
ARM defines NO_IRQ to -1, but OF code relies on IRQ domains support,
which returns correct ('0') value in 'no irq' case. So everything
should be fine.
Other arches might break if some of their OF drivers rely on NO_IRQ
being not 0. If so,
On 12/05/2011 05:46 PM, Mark Brown wrote:
And what I'm saying is that my main concern is that you're publishing
documenting a binding which isn't intended to be the the final binding
and which there's no intention that anyone should use directly anyway.
I felt it is the right thing to document
Hi Heiko,
On Sun, Dec 04, 2011 at 15:11:19, Heiko Schocher wrote:
Please provide a patch description. Nice to see device tree
support being added for DaVinci devices.
Signed-off-by: Heiko Schocher h...@denx.de
Cc: davinci-linux-open-sou...@linux.davincidsp.com
Cc:
On Wed, Dec 7, 2011 at 6:41 AM, Rob Herring robherri...@gmail.com wrote:
This patch changes the Microblaze NO_IRQ setting from -1 to 0 to bring
it in line with most of the rest of the kernel. It also prepares for
Microblaze eventually supporting multiple interrupt controllers by
breaking the
On Thu, Dec 08, 2011 at 13:17:05, Heiko Schocher wrote:
diff --git a/Documentation/devicetree/bindings/arm/davinci/aemif.txt
b/Documentation/devicetree/bindings/arm/davinci/aemif.txt
new file mode 100644
index 000..c9ed551
--- /dev/null
+++
Hi Heiko,
On Thu, Dec 08, 2011 at 14:36:47, Heiko Schocher wrote:
diff --git a/arch/arm/mach-davinci/aemif.c
b/arch/arm/mach-davinci/aemif.c
index 1ce70a9..12c559f 100644
--- a/arch/arm/mach-davinci/aemif.c
+++ b/arch/arm/mach-davinci/aemif.c
@@ -13,12 +13,14 @@
#include
This patchset adds support for the tegra30 SoC and the cardhu development
board.
Patchset is on top of linux-next and
http://www.spinics.net/lists/linux-tegra/msg03016.html.
Most important changes in v6:
* Align with latest version of the ARM restart implementation
* Address comments on
This patchset adds support for the tegra30 SoC and the cardhu development
board.
Patchset is on top of linux-next and
http://www.spinics.net/lists/linux-tegra/msg03016.html.
Most important changes in v6:
* Align with latest version of the ARM restart implementation
* Address comments on
This patch adds the initial device tree for tegra30
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---
Documentation/devicetree/bindings/arm/tegra.txt | 14 +++
arch/arm/boot/dts/tegra30.dtsi | 127 +++
2 files changed, 141 insertions(+), 0
* add a dependency to ARCH_TEGRA_2x_SOC in Kconfig to all tegra20 based boards
and TEGRA_PCI
* make powergating dependent on ARCH_TEGRA_2x_SOC
* remove dependency on ARCH_TEGRA_2x_SOC for clock.c
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---
arch/arm/mach-tegra/Kconfig |8
Rework the tegra20 clock code to support multiple tegra variants :
* remove tegra2_periph_reset_assert/tegra2_periph_reset_deassert. This
functionality should be in clock.c.
* compile tegra_sdmmc_tap_delay only on tegra20 as this feature will not
be available in future variants.
* don't
This patch splits the early init code in a common and a tegra20 specific part.
L2 cache initialization is generalized and discovers the cache associativity
at runtime. Also use arm_pm_restart instead of arm_arch_reset and reset the
the system using the PMC reset feature rather then the CAR system
Rename pinmux-t2.h and pinmux-t2-tables.c to the new tegra naming. This file
will be reworked somewhat in the next patch to support multiple tegra SoC
types.
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---
arch/arm/mach-tegra/Makefile |2 +-
Add new fields to struct tegra_pingroup_desc to support new hardware features
introduced in the tegra30 SoC. The pinmux driver won't use those fields yet,
but the tegra30 pinmux tables will already provide the necessary data.
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---
Define the pinmuxing and pindrive tables for tegra30. The pinmux table defines
the available functions for each pinmux group. The pindrive table defines the
default pullup or pulldowns for each group.
Derived from code by Scott Williams (scwilli...@nvidia.com)
Signed-off-by: Peter De Schrijver
Add support for tegra30 SoC. This includes a device tree compatible type for
this SoC (nvidia,tegra30) and adds L2 cache initialization for this new SoC.
The clock framework is still missing, which prevents most drivers from working.
The basic IRQs are the same, so remove the dependency on
Add support for the tegra30 based cardhu development board. Cardhu is a tablet
formfactor reference design for tegra30. The patch provides a device tree for
the board, updates Makefile.boot to build the dtb, includes the platform in
Kconfig and updates board-dt.c.
Signed-off-by: Peter De
On Thu, Dec 8, 2011 at 4:43 AM, Peter De Schrijver
pdeschrij...@nvidia.comwrote:
Rework the tegra20 clock code to support multiple tegra variants :
* remove tegra2_periph_reset_assert/tegra2_periph_reset_deassert. This
functionality should be in clock.c.
* compile tegra_sdmmc_tap_delay
On Thu, Dec 8, 2011 at 9:57 AM, Stephen Warren swar...@nvidia.com wrote:
Peter De Schrijver wrote at Thursday, December 08, 2011 5:44 AM:
This patch splits the early init code in a common and a tegra20 specific
part.
L2 cache initialization is generalized and discovers the cache associativity
On Thu, Dec 08, 2011 at 07:25:53PM +0100, Colin Cross wrote:
On Thu, Dec 8, 2011 at 4:43 AM, Peter De Schrijver
pdeschrij...@nvidia.commailto:pdeschrij...@nvidia.com wrote:
Rework the tegra20 clock code to support multiple tegra variants :
* remove
Use the data field of of_device_id to hold the type for
s3c_cpu_type.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
drivers/rtc/rtc-s3c.c | 27 +--
1 files changed, 21 insertions(+), 6 deletions(-)
diff --git a/drivers/rtc/rtc-s3c.c b/drivers/rtc/rtc-s3c.c
index
choice
prompt Low-level debug console UART
default TEGRA_DEBUG_UART_NONE
diff --git a/arch/arm/mach-tegra/Makefile.boot
b/arch/arm/mach-tegra/Makefile.boot
index cf51a00..7c1110f 100644
--- a/arch/arm/mach-tegra/Makefile.boot
+++
On Fri, Dec 9, 2011 at 1:13 AM, Peter De Schrijver
pdeschrij...@nvidia.com wrote:
On Thu, Dec 08, 2011 at 07:25:53PM +0100, Colin Cross wrote:
On Thu, Dec 8, 2011 at 4:43 AM, Peter De Schrijver
pdeschrij...@nvidia.commailto:pdeschrij...@nvidia.com wrote:
Rework the tegra20 clock code to
On Fri, Dec 9, 2011 at 3:19 AM, Peter De Schrijver
pdeschrij...@nvidia.com wrote:
On Thu, Dec 08, 2011 at 07:29:43PM +0100, Colin Cross wrote:
On Thu, Dec 8, 2011 at 9:57 AM, Stephen Warren swar...@nvidia.com wrote:
Peter De Schrijver wrote at Thursday, December 08, 2011 5:44 AM:
This patch
Hi,
I am designing a bus driver for the System Power Management Interface,
which is also known as SPMI. Information about the bus can be found
through this website:
http://www.mipi.org/specifications/system-power-management-interface
In short, to make a transaction, you need two things: a 4
Hi Thomas,
thanks for your review and you are of course right with both your suggestions.
I will submit a v2 series shortly, implementing these suggestions.
Heiko
Am Sonntag, 11. Dezember 2011, 06:47:43 schrieb Thomas Abraham:
Hi Heiko,
On 9 December 2011 15:20, Heiko Stübner
On Fri, Dec 09, 2011 at 07:35:09PM +0100, Colin Cross wrote:
On Fri, Dec 9, 2011 at 3:19 AM, Peter De Schrijver
pdeschrij...@nvidia.com wrote:
On Thu, Dec 08, 2011 at 07:29:43PM +0100, Colin Cross wrote:
On Thu, Dec 8, 2011 at 9:57 AM, Stephen Warren swar...@nvidia.com wrote:
Peter De
On Fri, Dec 09, 2011 at 10:13:20AM +0100, Peter De Schrijver wrote:
On Thu, Dec 08, 2011 at 07:25:53PM +0100, Colin Cross wrote:
On Thu, Dec 8, 2011 at 4:43 AM, Peter De Schrijver
pdeschrij...@nvidia.commailto:pdeschrij...@nvidia.com wrote:
Rework the tegra20 clock code to support multiple
Hi,
On Tue, 2011-12-06 at 17:49 +0100, Benoit Cousson wrote:
devicetree will become the mandatory boot method for OMAP2+.
In order to avoid cluttering the OMAP code with #ifdef CONFIG_OF,
select USE_OF by default for every OMAP2+ systems.
Select as well the APPENDED_DTB and ATAG_DTB_COMPAT to
On Tue, 2012-01-03 at 16:19 +0200, Gilad Ben-Yossef wrote:
on_each_cpu() returns as its own return value the return value of
smp_call_function(). smp_call_function() in turn returns a hard
coded value of zero.
Some callers to on_each_cpu() waste cycles and bloat code space
by checking the
On 12/16/2011 02:52 AM, Jamie Iles wrote:
+static DEFINE_PER_CPU(unsigned long, l_p_j_ref);
+static unsigned long l_p_j_ref_freq;
+
+static struct clk *cpu_clk;
This assumes that all CPU's share the same clk and run at the same rate.
Is that a fair/safe assumption? I honestly don't
On Thu, 2011-12-15 at 14:02 +, Pawel Moll wrote:
This patch adds generic Versatile Express DT machine description,
Device Tree description for the motherboard and documentation for
the bindings.
[...]
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
[...]
Hi Arnd,
On Thu, Dec 08, 2011 at 21:18:08, Arnd Bergmann wrote:
On Thursday 08 December 2011, Nori, Sekhar wrote:
DaVinci AEMIF is an async memory interface peripheral implemented
in arch/arm/mach-davinci/aemif.c. It helps interface to NAND, NOR
and other asynchronous memories. Currently
Hello Arnd and Sekhar,
On Tue, Dec 13, 2011 at 1:34 PM, Nori, Sekhar nsek...@ti.com wrote:
[...]
On Thu, Dec 08, 2011 at 21:18:08, Arnd Bergmann wrote:
[...]
If you want it to provide endpoint devices that are handled by
distinct subsystems in Linux, I would make it an mfd multifunction
This patchset adds support for the tegra30 SoC and the cardhu development
board.
Patchset is on top of linux-next and
http://www.spinics.net/lists/linux-tegra/msg03016.html.
Most important changes in v7:
* split board-dt.c in board-dt-tegra20.c and board-dt-tegra30.c
* split early init
This patch adds the initial device tree for tegra30
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---
Documentation/devicetree/bindings/arm/tegra.txt | 14 +++
arch/arm/boot/dts/tegra30.dtsi | 127 +++
2 files changed, 141 insertions(+), 0
* add a dependency to ARCH_TEGRA_2x_SOC in Kconfig to all tegra20 based boards
and TEGRA_PCI
* make powergating dependent on ARCH_TEGRA_2x_SOC
* remove dependency on ARCH_TEGRA_2x_SOC for clock.c
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---
arch/arm/mach-tegra/Kconfig |8
Rework the tegra20 clock code to support multiple tegra variants :
* remove tegra2_periph_reset_assert/tegra2_periph_reset_deassert. This
functionality should be in clock.c.
* remove tegra_sdmmc_tap_delay and export tegra2_sdmmc_tap_delay
directly. This feature is handled inside the
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