* Stephen Warren wrote:
On 06/11/2012 09:05 AM, Thierry Reding wrote:
Device tree support for the TPS6586x PMU used on Harmony has recently
been added. This commit adds the required device tree nodes to probe the
PMU from the device tree.
diff --git a/arch/arm/boot/dts/tegra-harmony.dts
* Stephen Warren wrote:
On 06/11/2012 09:05 AM, Thierry Reding wrote:
This commit adds support for instantiating the Tegra PCIe controller
from a device tree.
+++ b/Documentation/devicetree/bindings/pci/tegra-pcie.txt
Can we please name this nvidia,tegra20-pcie.txt to match the naming
* Jon Hunter jon-hun...@ti.com [120607 15:15]:
Simple DTS file for OMAP2420 SDP adding memory information to allow
device-tree
testing on an OMAP2420 SDP.
Verified that kernel boots with DT using a simple RAMDISK file-system on
OMAP2420 SDP.
I suspect this is the H4 board? If so, please
* Thierry Reding wrote:
AFAICT the even partitioning of the non-prefetchable and prefetchable
memory regions is arbitrary and it could potentially be useful to make
it configurable via the DT.
So it turns out that this isn't true. But apart from the comments in the
driver I couldn't find any
Add infrastructure to be able to modify the cpu_power of each core
Signed-off-by: Vincent Guittot vincent.guit...@linaro.org
---
arch/arm/include/asm/topology.h |2 ++
arch/arm/kernel/topology.c | 36 +++-
2 files changed, 37 insertions(+), 1
The factorization has also be proposed in another patch that is not merge yet.
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-January/080873.html
So it could be dropped depending of the state of the other patch.
Signed-off-by: Lorenzo Pieralisi lorenzo.pieral...@arm.com
Signed-off-by:
Heteregeneous ARM platform uses arch_scale_freq_power function
to reflect the relative capacity of each core
Signed-off-by: Vincent Guittot vincent.guit...@linaro.org
---
kernel/sched/features.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/kernel/sched/features.h
+ spi@10600 {
+ compatible = marvell,orion-spi;
+ #address-cells = 1;
+ #size-cells = 0;
+ cell-index = 0;
+ reg = 0x10600 0x28;
+ status = disabled;
+ };
From: Rob Herring rob.herr...@calxeda.com
This series defines clock bindings for Device-Tree and adds kernel
support using the common clock infrastructure. The last patch enables
DT clock support for the Calxeda Highbank platform.
I'm posting this again to solicit further review. There has been
From: Grant Likely grant.lik...@secretlab.ca
Based on work 1st by Ben Herrenschmidt and Jeremy Kerr, then by Grant
Likely, this patch adds support to clk_get to allow drivers to retrieve
clock data from the device tree.
Platforms scan for clocks in DT with of_clk_init and a match table, and
the
From: Grant Likely grant.lik...@secretlab.ca
Add support for DT fixed-clock binding to the common fixed rate clock
support.
Signed-off-by: Grant Likely grant.lik...@secretlab.ca
[Rob Herring] Rework and move into common clock infrastructure
Signed-off-by: Rob Herring rob.herr...@calxeda.com
---
From: Rob Herring rob.herr...@calxeda.com
Add clock binding information for primecell peripherals. For most, a
clock input name of apb_pclk is required. Any primecell peripherals
which are different will need to be documented separately.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
---
From: Rob Herring rob.herr...@calxeda.com
This adds real clock support to Calxeda Highbank SOC using the common
clock infrastructure.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
---
.../devicetree/bindings/clock/calxeda.txt | 17 +
arch/arm/Kconfig
On 06/12/2012 12:21 AM, Thierry Reding wrote:
* Stephen Warren wrote:
On 06/11/2012 09:05 AM, Thierry Reding wrote:
This commit adds support for instantiating the Tegra PCIe
controller from a device tree.
+++ b/Documentation/devicetree/bindings/pci/tegra-pcie.txt
Can we please name this
On 20120612-09:41, Rob Herring wrote:
From: Rob Herring rob.herr...@calxeda.com
This series defines clock bindings for Device-Tree and adds kernel
support using the common clock infrastructure. The last patch enables
DT clock support for the Calxeda Highbank platform.
I'm posting
On 06/12/2012 01:24 AM, Thierry Reding wrote:
* Thierry Reding wrote:
AFAICT the even partitioning of the non-prefetchable and
prefetchable memory regions is arbitrary and it could
potentially be useful to make it configurable via the DT.
So it turns out that this isn't true. But apart
On 06/12/2012 10:47 AM, Mike Turquette wrote:
On 20120612-09:41, Rob Herring wrote:
From: Rob Herring rob.herr...@calxeda.com
This series defines clock bindings for Device-Tree and adds kernel
support using the common clock infrastructure. The last patch enables
DT clock support
* Stephen Warren wrote:
On 06/12/2012 12:21 AM, Thierry Reding wrote:
* Stephen Warren wrote:
On 06/11/2012 09:05 AM, Thierry Reding wrote:
This commit adds support for instantiating the Tegra PCIe
controller from a device tree.
+++
* Stephen Warren wrote:
On 06/12/2012 12:10 AM, Thierry Reding wrote:
* Thierry Reding wrote:
* Stephen Warren wrote:
On 06/11/2012 09:05 AM, Thierry Reding wrote:
[...]
+static int tegra_pcie_disable_msi(struct platform_device
*pdev)
Should this free pcie-msi-pages?
Yes it
Hi Heiko,
On 6/2/2012 1:06 AM, Sekhar Nori wrote:
Hi Heiko,
On 5/30/2012 3:48 PM, Heiko Schocher wrote:
Signed-off-by: Heiko Schocher h...@denx.de
Cc: davinci-linux-open-sou...@linux.davincidsp.com
Cc: linux-arm-ker...@lists.infradead.org
Cc: devicetree-discuss@lists.ozlabs.org
Cc: Grant
On Tue, Jun 12, 2012 at 02:04:33PM +0200, Andrew Lunn wrote:
+ spi@10600 {
+ compatible = marvell,orion-spi;
+ #address-cells = 1;
+ #size-cells = 0;
+ cell-index = 0;
+ reg = 0x10600 0x28;
Tested on an OLPC XO-1.75. (MMP2, sdhci-pxav3, CONFIG_MACH_MMP2_DT=y)
Signed-off-by: Chris Ball c...@laptop.org
---
.../devicetree/bindings/mmc/sdhci-pxa.txt | 21
drivers/mmc/host/sdhci-pxav2.c | 52
drivers/mmc/host/sdhci-pxav3.c
On 6/12/2012 7:20 AM, Thierry Reding wrote:
* Stephen Warren wrote:
On 06/12/2012 12:21 AM, Thierry Reding wrote:
* Stephen Warren wrote:
On 06/11/2012 09:05 AM, Thierry Reding wrote:
This commit adds support for instantiating the Tegra PCIe
controller from a device tree.
+++
This patch adds a driver for the MLC NAND controller of the LPC32xx SoC.
Signed-off-by: Roland Stigge sti...@antcom.de
Signed-off-by: Alexandre Pereira da Silva aletes@gmail.com
---
Applies to v3.5-rc2 + LPC32xx SLC NAND driver (Kconfig + Makefile)
Changes since v7:
* Cleanup: Use mtd nand
On 06/12/2012 01:10 PM, Mitch Bradley wrote:
On 6/12/2012 7:20 AM, Thierry Reding wrote:
...
I came up with the following alternative:
pci {
compatible = nvidia,tegra20-pcie;
reg = 0x80003000 0x0800 /* PADS registers */
0x80003800
On 6/12/2012 9:46 AM, Stephen Warren wrote:
On 06/12/2012 01:10 PM, Mitch Bradley wrote:
On 6/12/2012 7:20 AM, Thierry Reding wrote:
...
I came up with the following alternative:
pci {
compatible = nvidia,tegra20-pcie;
reg =0x80003000 0x0800 /*
On 06/12/2012 11:20 AM, Thierry Reding wrote:
...
I came up with the following alternative:
pci {
compatible = nvidia,tegra20-pcie;
reg = 0x80003000 0x0800 /* PADS registers */
0x80003800 0x0200 /* AFI registers */
From: Stephen Warren swar...@nvidia.com
When compiling the current code-base with gcc 4.6.1, the following warning
is raised, which is interpreted as an error:
cc1: warnings being treated as errors
tests/setprop_inplace.c: In function ‘main’:
tests/setprop_inplace.c:62: error: format ‘%016llx’
From: Stephen Warren swar...@nvidia.com
When merging one device tree over the top of a previous tree, it is
possible to define a duplicate label that has the same name and points
to the same property or node. This is currently allowed by the duplicate
label checking code. However, alternative
On 6/12/2012 10:15 AM, Stephen Warren wrote:
On 06/12/2012 11:20 AM, Thierry Reding wrote:
...
I came up with the following alternative:
pci {
compatible = nvidia,tegra20-pcie;
reg =0x80003000 0x0800 /* PADS registers */
From: Stephen Warren swar...@nvidia.com
dtc currently allows the contents of properties to be changed, and the
contents of nodes to be added to. There are situations where removing
properties or nodes may be useful. This change implements the following
syntax to do that:
/ {
propname
On Fri, Jun 08, 2012 at 08:37:06PM +0800, Richard Zhao wrote:
Sometimes, the driver bindings may know what phy they use.
For example, when using device tree, the usb controller may have a
phandler pointing to usb phy.
Signed-off-by: Richard Zhao richard.z...@freescale.com
Reviewed-by: Marek
On Tue, Jun 12, 2012 at 02:48:12PM -0600, Stephen Warren wrote:
From: Stephen Warren swar...@nvidia.com
When compiling the current code-base with gcc 4.6.1, the following warning
is raised, which is interpreted as an error:
cc1: warnings being treated as errors
tests/setprop_inplace.c: In
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