From: Tang Yuantian yuantian.t...@freescale.com
As the function itself says it is caller's responsibility to call the
of_node_put(). So, remove it on success to keep the reference count
correct.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
drivers/of/base.c | 3 ---
1 file
Hi Greg,
Am Montag, den 08.04.2013, 10:40 -0700 schrieb Greg Kroah-Hartman:
On Mon, Apr 08, 2013 at 06:04:31PM +0200, Philipp Zabel wrote:
Hi,
the following patches allow to use the integrated Television Encoder
(TVEv2) on the i.MX53 SoC as VGA output encoder for the IPU. This is
Hi Roger,
On Mon, Mar 25, 2013 at 12:42:04PM +0200, Roger Quadros wrote:
Hi Samuel,
I've rebased this now on top of 3.9-rc4. Please pull this into your
next branch when appropriate. Thanks.
The following changes since commit 8bb9660418e05bb1845ac1a2428444d78e322cc7:
Linux 3.9-rc4
Am Donnerstag, den 04.04.2013, 09:53 +0200 schrieb Philipp Zabel:
Am Mittwoch, den 03.04.2013, 15:04 -0300 schrieb Fabio Estevam:
Fix typo in 'initially-in-reset' example.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
.../devicetree/bindings/reset/gpio-reset.txt |
On Tue, Apr 9, 2013 at 2:16 AM, Andrew Morton a...@linux-foundation.org wrote:
On Wed, 3 Apr 2013 20:39:43 -0600 Stephen Warren swar...@wwwdotorg.org
wrote:
A simple frame-buffer describes a raw memory region that may be rendered
to, with the assumption that the display hardware has already
On Mon, Apr 08, 2013 at 11:28:58PM +0100, Bjorn Helgaas wrote:
On Tue, Mar 26, 2013 at 10:52 AM, Thomas Petazzoni
thomas.petazz...@free-electrons.com wrote:
From: Thierry Reding thierry.red...@avionic-design.de
#endif /* LINUX_MSI_H */
diff --git a/include/linux/pci.h
Hi Rob,
Am Donnerstag, den 04.04.2013, 08:49 -0500 schrieb Rob Herring:
On 03/28/2013 11:35 AM, Philipp Zabel wrote:
From: Stephen Warren swar...@nvidia.com
This binding is intended to represent the hardware reset signals present
internally in most IC (SoC, FPGA, ...) designs.
It
On Mon, Apr 08, 2013 at 04:28:58PM -0600, Bjorn Helgaas wrote:
On Tue, Mar 26, 2013 at 10:52 AM, Thomas Petazzoni
thomas.petazz...@free-electrons.com wrote:
From: Thierry Reding thierry.red...@avionic-design.de
The new struct msi_chip is used to associated an MSI controller with a
PCI
On Tue, Apr 09, 2013 at 09:11:19AM +0100, Andrew Murray wrote:
[...]
Also I believe pci_alloc_child_bus function would need to be changed to add
b-msi = msi to inherit msi_chip for child buses in the above patch?
The patch already does:
child-msi = parent-msi;
in
On Tue, Apr 09, 2013 at 09:22:33AM +0100, Thierry Reding wrote:
On Tue, Apr 09, 2013 at 09:11:19AM +0100, Andrew Murray wrote:
[...]
Also I believe pci_alloc_child_bus function would need to be changed to add
b-msi = msi to inherit msi_chip for child buses in the above patch?
The patch
On Tue, Apr 9, 2013 at 4:45 AM, Rob Herring robherri...@gmail.com wrote:
On 04/08/2013 05:56 PM, Javier Martinez Canillas wrote:
On 04/09/2013 12:16 AM, Stephen Warren wrote:
On 04/08/2013 04:05 PM, Rob Herring wrote:
On 04/05/2013 02:48 AM, Javier Martinez Canillas wrote:
According to
For gapless tuning, there is no need for PLL reset and clkout power-down
when tuning output. silabs,gapless-tuning parameter enables gapless tuning
for specific clock output.
Signed-off-by: Michal Bachraty michal.bachr...@streamunlimited.com
---
.../devicetree/bindings/clock/silabs,si5351.txt
On Tue, Apr 9, 2013 at 10:26 AM, Javier Martinez Canillas
jav...@dowhile0.org wrote:
On Tue, Apr 9, 2013 at 4:45 AM, Rob Herring robherri...@gmail.com wrote:
On 04/08/2013 05:56 PM, Javier Martinez Canillas wrote:
On 04/09/2013 12:16 AM, Stephen Warren wrote:
On 04/08/2013 04:05 PM, Rob
Hi Sebastian,
I posted patch for gap-less tuning. It is based on v5 of your driver. This
patch was tested for tuning with 1ppm clock step.
Best,
Michal.
On Mon, Mar 25, 2013 at 12:54 PM, Sebastian Hesselbarth
sebastian.hesselba...@gmail.com wrote:
On Wed, Mar 20, 2013 at 5:48 PM, Daniel
Samuel,
You had the conflicts because a patch [*] was introduced and is not
required since the reset logic is being removed from the driver.
Anyways, I've rebased the 2 patches on top of mfd-next, so now it
shouldn't matter.
cheers,
-roger
[*]
commit 71f4b9cdfccfb82cff702fe61f4ace97a1dfb0e0
PHY reset GPIO handling will be done in the PHY driver
Signed-off-by: Roger Quadros rog...@ti.com
Acked-by: Felipe Balbi ba...@ti.com
Acked-by: Samuel Ortiz sa...@linux.intel.com
---
drivers/mfd/omap-usb-host.c | 28
1 files changed, 0 insertions(+), 28
Allows the OMAP HS USB host controller to be specified
via device tree.
Signed-off-by: Roger Quadros rog...@ti.com
Reviewed-by: Mark Rutland mark.rutl...@arm.com
---
.../devicetree/bindings/mfd/omap-usb-host.txt | 80 ++
drivers/mfd/omap-usb-host.c| 161
On Tue, Apr 09, 2013 at 01:22:29AM +0200, Laurent Pinchart wrote:
Hi Guennadi,
On Monday 08 April 2013 14:15:39 Guennadi Liakhovetski wrote:
On Mon, 8 Apr 2013, Laurent Pinchart wrote:
On Monday 08 April 2013 13:25:46 Guennadi Liakhovetski wrote:
On Mon, 8 Apr 2013, Laurent Pinchart
On Tue, Apr 09, 2013 at 11:39:16AM +0300, Roger Quadros wrote:
Samuel,
You had the conflicts because a patch [*] was introduced and is not
required since the reset logic is being removed from the driver.
Anyways, I've rebased the 2 patches on top of mfd-next, so now it
shouldn't matter.
Hi Stephen,
On Tue, Apr 09, 2013 at 03:30:20AM +0100, Stephen Boyd wrote:
Add a binding for the arm architected timer hardware's memory
mapped interface. The mmio timer hardware is made up of one base
frame and a collection of up to 8 timer frames, where each of the
8 timer frames can have
From: Tang Yuantian yuantian.t...@freescale.com
This adds the clock driver for Freescale PowerPC corenet
series SoCs using common clock infrastructure.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
v3:
- remove the module author
From: Tang Yuantian yuantian.t...@freescale.com
The following SoCs will be affected: p2041, p3041, p4080,
p5020, p5040
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
* resend for review
arch/powerpc/boot/dts/fsl/p2041si-post.dtsi | 62
On Tue, Apr 9, 2013 at 10:26 AM, Michal Bachraty
michal.bachr...@streamunlimited.com wrote:
For gapless tuning, there is no need for PLL reset and clkout power-down
when tuning output. silabs,gapless-tuning parameter enables gapless tuning
for specific clock output.
Michal,
does gapless
On 04/05/2013 06:58 PM, Tony Lindgren wrote:
* Roger Quadros rog...@ti.com [130405 03:44]:
On 04/04/2013 07:41 PM, Tony Lindgren wrote:
* Roger Quadros rog...@ti.com [130404 00:39]:
On 04/04/2013 02:42 AM, Tony Lindgren wrote:
For v3.10, let's just make sure that USB works with DT as then
On 04/05/2013 08:56 PM, Grygorii Strashko wrote:
On 04/04/2013 07:41 PM, Tony Lindgren wrote:
* Roger Quadros rog...@ti.com [130404 00:39]:
On 04/04/2013 02:42 AM, Tony Lindgren wrote:
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ b/arch/arm/mach-omap2/cclock44xx_data.c
@@ -27,6 +27,7 @@
On Mon, 08 Apr 2013 12:46:47 +0200
Lars-Peter Clausen l...@metafoo.de wrote:
...
+static struct dma_chan *mpc_dma_xlate(struct of_phandle_args *dma_spec,
+ struct of_dma *ofdma)
+{
+ int count = dma_spec-args_count;
+ struct mpc_dma *mdma =
Patch series addresses below issues:
1) Do clk_get on dev_id when there is single clock for a module
2) Fix garbled UART log with DT kernel on da850-evm.
Applies on top of v3.9-rc9 of Linus's.
Tested on da850-evm. Able to see proper bootup log and console on UART2.
Manjunathappa, Prakash (4):
Populate OF_DEV_AUXDATA with desired device name so as to prevent
clk_get failures.
Signed-off-by: Manjunathappa, Prakash prakash...@ti.com
---
arch/arm/mach-davinci/da8xx-dt.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-davinci/da8xx-dt.c
For modules having single clock, clk_get should be done with dev_id.
But current davinci implementation handles multiple instances
of the UART devices with single platform_device_register. Hence clk_get
is based on con_id rather than dev_id, this is not correct. Do
platform_device_register for
DT kernel on da850-evm comes up with garbled UART logs. This is because
of mismatch in actual module clock rate and rate specified(clock-frequency)
in DT blob. kernel should not assume or depend on bootloaders clock
configuration, instead let it find the clock rate at runtime.
Issue discussed
Serial clocks are enabled from of_platform_serial_setup:of_serial.c,
so remove davinci_serial_setup_clk from here.
Signed-off-by: Manjunathappa, Prakash prakash...@ti.com
---
arch/arm/mach-davinci/da8xx-dt.c |8
1 files changed, 0 insertions(+), 8 deletions(-)
diff --git
On Mon, Apr 08, 2013 at 04:46:18PM +0200, Philipp Zabel wrote:
Hi,
the first two are just cleanups, the following three patches are changes
to the i.MX53 clock tree that are necessary to use the TVEv2 module as
VGA output on the Freescale i.MX53-QSB or TQ MBa53 boards.
regards
Philipp
On Mon, Apr 08, 2013 at 06:04:38PM +0200, Philipp Zabel wrote:
This driver adds support for the Television Encoder integrated
on i.MX53 SoCs (TVEv2).
Currently only the VGA output mode is supported, which only uses
the TVDAC to generate RGB levels. HSYNC and VSYNC signals are
routed
Hi Joachim,
On 02/14/2013 11:02 PM, Joachim Eastwood :
Signed-off-by: Joachim Eastwood manab...@gmail.com
---
.../devicetree/bindings/watchdog/atmel-at91rm9200-wdt.txt| 9
+
drivers/watchdog/Kconfig | 2 +-
On 04/09/13 02:08, Mark Rutland wrote:
On Tue, Apr 09, 2013 at 03:30:20AM +0100, Stephen Boyd wrote:
-** Timer node properties:
+** CP15 Timer node properties:
- compatible : Should at least contain one of
arm,armv7-timer
@@ -26,3 +30,55 @@ Example:
1
* Roger Quadros rog...@ti.com [130409 03:00]:
On 04/05/2013 06:58 PM, Tony Lindgren wrote:
Well your approach is fine as a first step moving all the clock
code, but it needs to be a real driver under drivers/clock/omap.
And the DT binding needs to stay the same for the driver(s) in the
The GPMC timing properties for device-tree have been updated
by adding a -ns or -ps suffix to indicate the units of
time the property represents. Therefore, update the timing
property names for TI GPMC NAND example.
Signed-off-by: Jon Hunter jon-hun...@ti.com
---
* Tony Lindgren t...@atomide.com [130409 09:54]:
* Roger Quadros rog...@ti.com [130409 03:00]:
On 04/05/2013 06:58 PM, Tony Lindgren wrote:
Can't you just use the clock name there to get it?
In device tree we don't pass around clock names. You can either get
a phandle or an index
Dear Arnd Bergmann,
On Tue, 9 Apr 2013 00:14:06 +0200, Arnd Bergmann wrote:
pcie-realio.type = IORESOURCE_IO;
pcie-realio.start = max(PCIBIOS_MIN_IO, range-pci_addr);
pcie-realio.end = max(IO_SPACE_LIMIT, range-pci_addr + range-size);
Shouldn't this last line be using min()
On Tuesday 09 April 2013, Thomas Petazzoni wrote:
Dear Arnd Bergmann,
On Tue, 9 Apr 2013 00:14:06 +0200, Arnd Bergmann wrote:
pcie-realio.type = IORESOURCE_IO;
pcie-realio.start = max(PCIBIOS_MIN_IO, range-pci_addr);
pcie-realio.end = max(IO_SPACE_LIMIT,
On 04/05/2013 01:46 PM, Stephen Warren wrote:
Rob, it might be worth keeping this in a separate branch in linux-next
so you can pull it out if it causes any issues. I've been using these
patches for quite a while now, but there's always opportunity for
surprises on architectures I don't use. I
Wolfram,
Thanks for your review!
On Mon, Apr 8, 2013 at 3:26 AM, Wolfram Sang w...@the-dreams.de wrote:
I'd like to have the bindings more generic. They should allow for n
possible masters IMO. It doesn't need to be implemented right now, but
it should be possible to add that later.
Done.
The i2c-arb-gpio-challenge driver implements an I2C arbitration scheme
where masters need to claim the bus with a GPIO before they can start
a transcation. This should generally only be used when standard I2C
multimaster isn't appropriate for some reason (errata/bugs).
This driver is based on
On 10:43-20130409, Tony Lindgren wrote:
* Tony Lindgren t...@atomide.com [130409 09:54]:
* Roger Quadros rog...@ti.com [130409 03:00]:
On 04/05/2013 06:58 PM, Tony Lindgren wrote:
Can't you just use the clock name there to get it?
In device tree we don't pass around clock
Hi All,
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 7f809fd..82ebff9 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -116,7 +116,7 @@ config ARM_SP805_WATCHDOG
config AT91RM9200_WATCHDOG
tristate AT91RM9200 watchdog
-
Hello,
This series of patches introduces PCIe support for the Marvell Armada
370 and Armada XP. In the future, we plan to extend the driver to
cover Kirkwood platforms, and possibly other Marvell EBU platforms as
well.
Here is the current status of the different patches:
* Patches 1-5 are
From: Andrew Murray andrew.mur...@arm.com
The pci_process_bridge_OF_ranges function, used to parse the ranges
property of a PCI host device, is found in both Microblaze and PowerPC
architectures. These implementations are nearly identical. This patch
moves this common code to a common place.
From: Andrew Murray andrew.mur...@arm.com
This patch factors out common implementation patterns to reduce
overall kernel code and provide a means for host bridge drivers to
directly obtain struct resources from the DT's ranges property without
relying on architecture specific DT handling. This
From: Andrew Murray andrew.mur...@arm.com
This patch converts the pci_load_of_ranges function to use the new
common of_pci_range_parser.
Signed-off-by: Andrew Murray andrew.mur...@arm.com
Signed-off-by: Liviu Dudau liviu.du...@arm.com
Signed-off-by: Thomas Petazzoni
From: Thierry Reding thierry.red...@avionic-design.de
This function can be used to parse the device and function number from a
standard 5-cell PCI resource. PCI_SLOT() and PCI_FUNC() can be used on
the returned value obtain the device and function numbers respectively.
Signed-off-by: Thierry
As agreed by the community, PCI host drivers will now be stored in
drivers/pci/host. This commit adds this directory and the related
Kconfig/Makefile changes to allow new drivers to be added in this
directory.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
Acked-by: Bjorn
The PCI specifications says that an I/O region must be aligned on a 4
KB boundary, and a memory region aligned on a 1 MB boundary.
However, the Marvell PCIe interfaces rely on address decoding windows
(which allow to associate a range of physical addresses with a given
device). For PCIe memory
The Armada 370 has two gatable clocks for each PCIe interface, and we
want both of them to be enabled. We therefore make one of the two
clocks a child of the other, as we did for the sataX and sataXlnk
clocks on Armada XP.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
Cc:
The current revision of the datasheet only mentions the gatable clocks
for the PCIe 0.0, 0.1, 0.2 and 0.3 interfaces, and forgot to mention
the ones for the PCIe 1.0, 1.1, 1.2, 1.3, 2.0 and 3.0
interfaces. After confirmation with Marvell engineers, this patch adds
the missing gatable clocks for
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup
Now that the PCIe driver for mvebu has been integrated and all its
relevant dependencies, we can mark the ARCH_MVEBU platform has
MIGHT_HAVE_PCI, which allows to select the PCI bus support if needed.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
The Armada 370 SoC has two 1x PCIe 2.0 interfaces, so we add the
necessary Device Tree informations to make these interfaces availabel.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/boot/dts/armada-370.dtsi | 51 +
1 file
The Armada XP SoCs have multiple PCIe interfaces. The MV78230 has 2
PCIe units (one 4x or quad 1x, the other 1x only), the MV78260 has 3
PCIe units (two 4x or quad 1x and one 4x/1x), the MV78460 has 4 PCIe
units (two 4x or quad 1x and two 4x/1x). We therefore add the
necessary Device Tree
The PlatHome OpenBlocks AX3-4 has an internal mini-PCIe slot that can
be used to plug mini-PCIe devices. We therefore enable the PCIe
interface that corresponds to this slot.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
The Marvell evaluation board (DB) for the Armada XP SoC has 6
physicals full-size PCIe slots, so we enable the corresponding PCIe
interfaces in the Device Tree.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/boot/dts/armada-xp-db.dts | 33
The Globalscale Mirabox platform uses one PCIe interface for an
available mini-PCIe slot, and the other PCIe interface for an internal
USB 3.0 controller. We add the necessary Device Tree informations to
enable those two interfaces.
Signed-off-by: Thomas Petazzoni
The Marvell evaluation board (DB) for the Armada 370 SoC has 2
physical full-size PCIe slots, so we enable the corresponding PCIe
interfaces in the Device Tree.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/boot/dts/armada-370-db.dts | 17 +
1
The Marvell Armada XP GP board has 3 physical full-size PCIe slots, so
we enable the corresponding PCIe interfaces in the Device Tree.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/boot/dts/armada-xp-gp.dts | 21 +
1 file changed, 21
Now that we have the necessary drivers and Device Tree informations to
support PCIe on Armada 370 and Armada XP, enable the CONFIG_PCI
option.
Also, since the Armada 370 Mirabox has a built-in USB XHCI controller
connected on the PCIe bus, enable the corresponding options as well.
Signed-off-by:
On Tue, Apr 9, 2013 at 3:06 PM, Thomas Petazzoni
thomas.petazz...@free-electrons.com wrote:
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Dear Bjorn Helgaas,
On Tue, 9 Apr 2013 15:12:58 -0600, Bjorn Helgaas wrote:
On Tue, Apr 9, 2013 at 3:06 PM, Thomas Petazzoni
thomas.petazz...@free-electrons.com wrote:
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might
The i2c-arb-gpio-challenge driver implements an I2C arbitration scheme
where masters need to claim the bus with a GPIO before they can start
a transcation. This should generally only be used when standard I2C
multimaster isn't appropriate for some reason (errata/bugs).
This driver is based on
On 15:49-20130409, Nishanth Menon wrote:
On 10:43-20130409, Tony Lindgren wrote:
* Tony Lindgren t...@atomide.com [130409 09:54]:
* Roger Quadros rog...@ti.com [130409 03:00]:
On 04/05/2013 06:58 PM, Tony Lindgren wrote:
Can't you just use the clock name there to get
* Nishanth Menon n...@ti.com [130409 13:53]:
I did try to have an implementation for cpufreq using clock nodes.
unfortunately, device tree wont let me have arguments of strings :(
So, I am unable to do clock = clk mpu_dpll;
instead, I am forced to do clock = clk 249;
It seems that you should
Hi Guennadi,
On Mon, Apr 8, 2013 at 5:08 PM, Guennadi Liakhovetski
g.liakhovet...@gmx.de wrote:
Most Renesas irqpin controllers have 4-bit sense fields, however, some
have different widths. This patch adds a DT binding to optionally
specify such non-standard values.
Signed-off-by: Guennadi
On Tue, Apr 09, 2013 at 09:44:46AM +0200, Philipp Zabel wrote:
Hi Greg,
Am Montag, den 08.04.2013, 10:40 -0700 schrieb Greg Kroah-Hartman:
On Mon, Apr 08, 2013 at 06:04:31PM +0200, Philipp Zabel wrote:
Hi,
the following patches allow to use the integrated Television Encoder
On Wed, Apr 10, 2013 at 07:23:06AM +0900, Magnus Damm wrote:
Hi Guennadi,
On Mon, Apr 8, 2013 at 5:08 PM, Guennadi Liakhovetski
g.liakhovet...@gmx.de wrote:
Most Renesas irqpin controllers have 4-bit sense fields, however, some
have different widths. This patch adds a DT binding to
On Fri, Apr 05, 2013 at 11:13:39AM +0900, Simon Horman wrote:
On Fri, Apr 05, 2013 at 10:44:29AM +0900, Simon Horman wrote:
On Thu, Apr 04, 2013 at 11:47:05PM +0200, Guennadi Liakhovetski wrote:
Hi Simon
On Thu, 4 Apr 2013, Simon Horman wrote:
On Wed, Apr 03, 2013 at
On Wed, Apr 03, 2013 at 11:19:07AM +0200, Guennadi Liakhovetski wrote:
Add an irqpin interrupt controller DT node on marzen-reference.
Signed-off-by: Guennadi Liakhovetski g.liakhovetski+rene...@gmail.com
Thanks, queued up in the boards-marzen branch.
On Wed, Apr 10, 2013 at 10:08:18AM +0900, Simon Horman wrote:
On Fri, Apr 05, 2013 at 11:13:39AM +0900, Simon Horman wrote:
On Fri, Apr 05, 2013 at 10:44:29AM +0900, Simon Horman wrote:
On Thu, Apr 04, 2013 at 11:47:05PM +0200, Guennadi Liakhovetski wrote:
Hi Simon
On Thu, 4 Apr
From: Tang Yuantian yuantian.t...@freescale.com
Call of_node_put() only when the out_args is NULL on success,
or the node's reference count will not be correct because the caller
will call of_node_put() again.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
v2:
- modified
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