On 9/19/2011 11:53 PM, Rob Herring wrote:
On 09/19/2011 04:14 PM, Grant Likely wrote:
On Mon, Sep 19, 2011 at 7:48 AM, Rob Herringrobherri...@gmail.com wrote:
On 09/19/2011 07:09 AM, Cousson, Benoit wrote:
On 9/18/2011 11:23 PM, Rob Herring wrote:
I was headed down the path of implementing
On 9/18/2011 8:15 AM, Grant Likely wrote:
On Thu, Sep 15, 2011 at 12:07:25PM +0200, Cousson, Benoit wrote:
Hi Rob,
On 9/15/2011 9:55 AM, Thomas Abraham wrote:
Hi Rob,
On 14 September 2011 22:01, Rob Herringrobherri...@gmail.com wrote:
From: Rob Herringrob.herr...@calxeda.com
This adds
On Sun, Sep 18, 2011 at 7:21 AM, Grant Likely grant.lik...@secretlab.ca wrote:
On Fri, Sep 16, 2011 at 05:09:39PM +0100, Dave Martin wrote:
For now, we express the mapping by putting an interrupt-map in the
core-tile DT, but this feels inelegant as well as wasteful -- expressing
+ 32 using a
On 9/18/2011 11:23 PM, Rob Herring wrote:
On 09/15/2011 11:43 AM, Rob Herring wrote:
On 09/15/2011 08:52 AM, Cousson, Benoit wrote:
On 9/15/2011 3:11 PM, Rob Herring wrote:
On 09/15/2011 05:07 AM, Cousson, Benoit wrote:
[...]
I have another concern on a similar topic.
On OMAP4 the SoC
Hi Grant,
On 18 September 2011 11:40, Grant Likely grant.lik...@secretlab.ca wrote:
On Fri, Sep 16, 2011 at 03:04:11PM +0530, Thomas Abraham wrote:
Hi Rob,
On 15 September 2011 18:24, Rob Herring robherri...@gmail.com wrote:
On 09/15/2011 02:55 AM, Thomas Abraham wrote:
+void __init
On 9/19/2011 2:07 PM, Dave Martin wrote:
On Sun, Sep 18, 2011 at 7:21 AM, Grant Likelygrant.lik...@secretlab.ca wrote:
On Fri, Sep 16, 2011 at 05:09:39PM +0100, Dave Martin wrote:
For now, we express the mapping by putting an interrupt-map in the
core-tile DT, but this feels inelegant as well
On Mon, Sep 19, 2011 at 11:47:18AM +0200, Cousson, Benoit wrote:
Since the cpumask is not relevant for the SPI, maybe having two
interrupt controllers will be more relevant. Or maybe 3, since there is
some SGIs as well.
I don't think anyone uses SGIs outside of the common SMP code.
On 09/19/2011 07:09 AM, Cousson, Benoit wrote:
On 9/18/2011 11:23 PM, Rob Herring wrote:
On 09/15/2011 11:43 AM, Rob Herring wrote:
On 09/15/2011 08:52 AM, Cousson, Benoit wrote:
On 9/15/2011 3:11 PM, Rob Herring wrote:
On 09/15/2011 05:07 AM, Cousson, Benoit wrote:
[...]
I have another
On 9/19/2011 3:48 PM, Rob Herring wrote:
On 09/19/2011 07:09 AM, Cousson, Benoit wrote:
On 9/18/2011 11:23 PM, Rob Herring wrote:
On 09/15/2011 11:43 AM, Rob Herring wrote:
On 09/15/2011 08:52 AM, Cousson, Benoit wrote:
On 9/15/2011 3:11 PM, Rob Herring wrote:
On 09/15/2011 05:07 AM,
On Mon, Sep 19, 2011 at 02:09:46PM +0200, Cousson, Benoit wrote:
Every CortexA9 based SoC have to add the 32 offset to the SoC level
interrupt number line. The ID numbering scheme is relevant only inside
the GIC, but at SoC level only the IRQ lines that entered the MP core
are relevant. That
On Mon, Sep 19, 2011 at 7:33 AM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Mon, Sep 19, 2011 at 11:47:18AM +0200, Cousson, Benoit wrote:
Since the cpumask is not relevant for the SPI, maybe having two
interrupt controllers will be more relevant. Or maybe 3, since there is
some
On Sun, Sep 18, 2011 at 04:23:40PM -0500, Rob Herring wrote:
On 09/15/2011 11:43 AM, Rob Herring wrote:
I see 2 options (besides leaving it as is):
- Revert back to my previous binding where PPIs are a sub-node and a
different interrupt parent.
- Use the current binding, but allow
On Mon, Sep 19, 2011 at 3:53 PM, Rob Herring robherri...@gmail.com wrote:
On 09/19/2011 04:14 PM, Grant Likely wrote:
* ARM Generic Interrupt Controller
ARM SMP cores are often associated with a GIC, providing per processor
interrupts (PPI), shared processor interrupts (SPI) and software
On Mon, Sep 19, 2011 at 04:53:39PM -0500, Rob Herring wrote:
On 09/19/2011 04:14 PM, Grant Likely wrote:
(Alternately, if there is no need for a CPU mask because PPI
interrupts will never be wired to more than one CPU, then it would be
better to encode the CPU number into the second cell
On Fri, Sep 16, 2011 at 03:04:11PM +0530, Thomas Abraham wrote:
Hi Rob,
On 15 September 2011 18:24, Rob Herring robherri...@gmail.com wrote:
On 09/15/2011 02:55 AM, Thomas Abraham wrote:
+void __init gic_of_init(struct device_node *node, struct device_node
*parent)
+{
+ void
On Fri, Sep 16, 2011 at 05:09:39PM +0100, Dave Martin wrote:
For now, we express the mapping by putting an interrupt-map in the
core-tile DT, but this feels inelegant as well as wasteful -- expressing
+ 32 using a table which is about 1K in size and duplicates that
information 43 times.
On Thu, Sep 15, 2011 at 12:07:25PM +0200, Cousson, Benoit wrote:
Hi Rob,
On 9/15/2011 9:55 AM, Thomas Abraham wrote:
Hi Rob,
On 14 September 2011 22:01, Rob Herringrobherri...@gmail.com wrote:
From: Rob Herringrob.herr...@calxeda.com
This adds gic initialization using device tree
On Wed, Sep 14, 2011 at 11:31:40AM -0500, Rob Herring wrote:
From: Rob Herring rob.herr...@calxeda.com
This adds gic initialization using device tree data. The initialization
functions are intended to be called by a generic OF interrupt
controller parsing function once the right pieces are
On 09/15/2011 11:43 AM, Rob Herring wrote:
Benoit,
On 09/15/2011 08:52 AM, Cousson, Benoit wrote:
On 9/15/2011 3:11 PM, Rob Herring wrote:
Benoit,
On 09/15/2011 05:07 AM, Cousson, Benoit wrote:
Hi Rob,
On 9/15/2011 9:55 AM, Thomas Abraham wrote:
Hi Rob,
On 14 September 2011 22:01,
On Wed, Sep 14, 2011 at 01:51:42PM -0500, Rob Herring wrote:
On 09/14/2011 01:34 PM, Marc Zyngier wrote:
Hi Rob,
On 14/09/11 18:57, Rob Herring wrote:
Marc,
On 09/14/2011 12:46 PM, Marc Zyngier wrote:
On 14/09/11 17:31, Rob Herring wrote:
From: Rob Herring rob.herr...@calxeda.com
Hi Rob,
On 15 September 2011 18:24, Rob Herring robherri...@gmail.com wrote:
On 09/15/2011 02:55 AM, Thomas Abraham wrote:
Hi Rob,
On 14 September 2011 22:01, Rob Herring robherri...@gmail.com wrote:
From: Rob Herring rob.herr...@calxeda.com
This adds gic initialization using device tree
On Thu, Sep 15, 2011 at 12:07:25PM +0200, Cousson, Benoit wrote:
Hi Rob,
On 9/15/2011 9:55 AM, Thomas Abraham wrote:
Hi Rob,
On 14 September 2011 22:01, Rob Herringrobherri...@gmail.com wrote:
From: Rob Herringrob.herr...@calxeda.com
This adds gic initialization using device tree
Hi Rob,
On 9/15/2011 9:55 AM, Thomas Abraham wrote:
Hi Rob,
On 14 September 2011 22:01, Rob Herringrobherri...@gmail.com wrote:
From: Rob Herringrob.herr...@calxeda.com
This adds gic initialization using device tree data. The initialization
functions are intended to be called by a generic
On Thu, Sep 15, 2011 at 12:07:25PM +0200, Cousson, Benoit wrote:
On OMAP4 the SoC interrupts external to the MPU (SPI) have an offset of
32. Only the internal PPI are between 0 and 31.
SGIs are 0 to 15, PPIs are 16 to 31, and SPIs are 32+ - that's the
numbering given to us by the GIC.
The
On Wednesday 14 September 2011, Rob Herring wrote:
From: Rob Herring rob.herr...@calxeda.com
This adds gic initialization using device tree data. The initialization
functions are intended to be called by a generic OF interrupt
controller parsing function once the right pieces are in place.
On 9/15/2011 12:29 PM, Russell King - ARM Linux wrote:
On Thu, Sep 15, 2011 at 12:07:25PM +0200, Cousson, Benoit wrote:
On OMAP4 the SoC interrupts external to the MPU (SPI) have an offset of
32. Only the internal PPI are between 0 and 31.
SGIs are 0 to 15, PPIs are 16 to 31, and SPIs are 32+
On Thu, Sep 15, 2011 at 02:28:06PM +0200, Cousson, Benoit wrote:
The HW specs is obviously counting the IRQ number at the GIC interface.
That offset is not known outside the MPUSS. Please have a look at the
OMAP4430 TRM p4761 (NDA vM version).
As far as I know, I have no access to that.
On 09/15/2011 02:55 AM, Thomas Abraham wrote:
Hi Rob,
On 14 September 2011 22:01, Rob Herring robherri...@gmail.com wrote:
From: Rob Herring rob.herr...@calxeda.com
This adds gic initialization using device tree data. The initialization
functions are intended to be called by a generic OF
On 9/15/2011 2:51 PM, Russell King - ARM Linux wrote:
On Thu, Sep 15, 2011 at 02:28:06PM +0200, Cousson, Benoit wrote:
The HW specs is obviously counting the IRQ number at the GIC interface.
That offset is not known outside the MPUSS. Please have a look at the
OMAP4430 TRM p4761 (NDA vM
Benoit,
On 09/15/2011 05:07 AM, Cousson, Benoit wrote:
Hi Rob,
On 9/15/2011 9:55 AM, Thomas Abraham wrote:
Hi Rob,
On 14 September 2011 22:01, Rob Herringrobherri...@gmail.com wrote:
From: Rob Herringrob.herr...@calxeda.com
This adds gic initialization using device tree data. The
On 9/15/2011 3:11 PM, Rob Herring wrote:
Benoit,
On 09/15/2011 05:07 AM, Cousson, Benoit wrote:
Hi Rob,
On 9/15/2011 9:55 AM, Thomas Abraham wrote:
Hi Rob,
On 14 September 2011 22:01, Rob Herringrobherri...@gmail.com wrote:
From: Rob Herringrob.herr...@calxeda.com
This adds gic
Benoit,
On 09/15/2011 08:52 AM, Cousson, Benoit wrote:
On 9/15/2011 3:11 PM, Rob Herring wrote:
Benoit,
On 09/15/2011 05:07 AM, Cousson, Benoit wrote:
Hi Rob,
On 9/15/2011 9:55 AM, Thomas Abraham wrote:
Hi Rob,
On 14 September 2011 22:01, Rob Herringrobherri...@gmail.com wrote:
From:
Marc,
On 09/14/2011 12:46 PM, Marc Zyngier wrote:
On 14/09/11 17:31, Rob Herring wrote:
From: Rob Herring rob.herr...@calxeda.com
This adds gic initialization using device tree data. The initialization
functions are intended to be called by a generic OF interrupt
controller parsing function
On 14/09/11 17:31, Rob Herring wrote:
From: Rob Herring rob.herr...@calxeda.com
This adds gic initialization using device tree data. The initialization
functions are intended to be called by a generic OF interrupt
controller parsing function once the right pieces are in place.
PPIs are
Hi Rob,
On 14/09/11 18:57, Rob Herring wrote:
Marc,
On 09/14/2011 12:46 PM, Marc Zyngier wrote:
On 14/09/11 17:31, Rob Herring wrote:
From: Rob Herring rob.herr...@calxeda.com
This adds gic initialization using device tree data. The initialization
functions are intended to be called by a
On 09/14/2011 01:34 PM, Marc Zyngier wrote:
Hi Rob,
On 14/09/11 18:57, Rob Herring wrote:
Marc,
On 09/14/2011 12:46 PM, Marc Zyngier wrote:
On 14/09/11 17:31, Rob Herring wrote:
From: Rob Herring rob.herr...@calxeda.com
This adds gic initialization using device tree data. The
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