On Wed, Jan 18, 2012 at 06:04:53PM +, Russell King - ARM Linux wrote:
On Wed, Jan 18, 2012 at 05:50:28PM +, Lorenzo Pieralisi wrote:
I agree with you Russell, that's 100% valid on a single cluster. But on
a multi-cluster (eg dual-cluster) the MPIDR might be wired like this:
On Thu, Jan 19, 2012 at 12:18:32PM +, Catalin Marinas wrote:
On Wed, Jan 18, 2012 at 06:04:53PM +, Russell King - ARM Linux wrote:
On Wed, Jan 18, 2012 at 05:50:28PM +, Lorenzo Pieralisi wrote:
This sounds like you're saying that the contents of MPIDR might be buggy
sometime
On Wed, Jan 18, 2012 at 06:04:53PM +, Russell King - ARM Linux wrote:
On Wed, Jan 18, 2012 at 05:50:28PM +, Lorenzo Pieralisi wrote:
This sounds like you're saying that the contents of MPIDR might be buggy
sometime in the future? Do we actually know of any situations where the
The introduction of multi-cluster ARM systems in SoC designs requires the kernel
to become cluster aware, so that it can be booted on every CPU in the system
and it can build an appropriate representation of topology levels.
Current code in the kernel, in particular the boot sequence, hinges upon
On 01/18/2012 08:36 AM, Lorenzo Pieralisi wrote:
The introduction of multi-cluster ARM systems in SoC designs requires the
kernel
to become cluster aware, so that it can be booted on every CPU in the system
and it can build an appropriate representation of topology levels.
Current code in
On Wed, Jan 18, 2012 at 03:38:54PM +, Rob Herring wrote:
On 01/18/2012 08:36 AM, Lorenzo Pieralisi wrote:
The introduction of multi-cluster ARM systems in SoC designs requires the
kernel
to become cluster aware, so that it can be booted on every CPU in the system
and it can build an
On Wed, Jan 18, 2012 at 02:36:43PM +, Lorenzo Pieralisi wrote:
Current code in the kernel, in particular the boot sequence, hinges upon a
sequential mapping of MPIDR values for cpus and related interrupt
controller CPU interfaces to logical cpu indexing.
I don't believe it does. What it
On Wed, Jan 18, 2012 at 04:24:23PM +, Russell King - ARM Linux wrote:
On Wed, Jan 18, 2012 at 02:36:43PM +, Lorenzo Pieralisi wrote:
Current code in the kernel, in particular the boot sequence, hinges upon a
sequential mapping of MPIDR values for cpus and related interrupt
