Hollis Blanchard wrote:
On Thu, 2010-01-07 at 20:35 -0600, Hunter Cobbs wrote:
I think that is definitely a solution. It does centralize the testing
for this particular issue. The only thing question I have is if its
really better to have the upper level do the check. Shouldn't the
driver
Grant Likely wrote:
On Wed, Jan 13, 2010 at 10:23 AM, Scott Wood scottw...@freescale.com wrote:
Grant Likely wrote:
On Wed, Jan 13, 2010 at 7:19 AM, Yoder Stuart-B08248
b08...@freescale.com wrote:
It does not sound sane or
particularly parseable to stuff it into bitfields within the second
Grant Likely wrote:
On Mon, Feb 22, 2010 at 9:13 AM, Yoder Stuart-B08248
We had a similar problem in the Freescale Embedded Hypervisor
to control the generation of guest device trees. We defined
several 'magic' properties that had special meaning in
the context of a node update.
heh, so the
Segher Boessenkool wrote:
As far as I can see, you want that indirection node so that you
safe space in the DTB.
Probably more of a general desire to not duplicate things that don't
need to be duplicated... I don't think the space issue is critical in
this particular case.
With real OF
Grant Likely wrote:
[cc'd David Gibson]
On Thu, Mar 25, 2010 at 8:42 AM, Timur Tabi ti...@freescale.com wrote:
The initrd thing is a good idea, but it doesn't help non-Linux
operating systems. Then again, those OS's might not have any GPL
issues, so it could be a moot point.
The more I
Timur Tabi wrote:
Grant Likely wrote:
On Thu, Mar 25, 2010 at 9:29 AM, Mitch Bradley w...@firmworks.com wrote:
It seems to me that there are plausible use cases for both direct-inclusion
and indirection. I don't see any real problems with either, so I would vote
for specifying both
Grant Likely wrote:
On Thu, Mar 25, 2010 at 11:03 AM, Timur Tabi ti...@freescale.com wrote:
Grant Likely wrote:
For indirect firmware, create a /chosen/firmware node. Don't add a
compatible property,
Oh, I don't like that idea at all. The compatible property is useful for me to
know *how*
Timur Tabi wrote:
On Fri, Apr 30, 2010 at 11:22 AM, Scott Wood scottw...@freescale.com wrote:
That's what I meant. Actually, I think it's ULL. Regardless, I think
the compiler will see the 10 ... * 1000 and just combine
them together. You're not actually outsmarting the compiler
Grant Likely wrote:
+ // IPIC
+ // interrupts cell = intr #, sense
+ // sense values match linux IORESOURCE_IRQ_* defines:
+ // sense == 8: Level, low assertion
+ // sense == 2: Edge, high-to-low change
+ //
+
On 05/14/2010 11:46 AM, Richard Cochran wrote:
diff --git a/Documentation/powerpc/dts-bindings/fsl/tsec.txt
b/Documentation/powerpc/dts-bindings/fsl/tsec.txt
index edb7ae1..b09ba66 100644
--- a/Documentation/powerpc/dts-bindings/fsl/tsec.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/tsec.txt
On 05/18/2010 01:36 AM, Richard Cochran wrote:
On Mon, May 17, 2010 at 01:05:54PM -0500, Scott Wood wrote:
+ - tmr_fiper1 Fixed interval period pulse generator.
+ - tmr_fiper2 Fixed interval period pulse generator.
MPC8572 and P2020 have fiper3 as well.
I doubt they really have
On 05/19/2010 08:18 PM, David Gibson wrote:
On Wed, May 19, 2010 at 07:03:17PM -0500, Timur Tabi wrote:
On Wed, May 19, 2010 at 5:44 PM, Benjamin Herrenschmidt
The padding in the kernel built is intended to
make space for DT changes done by the zImage wrapper.
Well, okay. I think it would
On 05/19/2010 04:47 PM, Grant Likely wrote:
On Wed, May 19, 2010 at 3:37 PM, Scott Woodscottw...@freescale.com wrote:
I believe the only part of this that is new with ePAPR is that it asks that
the interrupt controller address cells be explicitly specified, as it's a
bit icky for it to default
On Tue, 17 Aug 2010 15:55:04 -0500
Kumar Gala ga...@kernel.crashing.org wrote:
As I said to Stuart. On the Freescale SOCs we have different device
blocks w/varying dma address capabilities. Some are limited to 32-bits
some are capable of 36-bits on the same SOC.
Is this something that the
On Mon, 30 Aug 2010 14:03:05 +1000
David Gibson da...@gibson.dropbear.id.au wrote:
In device trees, the unit name portion of any node (the part after the
@) is supposed to be derived from the value of the node's 'reg'
property. However, this is not enforced by the structure of a dtb
file,
On Mon, 30 Aug 2010 14:34:44 -0700
Yoder Stuart-B08248 b08...@freescale.com wrote:
I've consolidated what I am aware of with respect to errors found in
1.0,
clarifications needed, and new mechanisms to go into ePAPR 1.1 into
a single list.
Let me know if you are aware of anything else.
On Wed, 8 Sep 2010 14:25:30 -0600
Grant Likely grant.lik...@secretlab.ca wrote:
On Wed, Sep 01, 2010 at 12:47:18PM +1000, David Gibson wrote:
Hi folks,
Here's a patch I made for dtc a little while ago, and I'm not sure if
it's something that sensibly ought to be merged into mainline
On Mon, 30 Aug 2010 14:34:44 -0700
Yoder Stuart-B08248 b08...@freescale.com wrote:
I've consolidated what I am aware of with respect to errors found in
1.0,
clarifications needed, and new mechanisms to go into ePAPR 1.1 into
a single list.
Let me know if you are aware of anything else.
On Thu, 16 Sep 2010 11:40:20 -0600
Grant Likely grant.lik...@secretlab.ca wrote:
However, what does compatible mean at the board level? Can a
BeagleBoard-xM claim compatibility with the original BeagleBoard? Or
even can a -b1 BeagleBoard claim compatibility with the original -a1
revision?
On Wed, 27 Oct 2010 13:42:27 +1100
David Gibson da...@gibson.dropbear.id.au wrote:
On Tue, Oct 26, 2010 at 08:37:55PM -0500, Timur Tabi wrote:
On Tue, Oct 26, 2010 at 7:51 PM, Mitch Bradley w...@firmworks.com wrote:
It's probably unnecessary on modern machines, but old PCs were fairly
On Thu, 18 Nov 2010 14:08:27 -0800
David VomLehn dvoml...@cisco.com wrote:
On Tue, Nov 09, 2010 at 10:25:37PM -0600, Grant Likely wrote:
On Wed, Nov 03, 2010 at 01:50:37PM -0700, David VomLehn wrote:
device-s {
compatible = cisco,device-s;
cisco,static-buffers =
On Wed, 8 Dec 2010 11:29:44 -0800
Deepak Saxena deepak_sax...@mentor.com wrote:
We only return the next child if the device is available.
Signed-off-by: Hollis Blanchard hollis_blanch...@mentor.com
Signed-off-by: Deepak Saxena deepak_sax...@mentor.com
---
drivers/of/base.c |4 +++-
1
On Wed, 22 Dec 2010 23:58:09 -0600
Meador Inge meador_i...@mentor.com wrote:
NOTE: The 'interrupt-parent' is implicit since message register nodes
are always children of interrupt controller nodes.
** Example:
mpic: p...@4 {
interrupt-controller;
On Wed, 5 Jan 2011 14:49:40 -0800
Blanchard, Hollis hollis_blanch...@mentor.com wrote:
On 01/05/2011 02:09 PM, Scott Wood wrote:
On Wed, 5 Jan 2011 15:58:55 -0600
Meador Ingemeador_i...@mentor.com wrote:
We need some sort of mapping between a message register and a message
register
On Mon, 17 Jan 2011 18:52:24 -0600
Meador Inge meador_i...@mentor.com wrote:
+** Required properties:
+
+ NOTE: Many of these descriptions were paraphrased from [1] to aid
+ readability.
+
+ - name : Specifies the name of the MPIC.
name isn't really a property with flat trees.
On Mon, 7 Feb 2011 15:53:09 -0600
Yoder Stuart-B08248 b08...@freescale.com wrote:
Could we not do both? Use an enum to identify the region type:
reserved = 0x1 0xc0 0x20; /* 2MB ramdisk
reserved = 0x2 0xbf 0x1000; /* devicetree */
reserved = 0x3 0x100 0x40;
On Fri, 11 Feb 2011 14:58:13 +
Yoder Stuart-B08248 b08...@freescale.com wrote:
-Original Message-
From: Meador Inge [mailto:mead...@gmail.com]
Sent: Thursday, February 10, 2011 9:26 PM
To: Benjamin Herrenschmidt
Cc: Yoder Stuart-B08248;
On Wed, 23 Feb 2011 09:50:58 -0700
Grant Likely grant.lik...@secretlab.ca wrote:
On Wed, Feb 23, 2011 at 11:38:17AM +0100, Richard Cochran wrote:
+
+* Gianfar PTP clock nodes
+
+General Properties:
+
+ - compatible Should be fsl,etsec-ptp
Should specify an *exact* part; ie:
On Wed, 23 Feb 2011 10:54:59 -0700
Grant Likely grant.lik...@secretlab.ca wrote:
On Wed, Feb 23, 2011 at 11:26:12AM -0600, Scott Wood wrote:
eTSEC is versioned, that's more reliable than the chip name since chips
have revisions (rev 2.1 of mpc8313 has eTSEC 1.6, not sure about previous
On Thu, 24 Feb 2011 17:39:44 +0100
Richard Cochran richardcoch...@gmail.com wrote:
On Wed, Feb 23, 2011 at 10:54:59AM -0700, Grant Likely wrote:
On Wed, Feb 23, 2011 at 11:26:12AM -0600, Scott Wood wrote:
The eTSEC revision is probeable as well, but due the way PTP is described
On Thu, 24 Feb 2011 17:50:04 +0100
Richard Cochran richardcoch...@gmail.com wrote:
On Wed, Feb 23, 2011 at 01:24:44PM -0600, Scott Wood wrote:
Whatever string is used should be written into a binding document.
fsl,etsec-v1.6-ptp seems like it would be just as good for that purpose
Signed-off-by: Scott Wood scottw...@freescale.com
---
arch/powerpc/include/asm/mpic.h |2 ++
arch/powerpc/sysdev/mpic.c | 37 -
2 files changed, 38 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm
Add support for MPIC timers as requestable interrupt sources.
Based on http://patchwork.ozlabs.org/patch/20941/ by Dave Liu.
Signed-off-by: Dave Liu dave...@freescale.com
Signed-off-by: Scott Wood scottw...@freescale.com
---
arch/powerpc/include/asm/mpic.h |3 +-
arch/powerpc/sysdev/mpic.c
, similar to msi-available-ranges.
Signed-off-by: Scott Wood scottw...@freescale.com
---
.../devicetree/bindings/powerpc/fsl/mpic-timer.txt | 38
.../devicetree/bindings/powerpc/fsl/mpic.txt |2 +-
2 files changed, 39 insertions(+), 1 deletions(-)
create mode 100644
-off-by: Scott Wood scottw...@freescale.com
---
arch/powerpc/boot/dts/p1022ds.dts | 106
1 files changed, 59 insertions(+), 47 deletions(-)
diff --git a/arch/powerpc/boot/dts/p1022ds.dts
b/arch/powerpc/boot/dts/p1022ds.dts
index 59ef405..4f685a7 100644
On Tue, 19 Apr 2011 11:59:34 -0500
Meador Inge meador_i...@mentor.com wrote:
+- interrupt-parent: Specifies the interrupt parent of the message
register
+ block. The type shall be a phandle and the value of that phandle
+ shall point to the interrupt parent.
interrupt-parent
On Tue, 19 Apr 2011 13:26:26 -0500
Meador Inge meador_i...@mentor.com wrote:
On 04/19/2011 12:52 PM, Scott Wood wrote:
On Tue, 19 Apr 2011 11:59:34 -0500
Meador Inge meador_i...@mentor.com wrote:
Aliases are of the form 'msgr-blockn',
+where n is an integer specifying the block's
On Wed, 20 Apr 2011 00:00:18 +0200
Hans J. Koch h...@hansjkoch.de wrote:
On Tue, Apr 19, 2011 at 12:08:16AM -0600, Grant Likely wrote:
PowerPC and x86 will return 0 for an unassigned IRQ, as will most platforms.
That might be right for these architectures. On ARM SoCs, IRQ0 is often a
On Thu, 21 Apr 2011 14:26:46 -0500
Meador Inge meador_i...@mentor.com wrote:
Hmmm ... In the MPC8572E and P1022DS manuals I don't see the terminology
group used for message registers.
I was looking at the P4080 manual, which does use it. It looks like some
other chip manuals just use
On Thu, 5 May 2011 16:41:29 -0500
Meador Inge meador_i...@mentor.com wrote:
/* OS 1 */
mpic_msgr_block0: mpic-msgr-block@41400 {
compatible = fsl,mpic-v3.1-msgr;
reg = 0x41400 0x200;
interrupts = 0xb0 2 0xb2 2;
hollis_blanch...@mentor.com
Cc: Grant Likely grant.lik...@secretlab.ca
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Acked-by: Scott Wood scottw...@freescale.com
---
.../devicetree/bindings/powerpc/fsl/mpic-msgr.txt | 62
1 files changed, 62 insertions(+), 0 deletions
On Fri, 20 May 2011 11:36:38 -0500
Meador Inge meador_i...@mentor.com wrote:
This binding documents how the message register blocks found in some FSL
MPIC implementations shall be represented in a device tree.
Signed-off-by: Meador Inge meador_i...@mentor.com
Cc: Hollis Blanchard
hollis_blanch...@mentor.com
Cc: Grant Likely grant.lik...@secretlab.ca
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: Scott Wood scottw...@freescale.com
---
.../devicetree/bindings/powerpc/fsl/mpic-msgr.txt | 62
1 files changed, 62 insertions(+), 0 deletions
On Fri, 17 Jun 2011 15:33:04 +1000
Benjamin Herrenschmidt b...@kernel.crashing.org wrote:
On Tue, 2011-05-31 at 14:19 -0500, Meador Inge wrote:
+void mpic_msgr_enable(struct mpic_msgr *msgr)
+{
+ out_be32(msgr-mer, in_be32(msgr-mer) | (1 msgr-num));
+}
On Sat, 18 Jun 2011 08:58:53 +1000
Benjamin Herrenschmidt b...@kernel.crashing.org wrote:
On Fri, 2011-06-17 at 11:58 -0500, Scott Wood wrote:
When did this change from considered an internal implementation
issue, and not really an interface to all new interfaces?
Interesting blurb
On Wed, 13 Jul 2011 19:52:12 +0400
Anton Vorontsov cbouatmai...@gmail.com wrote:
On Wed, Jul 06, 2011 at 03:05:18PM -0600, Grant Likely wrote:
On Thu, Jul 07, 2011 at 12:47:50AM +0800, Shawn Guo wrote:
+- cd-gpios : Specify GPIOs for card detection
+- wp-gpios : Specify GPIOs for write
On Wed, 27 Jul 2011 15:03:30 +0100
Jamie Iles ja...@jamieiles.com wrote:
diff --git a/Documentation/devicetree/bindings/mtd/gpio-nand.txt
b/Documentation/devicetree/bindings/mtd/gpio-nand.txt
new file mode 100644
index 000..98cb152
--- /dev/null
+++
On Mon, 1 Aug 2011 15:02:54 +0100
Jamie Iles ja...@jamieiles.com wrote:
diff --git a/Documentation/devicetree/bindings/mtd/gpio-control-nand.txt
b/Documentation/devicetree/bindings/mtd/gpio-control-nand.txt
new file mode 100644
index 000..2dc52de
--- /dev/null
+++
On Mon, 1 Aug 2011 20:33:16 +0100
Jamie Iles ja...@jamieiles.com wrote:
OK, fair points. I'm not sure what to say about endianness though.
Host byte order accesses are used in the driver so can I just specify
this? We could add a property later to support endianess swapping, but
I don't
On Mon, 1 Aug 2011 21:25:36 +0100
Jamie Iles ja...@jamieiles.com wrote:
On Mon, Aug 01, 2011 at 03:12:09PM -0500, Scott Wood wrote:
It looks like the code uses a little-endian accessor (readw) in a couple
places. The instance in gpio_nand_readbuf16() should never be reached
since the NAND
On 08/04/2011 05:36 AM, David Brown wrote:
Add uncached mappings from devicetree nodes similar to regular io
mappings.
SPARC is coherent, so there this call is the same as regular of_iomap.
Cc: David Millerda...@davemloft.net
Signed-off-by: David Browndav...@codeaurora.org
---
v2 - Add
On 08/05/2011 01:36 PM, Matt Sealey wrote:
On Fri, Aug 5, 2011 at 2:07 AM, David Brown dav...@codeaurora.org wrote:
On Thu, Aug 04, 2011 at 06:07:15PM -0500, Matt Sealey wrote:
Hi Grant, Shawn,
On Mon, Jul 25, 2011 at 3:46 PM, Grant Likely grant.lik...@secretlab.ca
wrote:
This could get
On 08/05/2011 04:29 PM, Matt Sealey wrote:
On Fri, Aug 5, 2011 at 3:36 PM, David Brown dav...@codeaurora.org wrote:
On Fri, Aug 05, 2011 at 03:26:29PM -0500, Scott Wood wrote:
Yes, it puts the onus of the work on the firmware guys, but they're
the ones writing the device trees
On 08/09/2011 12:47 PM, Cousson, Benoit wrote:
On 8/9/2011 7:23 PM, Grant Likely wrote:
There is no analogous mechanism for _byname in the device tree. The
DT binding for a device must explicitly state what order the register
ranges are in. The driver will need to be adapted.
That seems
On 08/09/2011 02:49 PM, Wolfgang Grandegger wrote:
Yes. The doc for the bindings we speak about
http://lxr.linux.no/#linux+v3.0.1/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
sneaked into the kernel without been presented on any mailing list and
without the corresponding
On 08/09/2011 02:32 PM, Wolfgang Grandegger wrote:
On 08/09/2011 08:17 PM, Scott Wood wrote:
On 08/09/2011 09:43 AM, Robin Holt wrote:
In working with the socketcan developers, we have come to the conclusion
the fsl-flexcan device tree bindings need to be cleaned up.
The driver does
On 08/09/2011 04:44 PM, Cousson, Benoit wrote:
OK, so what about extending the reg attribute to be a reg node?
dev {
reg {
name = foo_wrapper;
start = 0x1;
end = 0x200;
}
reg {
name = foo;
start = 0x2;
end = 0x200;
On 08/09/2011 10:12 AM, Jamie Iles wrote:
+Optional properties:
+- bank-width : Width (in bytes) of the device. If not present, the width
+ defaults to 8 bits.
in bytes versus defaults to 8 bits...
+- chip-delay : chip dependent delay for transferring data from array to
+ read registers
On 08/09/2011 08:52 PM, David Gibson wrote:
Of course, the problem with reg-names is that it will be ignored by
older OSes, and so 'reg' must still be in the correct order. In which
case you could argue it's more sensible to just have a static place to
name mapping in the Linux driver.
I
On 08/10/2011 11:27 AM, Robin Holt wrote:
-CPI Clock- Can Protocol Interface Clock
- This CLK_SRC bit of CTRL(control register) selects the clock source to
- the CAN Protocol Interface(CPI) to be either the peripheral clock
- (driven by the PLL) or the crystal oscillator clock. The
On 08/10/2011 12:19 PM, Robin Holt wrote:
On Wed, Aug 10, 2011 at 11:56:28AM -0500, Scott Wood wrote:
On 08/10/2011 11:27 AM, Robin Holt wrote:
-CPI Clock- Can Protocol Interface Clock
- This CLK_SRC bit of CTRL(control register) selects the clock source to
- the CAN Protocol Interface
On 09/07/2011 11:20 AM, Tabi Timur-B04825 wrote:
The problem is that both offset and irq_index are being incremented in
the loop, and cascade_data-index is set to the sum of the two.
Perhaps you meant this:
err = fsl_msi_setup_hwirq(msi, dev, offset, j);
That's not right
On 09/20/2011 03:04 AM, David Gibson wrote:
So, there are basically two approaches to macro or function support.
A) Functions
We allow definition of functions with parameters. These are stored
in some kind of parse tree representation in a symbol table. Instead
of producing a
On 09/27/2011 07:29 PM, David Gibson wrote:
On Tue, Sep 20, 2011 at 12:35:29PM -0500, Scott Wood wrote:
Another disadvantage of any approach that tries to separate macros from
the underlying language is that you can't have anything be conditional
on an expression that the macro layer doesn't
On 09/28/2011 03:15 AM, Cousson, Benoit wrote:
On 9/27/2011 7:40 AM, Nayak, Rajendra wrote:
On Monday 26 September 2011 10:20 PM, Benoit Cousson wrote:
+Required properties:
+- compatible:
+ - ti,omap2-gpio for OMAP2 and OMAP3 controllers
Would it be more readable to have
ti,omap2-gpio
On 09/28/2011 03:57 PM, Cousson, Benoit wrote:
On 9/28/2011 8:23 PM, Scott Wood wrote:
What does the id mean, in relation to the actual hardware?
It's true that the description is not super meaningful...
This is the HW instance number. We have 6 gpios, named gpio1 to gpio6,
but the pin
On 11/07/2011 02:09 PM, Robert Sciuk wrote:
In my continuing saga of dev/tree driver development, I have a problem which
might be obvious to those who have more experience in such matters.
I'm a bit perplexed on the tree nodes for the localbus/simplebus
nodes for my FPGA. CS0 is reserved
On 12/05/2011 04:11 PM, Simon Glass wrote:
Hi Stephen,
On Mon, Dec 5, 2011 at 2:07 PM, Stephen Warren swar...@nvidia.com wrote:
My point is that there are probably .dts files using ok instead of
okay or the kernel wouldn't support ok. People will probably want to
use those with U-Boot
On 01/23/2012 02:56 AM, Heiko Schocher wrote:
diff --git a/Documentation/devicetree/bindings/arm/davinci/nand.txt
b/Documentation/devicetree/bindings/arm/davinci/nand.txt
new file mode 100644
index 000..7e8d6db
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/davinci/nand.txt
On 01/24/2012 01:23 AM, Heiko Schocher wrote:
Hello Scott,
Scott Wood wrote:
On 01/23/2012 02:56 AM, Heiko Schocher wrote:
diff --git a/Documentation/devicetree/bindings/arm/davinci/nand.txt
b/Documentation/devicetree/bindings/arm/davinci/nand.txt
new file mode 100644
index 000
On 01/25/2012 01:09 AM, Heiko Schocher wrote:
Scott Wood wrote:
I found the following used options:
ecc_mode:
NAND_ECC_NONE
NAND_ECC_SOFT
NAND_ECC_HW
NAND_ECC_HW_SYNDROME
bbt_options:
NAND_BBT_USE_FLASH
ecc_bits:
1
4
options:
NAND_BUSWIDTH_16
Do all of these properties
On 01/27/2012 12:40 AM, Heiko Schocher wrote:
Hello Scott,
Scott Wood wrote:
On 01/25/2012 01:09 AM, Heiko Schocher wrote:
ecc_mode:
NAND_ECC_NONE
NAND_ECC_SOFT
NAND_ECC_HW
NAND_ECC_HW_SYNDROME
ti,davinci-nand-ecc-mode = none, soft, hw or hw_syndrome
OK.
bbt_options
On 03/15/2012 08:30 PM, Poonam Aggrwal wrote:
From: Poonam Aggrwal poonam.aggr...@freescale.com
This TDM controller is available in various Freescale SOCs like MPC8315,
P1020,
P1022, P1010.
Signed-off-by: Sandeep Singh sand...@freescale.com
Signed-off-by: Poonam Aggrwal
On 03/17/2012 11:07 AM, Tabi Timur-B04825 wrote:
On Sat, Mar 17, 2012 at 2:33 AM, Aggrwal Poonam-B10812
b10...@freescale.com wrote:
+ compatible = fsl,p1010-tdm, fsl,mpc8315-tdm;
+ reg = 0x16000 0x200 0x2c000 0x2000;
+ clock-frequency = 0;
Show a real
On 03/19/2012 12:32 PM, Timur Tabi wrote:
Scott Wood wrote:
Scott, are you suggesting that Poonam put a non-zero number in the DTS
for clock-frequency? If so, then I don't think that's a good idea, if
U-Boot will always override it.
This is a device tree binding document, not U-Boot
On 03/24/2012 08:14 AM, Jamie Lentin wrote:
Use devicetree to define NAND partitions. Use D-link partition scheme by
default, to be vaguely compatible with their userland.
Signed-off-by: Jamie Lentin j...@lentin.co.uk
---
arch/arm/boot/dts/kirkwood-dns320.dts | 35
On 03/26/2012 11:20 AM, Jason Cooper wrote:
On Mon, Mar 26, 2012 at 10:53:29AM -0500, Scott Wood wrote:
On 03/24/2012 08:14 AM, Jamie Lentin wrote:
Use devicetree to define NAND partitions. Use D-link partition scheme by
default, to be vaguely compatible with their userland.
Signed-off
On 04/13/2012 01:29 PM, Simon Glass wrote:
Add a NAND controller along with a bindings file for review.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Update NAND binding to add nvidia, prefix
arch/arm/dts/tegra20.dtsi |6 ++
On 04/13/2012 02:01 PM, Simon Glass wrote:
Hi Scott,
On Fri, Apr 13, 2012 at 11:43 AM, Scott Wood scottw...@freescale.com wrote:
On 04/13/2012 01:29 PM, Simon Glass wrote:
Add a NAND controller along with a bindings file for review.
Signed-off-by: Simon Glass s...@chromium.org
On 04/13/2012 04:05 PM, Stephen Warren wrote:
On 04/13/2012 12:29 PM, Simon Glass wrote:
Add a NAND controller along with a bindings file for review.
Signed-off-by: Simon Glasss...@chromium.org
+++ b/doc/device-tree-bindings/nand/nvidia-nand.txt
I'd prefer this be called
On 04/13/2012 03:58 PM, Stephen Warren wrote:
On 04/13/2012 12:43 PM, Scott Wood wrote:
On 04/13/2012 01:29 PM, Simon Glass wrote:
Add a NAND controller along with a bindings file for review.
Signed-off-by: Simon Glasss...@chromium.org
+++ b/doc/device-tree-bindings/nand/nvidia-nand.txt
On 04/13/2012 04:22 PM, Stephen Warren wrote:
On 04/13/2012 03:21 PM, Scott Wood wrote:
On 04/13/2012 03:58 PM, Stephen Warren wrote:
On 04/13/2012 12:43 PM, Scott Wood wrote:
On 04/13/2012 01:29 PM, Simon Glass wrote:
Add a NAND controller along with a bindings file for review.
Signed-off
On Thu, Mar 15, 2012 at 11:31:02PM -, chenhui zhao wrote:
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt
b/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt
index 07256b7..d296e88 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt
+++
On 04/17/2012 01:33 PM, Simon Glass wrote:
Hi Stephen,
On Fri, Apr 13, 2012 at 2:05 PM, Stephen Warren swar...@wwwdotorg.org wrote:
On 04/13/2012 12:29 PM, Simon Glass wrote:
+nand-controller@0x70008000 {
+ compatible = nvidia,tegra20-nand;
+ wp-gpios = gpio 59 0;/*
On 04/17/2012 01:44 PM, Simon Glass wrote:
Hi,
On Tue, Apr 17, 2012 at 11:38 AM, Scott Wood scottw...@freescale.com wrote:
On 04/17/2012 01:33 PM, Simon Glass wrote:
Hi Stephen,
On Fri, Apr 13, 2012 at 2:05 PM, Stephen Warren swar...@wwwdotorg.org
wrote:
On 04/13/2012 12:29 PM, Simon
On 04/17/2012 01:50 PM, Simon Glass wrote:
diff --git a/doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt
b/doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt
new file mode 100644
index 000..2484556
--- /dev/null
+++ b/doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt
@@
On 04/17/2012 03:18 PM, Simon Glass wrote:
+Jim, who wrote the driver originally
Hi Scott,
On Tue, Apr 17, 2012 at 12:06 PM, Scott Wood scottw...@freescale.com wrote:
+ - nvidia,page-data-bytes : Number of bytes in the data area
+ - nvidia,page-spare-bytes : Number of bytes in spare area
On 04/17/2012 03:36 PM, Simon Glass wrote:
Hi Scott,
On Tue, Apr 17, 2012 at 1:31 PM, Scott Wood scottw...@freescale.com wrote:
On 04/17/2012 03:18 PM, Simon Glass wrote:
On Tue, Apr 17, 2012 at 12:06 PM, Scott Wood scottw...@freescale.com
wrote:
Doesn't the number of cells depend
On 07/10/2012 05:53 PM, Simon Glass wrote:
Hi Scott,
On Tue, Jul 10, 2012 at 11:23 PM, Scott Wood scottw...@freescale.com
mailto:scottw...@freescale.com wrote:
Also note that even non-boolean properties can mean something different
when absent. Sometimes this is a default value
probed by the first driver, because
nothing else in the match struct is looked at if there's a compatible
match.
Signed-off-by: Scott Wood scottw...@freescale.com
---
drivers/of/base.c | 44
1 file changed, 32 insertions(+), 12 deletions(-)
diff --git
On 07/17/2012 09:38 PM, Rob Herring wrote:
On 07/17/2012 08:11 PM, Scott Wood wrote:
Commit 107a84e61cdd3406c842a0e4be7efffd3a05dba6 (of: match by compatible
property first) breaks the gianfar ethernet driver found on various
Freescale PPC chips.
You do know this is reverted, right?
No, I
On 07/22/2012 08:56 PM, Rob Herring wrote:
On 07/18/2012 11:04 AM, Scott Wood wrote:
On 07/17/2012 09:38 PM, Rob Herring wrote:
On 07/17/2012 08:11 PM, Scott Wood wrote:
Commit 107a84e61cdd3406c842a0e4be7efffd3a05dba6 (of: match by compatible
property first) breaks the gianfar ethernet driver
On 07/30/2012 01:53 AM, Simon Glass wrote:
Add a flash node to handle the NAND, including memory timings and
page / block size information.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Update NAND binding to add nvidia, prefix
Changes in v3:
- Add reg property for
On 07/30/2012 01:53 AM, Simon Glass wrote:
diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi
index f95be58..d936b1e 100644
--- a/arch/arm/dts/tegra20.dtsi
+++ b/arch/arm/dts/tegra20.dtsi
@@ -204,4 +204,11 @@
compatible = nvidia,tegra20-kbc;
reg =
On 08/10/2012 12:53 AM, dongsheng.w...@freescale.com wrote:
From: Wang Dongsheng dongsheng.w...@freescale.com
Add a description of the OPEN-PIC global timer in the OPEN-PIC document.
Moidfy mpic-timer document. 1.Add a TFRR register region. This register
is written by software to report
On 08/13/2012 01:17 AM, Li Yang-R58472 wrote:
-Original Message-
From: Wang Dongsheng-B40534
Sent: Monday, August 13, 2012 1:54 PM
To: Wood Scott-B07421
Cc: b...@kernel.crashing.org; pau...@samba.org; linuxppc-
d...@lists.ozlabs.org; Gala Kumar-B11780; Li Yang-R58472
Subject:
On 08/13/2012 12:40 AM, Wang Dongsheng-B40534 wrote:
diff --git a/Documentation/devicetree/bindings/open-pic.txt
b/Documentation/devicetree/bindings/open-pic.txt
index 909a902..045c2e9 100644
--- a/Documentation/devicetree/bindings/open-pic.txt
+++
On 08/13/2012 09:40 PM, Wang Dongsheng-B40534 wrote:
+Example 2:
+
+ timer: timer@010f0 {
+ compatible = open-pic,global-timer;
+ device_type = open-pic;
+ reg = 0x010f0 4 0x01100 0x100;
+ interrupts = 0 0 3 0
+ 1 0 3 0
+
On 08/20/2012 03:36 AM, Srinivas KANDAGATLA wrote:
On 17/08/12 16:36, Timur Tabi wrote:
Srinivas KANDAGATLA wrote:
If you know in advance that device on that SOC is broken, then I guess
Fail/Failed can be used in status property.
One user of this flag in kernel device trees is
On 08/20/2012 11:01 AM, Timur Tabi wrote:
Scott Wood wrote:
The distinction between disabled and fail is useful when the OS
knows how to enable a node (e.g. by manipulating muxing).
So a node that is marked as status=fail is not necessarily an
unrecoverable failure?
No, it's disabled
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