Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
Cc: devicetree-discuss@lists.ozlabs.org
---
Documentation/devicetree/bindings/dma/mv-xor.txt | 40 +++
drivers/dma/mv_xor.c | 57 --
2 files changed, 93 insertions
+-
And this one don't appear to belong in this commit, do they?
Thomas
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/Kconfig in patch 2/7,
so I think it shouldn't be added here in patch 3/7.
Thomas
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. The
previous clock-frequency property was not documented, but maybe the new
clocks property should.
Thomas
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of coherency here:
core_clk vs. clk_gate
marvell,dove-core-clocks vs. marvell,dove-clock-gating
Maybe:
core_clk / gate_clk
marvell,dove-core-clocks / marvell,dove-gating-clocks
Thomas
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to make use of these clk gates.
I had a quick look and made a few comments, but overall, it looks
really great. I really hope we can get this in 3.8.
Thomas
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.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
Cc: devicetree-discuss@lists.ozlabs.org
---
Documentation/devicetree/bindings/dma/mv-xor.txt | 40 +++
drivers/dma/mv_xor.c | 58 --
2 files changed, 94 insertions
the coherency fabric in order to provide
coherency with I/O.
Thanks to the coherency unit, we have an almost DMA coherent
architecture (see the HW I/O coherency patches from Grégory for
details).
Thomas
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material.
Thanks,
Gregory CLEMENT (2):
arm: mvebu: add RTC support for Armada 370 and Armada XP
rtc: rtc-mv: Add the device tree binding documentation
Would you mind adding a patch that updates the mvebu_defconfig to
include the RTC driver by default?
Thanks!
Thomas
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= okay here?
Thomas
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comments,
Thomas
[1] that I hope to extend to cover previous Marvell SoCs as well, they
work basically the same way
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, thanks for clarifying what the best practice is. This device being
internal to the SoC and having no dependency on external components, it
is indeed always available.
Thanks again for the clarification!
Thomas
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for example has a RTC on I2C, so maybe it'll
want to disable the on-SoC RTC.
Best regards,
Thomas
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solution.
Best regards,
Thomas
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Now that we have a 7-segment display driver in the kernel, use it on
the Marvell Armada XP DB evaluation board.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/boot/dts/armada-xp-db.dts |5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts
Now that we have a 7-segment display driver in the kernel, use it on
the Marvell Armada 370 DB evaluation board.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/boot/dts/armada-370-db.dts |5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot
decoder using GPIOs.
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni thomas.petazz...@free-electrons.com
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed as is without any
+ * warranty of any kind, whether express
,
with a convenient user-space interface.
Not having a kernel driver means that gazillions of applications
re-invent the same piece of code over and over again, have to hardcode
the GPIO numbers for a given piece of hardware, while the kernel
abstract all of this very nicely.
Thanks,
Thomas
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. Patches discarded.
Thanks,
Thomas
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On Mon, 7 Jan 2013 18:40:22 +0100, Thomas Petazzoni wrote:
Not having a kernel driver means that gazillions of applications
re-invent the same piece of code over and over again, have to hardcode
the GPIO numbers for a given piece of hardware, while the kernel
abstract all
sysfs files to output text or numbers on a 7-segment display,
while it could all be done using libusb from userspace? Seems like back
in 2008 you Signed-off-by on the patch adding this driver :-)
Thomas
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me, which I knew would not work :-)
As Russell points out, if you want this in the kernel, it needs to have
a good userspace api, and that needs a lot more work than just a single
sysfs file.
Ok, thanks.
Thomas
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more time on this.
Thanks,
Thomas
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much. As I said, for Tegra everything still
works without, so I didn't see a reason to add needless code.
Ok, thanks!
Thomas
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of the two physical ports is a
combined USB / eSATA port, but I don't think this makes any difference
at the software level.
I don't have the OpenBlocks AX3-4 with me right now, but I could
probably make a test on Friday.
Best regards,
Thomas
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.
+ set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
Incorrect indentation for this line.
Thomas
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will keep it.
ACK, fine. Didn't know about this specific point of the CodingStyle.
Best regards,
Thomas
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on the PCIe
bus. There is nothing like a PCIe port that uses a USB port, that
doesn't make sense.
So, IMHO, if OpenBlocks uses third USB port to connect some PCIe
controller, we should activate it in the dts file.
What do you think?
No, see above.
Thomas
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devm_request_and_ioremap() instead, in order to get
automatic unmap on error and in the -remove() path?
But maybe it won't work because this memory range is claimed both by
the MDIO driver and the Ethernet driver itself. In that case, you could
use devm_ioremap().
Best regards,
Thomas
--
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. No
functionnal code change introduced.
Signed-off-by: Florian Fainelli flor...@openwrt.org
Acked-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
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);
+ free_irq(dev-err_interrupt, dev);
free_irq() not needed since the IRQ handler is registered with
devm_request_irq().
mdiobus_unregister(bus);
kfree(bus-irq);
mdiobus_free(bus);
Thanks,
Thomas
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;
+ }
+
+ dev-err_interrupt = platform_get_irq(pdev, 0);
+ }
I think you can do a devm_ioremap() and a platform_get_irq() in both
cases here, and therefore keep the code common between the DT case and
the !DT case.
Thanks,
Thomas
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of this
MV643XX_ETH_SHARED_NAME driver, no?
Thanks,
Thomas
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be good to have followed patches that
progressively get rid of the shared driver thing, as it will help in
bringing a proper DT binding in the mv643xx_eth driver. But it
certainly doesn't need to be part of this specific patch.
Thanks,
Thomas
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the DT memory node
according to the ATAG_MEM passed by the bootloader.
Best regards,
Thomas
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that is present in the
Mirabox. But not on other boards.
Of course, it doesn't make sense to have drivers for pluggable devices
like PCIe devices that are not soldered, USB devices and things like
that. But for all the rest, I would say it should be in the defconfig.
Best regards,
Thomas
--
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Dear Thierry Reding,
On Wed, 9 Jan 2013 21:43:06 +0100, Thierry Reding wrote:
When using deferred driver probing, PCI host controller drivers may
actually require this function after the init stage.
Signed-off-by: Thierry Reding thierry.red...@avionic-design.de
Tested-by: Thomas Petazzoni
patches, that have already
gone through multiple iterations, could be merged.
Thanks,
Thomas
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suited to do this if you want to and have the time.
And I'll be more than happy to test your patches in the context of the
Marvell PCIe driver.
Best regards,
Thomas
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the Marvell PCIe driver) are putting our drivers in drivers/pci/host/,
in agreement with the PCI maintainers.
Thomas
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anyway have to construct this pciX.Y
string. But if you feel like using pcie@X,Y for the reg-names is
better even if I still need to construct the pcieX.Y string, then I
will be perfectly ok with making this change.
Best regards,
Thomas
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Thomas
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that in the case of my driver, the @X,Y represent the port and
lane of the PCIe interface. Not sure if it is correct, I can change the
names to whatever is appropriate, those names aren't used anywhere in
the driver.
Best regards,
Thomas
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-EPROBE_DEFER when it can't find its PHY so that its
-probe() operation gets called once again by the kernel when other
drivers (including mvmdio) have been probed.
Best regards,
Thomas
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,
+ struct device_node *node)
+{
+ return NULL;
+}
#endif /* CONFIG_OF_ADDRESS */
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)-flags instead of res-flags. If you don't do
that, then passing foobar as the 'res' parameter causes some
compilation failure because foobar-res is not valid, while
(foobar)-res is.
Best regards,
Thomas
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of_pci_get_devfn() function
of/pci: Add of_pci_parse_bus_range() function
Thomas Petazzoni (14):
pci: infrastructure to add drivers in drivers/pci/host
arm: pci: add a align_resource hook
clk: mvebu: create parent-child relation for PCIe clocks on Armada
370
clk: mvebu: add more PCIe
-by: Liviu Dudau liviu.du...@arm.com
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
Compared to the v2 sent by Andrew Murray, Thomas Petazzoni did:
* Add a memset() on the struct of_pci_range_iter when starting the
for loop in for_each_pci_range(). Otherwise
From: Thierry Reding thierry.red...@avionic-design.de
This function can be used to parse the device and function number from a
standard 5-cell PCI resource. PCI_SLOT() and PCI_FUNC() can be used on
the returned value obtain the device and function numbers respectively.
Signed-off-by: Thierry
From: Thierry Reding thierry.red...@avionic-design.de
This function can be used to parse a bus-range property as specified by
device nodes representing PCI bridges.
Signed-off-by: Thierry Reding thierry.red...@avionic-design.de
---
drivers/of/of_pci.c| 25 +
As agreed by the community, PCI host drivers will now be stored in
drivers/pci/host. This commit adds this directory and the related
Kconfig/Makefile changes to allow new drivers to be added in this
directory.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
drivers/pci
The Armada 370 has two gatable clocks for each PCIe interface, and we
want both of them to be enabled. We therefore make one of the two
clocks a child of the other, as we did for the sataX and sataXlnk
clocks on Armada XP.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
Cc
Now that the PCIe driver for mvebu has been integrated and all its
relevant dependencies, we can mark the ARCH_MVEBU platform has
MIGHT_HAVE_PCI, which allows to select the PCI bus support if needed.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/mach-mvebu
-mvebu/addr-map.c.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
.../devicetree/bindings/pci/mvebu-pci.txt | 201 +
drivers/pci/host/Kconfig |4 +
drivers/pci/host/Makefile |4 +
drivers/pci/host/pci
The Armada 370 SoC has two 1x PCIe 2.0 interfaces, so we add the
necessary Device Tree informations to make these interfaces availabel.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/boot/dts/armada-370.dtsi | 45 +
1 file
informations to make those PCIe interfaces
usable.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/boot/dts/armada-xp-mv78230.dtsi | 98 +
arch/arm/boot/dts/armada-xp-mv78260.dtsi | 113
arch/arm/boot/dts/armada-xp-mv78460.dtsi
The PlatHome OpenBlocks AX3-4 has an internal mini-PCIe slot that can
be used to plug mini-PCIe devices. We therefore enable the PCIe
interface that corresponds to this slot.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
The Globalscale Mirabox platform uses one PCIe interface for an
available mini-PCIe slot, and the other PCIe interface for an internal
USB 3.0 controller. We add the necessary Device Tree informations to
enable those two interfaces.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free
The Marvell evaluation board (DB) for the Armada XP SoC has 6
physicals full-size PCIe slots, so we enable the corresponding PCIe
interfaces in the Device Tree.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/boot/dts/armada-xp-db.dts | 33
The Marvell Armada XP GP board has 3 physical full-size PCIe slots, so
we enable the corresponding PCIe interfaces in the Device Tree.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/boot/dts/armada-xp-gp.dts | 21 +
1 file changed, 21
-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/configs/mvebu_defconfig |3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig
index 2ec8119..071a5b1 100644
--- a/arch/arm/configs/mvebu_defconfig
+++ b/arch
,
Thomas
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area that would be mapped at a
different address (above 4 GB).
However, I'm unsure why 0xC000 was chosen. Why not 0xD000,
where the internal registers currently start?
Best regards,
Thomas
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at a
different address (above 4 GB).
So why not map the whole SDRAM above 4GB physical address?
That's a good question. The problem is most likely that this would
require to synchronize with U-Boot modifications, which is not easy to
achieve.
Thomas
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can't do it early enough to preserve the earlyprintk
functionality. Maybe you have suggestions on how to achieve that?
Best regards,
Thomas
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.
Best regards,
Thomas
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on this patch, so if any
rework of this OF patch needs to be done, it'd be great to know it
sooner rather than later.
Thanks!
Thomas
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objection. I find it to be a little more encapsulated and therefore
easier to work with, but that's possibly just a matter of taste.
I don't have a strong opinion on this. Andrew, what do you think?
Thomas
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: enhance driver to support SMI error/done interrupts
mv643xx_eth: convert to use the Marvell Orion MDIO driver
For the entire series:
Tested-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
tested on:
* Armada XP DB, DT-based, which uses the mvneta driver. It is affected
by the 3 first
== IORESOURCE_MEM) {
[...]
Thomas
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support for parsing PCI DT ranges property
Thierry Reding (2):
of/pci: Add of_pci_get_devfn() function
of/pci: Add of_pci_parse_bus_range() function
Thomas Petazzoni (14):
pci: infrastructure to add drivers in drivers/pci/host
arm: pci: add a align_resource hook
clk: mvebu: create
-by: Liviu Dudau liviu.du...@arm.com
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
Compared to the v2 sent by Andrew Murray, Thomas Petazzoni did:
* Add a memset() on the struct of_pci_range_iter when starting the
for loop in for_each_pci_range(). Otherwise
From: Thierry Reding thierry.red...@avionic-design.de
This function can be used to parse the device and function number from a
standard 5-cell PCI resource. PCI_SLOT() and PCI_FUNC() can be used on
the returned value obtain the device and function numbers respectively.
Signed-off-by: Thierry
From: Thierry Reding thierry.red...@avionic-design.de
This function can be used to parse a bus-range property as specified by
device nodes representing PCI bridges.
Signed-off-by: Thierry Reding thierry.red...@avionic-design.de
---
drivers/of/of_pci.c| 25 +
As agreed by the community, PCI host drivers will now be stored in
drivers/pci/host. This commit adds this directory and the related
Kconfig/Makefile changes to allow new drivers to be added in this
directory.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
drivers/pci
The Armada 370 has two gatable clocks for each PCIe interface, and we
want both of them to be enabled. We therefore make one of the two
clocks a child of the other, as we did for the sataX and sataXlnk
clocks on Armada XP.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
Cc
for those PCIe interfaces.
It also changes the name of the previously existing PCIe gatable
clocks, in order to match the naming using the datasheets.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
drivers/clk/mvebu/clk-gating-ctrl.c | 14 ++
1 file changed, 10
Now that the PCIe driver for mvebu has been integrated and all its
relevant dependencies, we can mark the ARCH_MVEBU platform has
MIGHT_HAVE_PCI, which allows to select the PCI bus support if needed.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/mach-mvebu
-mvebu/addr-map.c.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
.../devicetree/bindings/pci/mvebu-pci.txt | 201 +
drivers/pci/host/Kconfig |4 +
drivers/pci/host/Makefile |4 +
drivers/pci/host/pci
The Armada 370 SoC has two 1x PCIe 2.0 interfaces, so we add the
necessary Device Tree informations to make these interfaces availabel.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/boot/dts/armada-370.dtsi | 45 +
1 file
The PlatHome OpenBlocks AX3-4 has an internal mini-PCIe slot that can
be used to plug mini-PCIe devices. We therefore enable the PCIe
interface that corresponds to this slot.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
informations to make those PCIe interfaces
usable.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/boot/dts/armada-xp-mv78230.dtsi | 98 +
arch/arm/boot/dts/armada-xp-mv78260.dtsi | 113
arch/arm/boot/dts/armada-xp-mv78460.dtsi
The Globalscale Mirabox platform uses one PCIe interface for an
available mini-PCIe slot, and the other PCIe interface for an internal
USB 3.0 controller. We add the necessary Device Tree informations to
enable those two interfaces.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free
The Marvell evaluation board (DB) for the Armada XP SoC has 6
physicals full-size PCIe slots, so we enable the corresponding PCIe
interfaces in the Device Tree.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/boot/dts/armada-xp-db.dts | 33
The Marvell evaluation board (DB) for the Armada 370 SoC has 2
physical full-size PCIe slots, so we enable the corresponding PCIe
interfaces in the Device Tree.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/boot/dts/armada-370-db.dts | 17 +
1
-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/configs/mvebu_defconfig |3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig
index 2ec8119..071a5b1 100644
--- a/arch/arm/configs/mvebu_defconfig
+++ b/arch
The Marvell Armada XP GP board has 3 physical full-size PCIe slots, so
we enable the corresponding PCIe interfaces in the Device Tree.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/boot/dts/armada-xp-gp.dts | 21 +
1 file changed, 21
: Introduce new MSI chip infrastructure
Thomas Petazzoni (10):
arm: mvebu: move L2 cache initialization in init_early()
irqchip: move IRQ driver for Armada 370/XP
irqchip: armada-370-xp: move IRQ handler to avoid forward declaration
irqchip: armada-370-xp: slightly cleanup irq controller
In preparation for moving the IRQ controller driver to
drivers/irqchip/, we don't want the IRQ controller driver to be
responsible for initializing the L2 cache. Instead, let's initialize
the L2 cache at the init_early() level, like mach-exynos/common.c is
doing.
Signed-off-by: Thomas Petazzoni
armada_370_xp_mpic_of_init(). That will be done in the next commit.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/mach-mvebu/Makefile |2 +-
arch/arm/mach-mvebu/armada-370-xp.c|4 ++--
drivers/irqchip/Makefile
.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
drivers/irqchip/irq-armada-370-xp.c | 83 +--
1 file changed, 40 insertions(+), 43 deletions(-)
diff --git a/drivers/irqchip/irq-armada-370-xp.c
b/drivers/irqchip/irq-armada-370-xp.c
index
cleanup first.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
drivers/irqchip/irq-armada-370-xp.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/irqchip/irq-armada-370-xp.c
b/drivers/irqchip/irq-armada-370-xp.c
index 1115bf8
The mpic alias is already defined in the common armada-370-xp.dtsi, so
there's no need to repeat it at the armada-xp.dtsi and armada-370.dtsi
level. Moreover, we're going to slightly change how the interrupt
controller is declared in the common armada-370-xp.dtsi file.
Signed-off-by: Thomas
, and are therefore
notified using IRQ1 of the main interrupt controller.
The Device Tree binding documentation for the armada-370-xp driver is
also updated in the process.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
.../devicetree/bindings/arm/armada-370-xp-mpic.txt | 39
is updated in the
following patch, when the MSI interrupt support is added to the
armada-370-xp irqchip driver.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/boot/dts/armada-370-xp.dtsi |9 ++---
drivers/irqchip/irq-armada-370-xp.c |9 +++--
2 files
-
specific MSI functions (arch_setup_msi_irq(), arch_teardown_msi_irq()
and arch_msi_check_device()) which check if a PCI device's bus has an
attached MSI chip and forward the call appropriately.
Signed-off-by: Thierry Reding thierry.red...@avionic-design.de
Signed-off-by: Thomas Petazzoni thomas.petazz
this, the PCIe driver registers the -setup_irq() and
-teardown_irq() callbacks using the newly introduced msi_chip
infrastructure, which allows the kernel PCI core to use the MSI
functionality.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
.../devicetree/bindings/pci/mvebu
Now that the Marvell EBU PCIe driver supports MSI, we can adjust the
Device Tree for the Armada 370 and Armada XP SoCs so that the PCIe
controller nodes point to the MSI interrupt controller using the
'msi-parent' property.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
Now that MSI support is available, both in the IRQ controller driver
and in the PCIe driver, let's enable it in the mvebu_defconfig used
for Armada 370/XP platforms.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/configs/mvebu_defconfig |1 +
1 file changed
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