Hi Christian, Gustavo,
Thanks for these patches.
On 1 June 2016 at 20:55, Gustavo Padovan wrote:
> 2016-06-01 Christian König :
>
>> From: Gustavo Padovan
>>
>> struct fence_collection inherits from struct fence and carries a
>> collection of fences that needs to be waited together.
>>
>> It
Hi Lin,
This patch include the two features as following:
- Monitor the ddr load
- Control the ddr's clock with ondemand governor based on load
The "Monitor the ddr load" has the specific the address in SoC.
Namely, it is separate the module.
So, I implemented the devfreq-event framework[1]
With 6e86d58be3, I get working X. With 0955c1250e ("drm/crtc: take
references to connectors used in a modeset. (v2)"), startx produces a
kernel oops and a blank screen.
4.7-rc1 with 0955c1250e reverted also works, which seems definitive.
The oops is:
[ 212.149973] nouveau :02:00.0: DRM:
On Wed, Jun 1, 2016 at 6:35 PM, Lin Huang wrote:
> there is dfi controller on rk3399 platform, it can monitor
> ddr load, register this controller to devfreq framework, and
> default to use simple_ondeamnd policy, and do ddr frequency
> scaling base on this result.
>
> Signed-off-by: Lin Huang
>
On Wed, Jun 01, 2016 at 06:51:51PM +0200, Peter Wu wrote:
> On Tue, May 31, 2016 at 02:20:26PM +0200, Lukas Wunner wrote:
> > On Mon, May 30, 2016 at 06:13:51PM +0200, Peter Wu wrote:
> > > Do you have any suggestions for the case where the pcieport driver
> > > refuses to put the bridge in D3
On Wed, Jun 01, 2016 at 12:28:47PM +0300, Mika Westerberg wrote:
> On Tue, May 31, 2016 at 01:02:31PM +0200, Peter Wu wrote:
> > On Tue, May 31, 2016 at 11:43:56AM +0300, Mika Westerberg wrote:
> > > On Mon, May 30, 2016 at 06:13:51PM +0200, Peter Wu wrote:
> > > > Do you have any suggestions for
On Tue, May 31, 2016 at 02:20:26PM +0200, Lukas Wunner wrote:
> On Mon, May 30, 2016 at 06:13:51PM +0200, Peter Wu wrote:
> > Do you have any suggestions for the case where the pcieport driver
> > refuses to put the bridge in D3 (because the BIOS is too old)? In that
> > case the nouveau driver
Hi Dave,
this tag contains support for pixel clock polarity configuration,
LVDS panel EDID reading via DDC, video mode selection via native-mode
DT property, UYVY/YUYV plane support, and some cleanups.
regards
Philipp
The following changes since commit 1a695a905c18548062509178b98bc91e67510864:
Hi Dave,
this tag contains two fixes, one each for an oversight in the DPI and
DSI driver, respectively.
regards
Philipp
The following changes since commit 1a695a905c18548062509178b98bc91e67510864:
Linux 4.7-rc1 (2016-05-29 09:29:24 -0700)
are available in the git repository at:
From: Monk Liu
should fist halt engine, and then doing the register
programing, and later unhalt engine, and finally run
ring_test.
this help fix reloading driver hang issue of SDMA
ring
original sequence is wrong for it programing engine
after unhalt, which will lead to
From: Monk Liu
This help fix reloading driver hang issue of SDMA
ring
Signed-off-by: Monk Liu
Reviewed-by: Alex Deucher
Reviewed-by: Christian König
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 2 ++
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 2
From: Monk Liu
This help fix reloading driver hang issue of SDMA
ring
Signed-off-by: Monk Liu
Reviewed-by: Alex Deucher
Reviewed-by: Christian König
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c | 1 +
1 file changed, 1 insertion(+)
diff --git
From: Monk Liu
This help fix reloading driver hang issue of SDMA
ring.
Signed-off-by: Monk Liu
Reviewed-by: Alex Deucher
Reviewed-by: Christian König
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 3 +++
1 file changed, 3 insertions(+)
diff
This patch set fixes SDMA after module reload.
Monk Liu (4):
drm/amdgpu: clear RB at ring init
drm/amdgpu: clear SA bo when created
drm/amdgpu: init more register for sdma
drm/amdgpu: modify sdma start sequence
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 3 +++
ming it's done through the engine...).
>
> --
Oh, and Mesa is 12.0 rc1.
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On Tue, 17 May 2016 08:47:11 +0200
Daniel Vetter wrote:
> > +static struct drm_encoder *sii902x_best_encoder(struct drm_connector
> > *connector)
> > +{
> > + struct sii902x *sii902x = connector_to_sii902x(connector);
> > +
> > + return sii902x->bridge.encoder;
> > +}
>
>
https://bugzilla.kernel.org/show_bug.cgi?id=117151
--- Comment #6 from Parker Reed ---
Created attachment 218661
--> https://bugzilla.kernel.org/attachment.cgi?id=218661=edit
4.7.0-rc1 log
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https://bugzilla.kernel.org/show_bug.cgi?id=117151
--- Comment #5 from Parker Reed ---
Compiled git today and issue persists. Log attached.
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Parker Reed changed:
What|Removed |Added
Kernel Version|4.6 |4.7
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Fallback drm_atomic_helper_best_encoder() is funcs->best_encoder() is NULL
so that DRM drivers can leave this hook unassigned if they know they want
to use drm_atomic_helper_best_encoder().
Signed-off-by: Boris Brezillon
---
drivers/gpu/drm/drm_atomic_helper.c | 4 +++-
1 file changed, 3
On 2016å¹´06æ01æ¥ 17:19, Yakir Yang wrote:
> There is a bug in RK3399 VOP, when bootloader/kernel only enable
> VOP Big or VOP Little to display, then VOP IOMMU would failed to
> reset at the initial time and VOP register couldn't write rightly.
>
> After do the pure reset of VOP module, then
Am Mittwoch, 1. Juni 2016, 08:24:48 schrieb Doug Anderson:
> Lin Huang,
>
> On Wed, Jun 1, 2016 at 2:35 AM, Lin Huang wrote:
> > add ddrc clock setting, so we can do ddr frequency
> > scaling on rk3399 platform in future.
> >
> > Signed-off-by: Lin Huang
> > ---
> >
> >
when in ddr frequency scaling process, vop can not do
enable or disable operate, since dcf will base on vop vblank
time to do frequency scaling and need to get vop irq if there
have vop enabled. So need register to dmc notifier, and we can
get the dmc status.
Signed-off-by: Lin Huang
---
there is dfi controller on rk3399 platform, it can monitor
ddr load, register this controller to devfreq framework, and
default to use simple_ondeamnd policy, and do ddr frequency
scaling base on this result.
Signed-off-by: Lin Huang
---
drivers/devfreq/Kconfig | 2 +-
add ddrc clock setting, so we can do ddr frequency
scaling on rk3399 platform in future.
Signed-off-by: Lin Huang
---
drivers/clk/rockchip/clk-rk3399.c | 16
include/dt-bindings/clock/rk3399-cru.h | 1 +
2 files changed, 17 insertions(+)
diff --git
On new rockchip platform(rk3399 etc), there have dcf controller to
do ddr frequency scaling, and this controller will implement in
arm-trust-firmware. We add a special clock-type to handle that.
Signed-off-by: Lin Huang
---
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk-ddr.c
rk3399 platform have dfi controller can monitor ddr load,
and dcf controller to handle ddr register so we can get the
right ddr frequency and make ddr controller happy work(which
will implement in bl31). So we do ddr frequency scaling with
following flow:
kernel
The power tables on some variants require different firmware.
This may fix stability issues on some newer CI parts.
bug:
https://bugs.freedesktop.org/show_bug.cgi?id=91880
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/cik.c | 14 +-
1 file changed, 13 insertions(+), 1
The power tables on some variants require different firmware.
This may fix stability issues on some newer SI parts.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/si.c | 45 -
1 file changed, 44 insertions(+), 1 deletion(-)
diff --git
The power tables on some variants require different firmware.
This fixes stability issues on some newer CI parts.
bug:
https://bugs.freedesktop.org/show_bug.cgi?id=91880
Signed-off-by: Alex Deucher
Signed-off-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/ci_dpm.c |
Hi Dave,
Same pull request but after fixing the prototype mismatch in patch 1
(this time I tested it).
This pull request contains 2 trivial fixes for the atmel-hlcdc driver.
The first one is making use of __drm_atomic_helper_crtc_destroy_state()
instead of duplicating its logic in
From: Herve Jourdain
Contrary to other flags to DRM_IOCTL_DEF_DRV(), which restrict usage,
the flag for render node is an enabler (the IOCTL can't be used from
render node if it's not present). So DRM_RENDER_ALLOW needs to be
added to all the flags that were previously
On Mon, May 30, 2016 at 07:52:53PM +0200, Daniel Vetter wrote:
> No dev->struct_mutex anywhere to be seen.
>
> Cc: Russell King
Acked-by: Russell King
(please note the new address.)
Thanks.
--
RMK's Patch system:
ahb_rst = devm_reset_control_get(vop->dev, "ahb");
This uses the same pattern, so you might want to consider reworking this
as well, though it should be a separate patch.
Thierry
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There is a bug in RK3399 VOP, when bootloader/kernel only enable
VOP Big or VOP Little to display, then VOP IOMMU would failed to
reset at the initial time and VOP register couldn't write rightly.
After do the pure reset of VOP module, then things back to right.
Signed-off-by: Yakir Yang
---
From: Monk Liu
1,should use late_fini to kfree all resource otherwise
the released pointer maybe accessed in IRQ ip fini routine.
2,hwmgr should not be kfree by pem_fini which is invoked
by hw fini path.
Signed-off-by: Monk Liu
Reviewed-by: Alex Deucher
Reviewed-by:
From: Monk Liu
This adds a late_fini callback for the powerplay
ip module.
Signed-off-by: Monk Liu
Reviewed-by: Alex Deucher
Reviewed-by: Christian König
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 17 +
1 file changed,
From: Monk Liu
This adds a late_fini function for handling special
ordering issues between ip modules at tear down time.
Signed-off-by: Monk Liu
Reviewed-by: Alex Deucher
Reviewed-by: Christian König
Signed-off-by: Alex Deucher
---
This fixes a crash in module unloading with powerplay enabled
due to cross IP module dependencies.
Monk Liu (3):
drm/amdgpu: add late_fini for ip_funcs
drm/amdgpu: impl late_fini for amdgpu_pp_ip
drm/amdgpu: fix pplib finish bug
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 5 +
Hi Thierry,
On Mon, 2016-05-30 at 12:45 +0200, Thierry Reding wrote:
> On Mon, May 23, 2016 at 05:43:02PM +0800, CK Hu wrote:
> > Hi, YT:
> >
> > One comment below.
> >
> > On Fri, 2016-05-20 at 23:05 +0800, yt.shen at mediatek.com wrote:
> > > From: YT Shen
> > >
> > > There are some
Hi Thierry,
On Mon, 2016-05-30 at 12:41 +0200, Thierry Reding wrote:
> On Fri, May 20, 2016 at 11:05:32PM +0800, yt.shen at mediatek.com wrote:
> > From: YT Shen
> >
> > Add MT8173 suffix for hardware related macros.
> >
> > Signed-off-by: YT Shen
> > ---
> >
Now that we handle this correctly, there is no need to force
it.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_atpx_handler.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_atpx_handler.c
b/drivers/gpu/drm/radeon/radeon_atpx_handler.c
On PX systems without dGPU power control, use PCI_D3hot.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_drv.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c
b/drivers/gpu/drm/radeon/radeon_drv.c
index 2dc43f5..ec80050
The runtime pm sequence is different depending on whether or
not the platform supports ATPX dGPU power control.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_atpx_handler.c | 4
drivers/gpu/drm/radeon/radeon_drv.c | 2 ++
2 files changed, 6 insertions(+)
diff
ATPX dGPU power control requires a 200ms delay between
power off and on. This should fix dGPU failures on
resume from power off.
Signed-off-by: Alex Deucher
Cc: stable at vger.kernel.org
---
drivers/gpu/drm/radeon/radeon_atpx_handler.c | 5 +
1 file changed, 5 insertions(+)
diff --git
The presence of the power control method should be determined
via the presence of the method in function 0. However, some
sbioses only set the appropriate bits in function 1 so use
then to override a missing power control function.
Signed-off-by: Alex Deucher
---
Windows 10 (and some 8.1) systems use standardized
ACPI calls for hybrid laptops to control dGPU power.
Detect those cases and disable the AMD specific ATPX
power control.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_atpx_handler.c | 5 +
1 file changed, 5 insertions(+)
Now that we handle this correctly, there is no need to force
it.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
On PX systems without dGPU power control, use PCI_D3hot.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index
The runtime pm sequence is different depending on whether or
not the platform supports ATPX dGPU power control.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c | 4
2 files changed, 6 insertions(+)
ATPX dGPU power control requires a 200ms delay between
power off and on. This should fix dGPU failures on
resume from power off.
Signed-off-by: Alex Deucher
Cc: stable at vger.kernel.org
---
drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c | 5 +
1 file changed, 5 insertions(+)
diff --git
The presence of the power control method should be determined
via the presence of the method in function 0. However, some
sbioses only set the appropriate bits in function 1 so use
then to override a missing power control function.
Signed-off-by: Alex Deucher
---
Windows 10 (and some 8.1) systems use standardized
ACPI calls for hybrid laptops to control dGPU power.
Detect those cases and disable the AMD specific ATPX
power control.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c | 5 +
1 file changed, 5 insertions(+)
This patch set cleans up and attempts to make runtime pm more
reliable in radeon and amdgpu on PX systems. If you have a PX
system that requires setting the runpm=0 module parameter for
stability, please try this patch set.
The main fix is that a minimum of 200ms of delay is required between
a
On Wed, Jun 01, 2016 at 03:48:38PM +0100, Liviu Dudau wrote:
> Because the HDLCD lacks a hardware counter for vsync signal, the DRM
> framework expects that the vsync interrupts are left running to feed
> the internal software counter. Currently the HDLCD is masking/unmasking
> the vsync interrupt
On Wed, 01 Jun 2016, Daniel Vetter wrote:
> On Wed, Jun 1, 2016 at 11:46 AM, Jani Nikula
> wrote:
>> On Wed, 01 Jun 2016, Daniel Vetter wrote:
>>> There's still something very fishy going on with some of these, e.g.
>>> the drm_modeset_lock Example: and the "Standard GTF Parameters:" Line
>>>
Just fallout from switching from asciidoc to sphinx/rst.
v2: Found more. Also s/\//#/ in the vgpu ascii-art - sphinx treats
those as comments and switch to variable-width, which wreaks the
layout.
v3: Undo some of the hacks, rebasing onto latest version of Jani's
series fixed it.
Signed-off-by:
On Wed, Jun 01, 2016 at 04:46:10PM +0300, Jani Nikula wrote:
> On Wed, 01 Jun 2016, Daniel Vetter wrote:
> > On Wed, Jun 1, 2016 at 11:46 AM, Jani Nikula
> > wrote:
> >> On Wed, 01 Jun 2016, Daniel Vetter wrote:
> >>> There's still something very fishy going on with some of these, e.g.
> >>>
On Wed, Jun 01, 2016 at 11:38:03AM +0100, Chris Wilson wrote:
> On Wed, Jun 01, 2016 at 11:57:09AM +0200, Daniel Vetter wrote:
> > On Mon, May 30, 2016 at 09:38:20AM +0100, Chris Wilson wrote:
> > > If a driver wants to more precisely control its initialisation and in
> > > particular, defer
On Wed, Jun 01, 2016 at 02:36:41PM +0200, Lukas Wunner wrote:
> On Wed, May 25, 2016 at 03:43:42PM +0200, Daniel Vetter wrote:
> > On Wed, May 25, 2016 at 12:51 PM, Lukas Wunner wrote:
> > > On Tue, May 24, 2016 at 11:30:42PM +0200, Daniel Vetter wrote:
> > >> On Tue, May 24, 2016 at 06:03:27PM
Since commit 4dfd64862ff8 ("drm: Use vblank timestamps to guesstimate
how many vblanks were missed"), the DRM framework can cope with devices
that don't have a hardware counter for vsync events without having
to keep the vsync interrupts enabled all the time. Drivers handling
such hardware should
drm_fb_cma code has a nice helper function to display in the debugfs
information about the underlying framebuffers used by HDLCD:
$ cat /sys/kernel/debug/dri/0/fb
fb: 1920x1200 at XR24
0: offset=0 pitch=7680, obj: 0 ( 2) 001011ba 0xfc30
ff800a27c000 9338880
fb: 1920x1200 at
Harden the plane_check() code to drop attempts at scaling because
that is not supported. Make hdlcd_plane_atomic_update() set the pitch
and line length registers that correctly reflect the plane's values.
And make hdlcd_crtc_mode_set_nofb() a helper function for
hdlcd_crtc_enable() rather than an
From: Daniel Vetter
event_list just reimplemented what drm_crtc_arm_vblank_event does. And
we also need to send out drm events when shutting down a pipe.
With this it's possible to use the new nonblocking commit support in
the helpers.
Signed-off-by: Daniel Vetter
Because the HDLCD driver acts as a component master it can end
up enabling the runtime PM functionality before the encoders
are initialised. This can cause crashes if the component slave
never probes (missing module) or if the PM operations kick in
before the probe finishes.
Move the enabling of
Hello,
Here are a series of patches that I would like to add to v4.7. It fixes issues
with suspend/resume on Juno (support for which has been added in v4.7-rc1).
When doing the work I've noticed some breakage on the vsync behaviour so I've
fixed that as well. In order to ease the introduction of
Hi Dave,
On Wed, 1 Jun 2016 14:23:27 +0200
Boris Brezillon wrote:
> Hi Dave,
>
> This pull request contains 2 trivial fixes for the atmel-hlcdc driver.
Please ignore this PR. The __drm_atomic_helper_crtc_destroy_state()
prototype has changed between my submission and the 4.7-rc1 release and
drm_fb_cma code has a nice helper function to display in the debugfs
information about the underlying framebuffers used by HDLCD:
$ cat /sys/kernel/debug/dri/0/fb
fb: 1920x1200 at XR24
0: offset=0 pitch=7680, obj: 0 ( 2) 001011ba 0xfc30
ff800a27c000 9338880
fb: 1920x1200 at
Because the HDLCD lacks a hardware counter for vsync signal, the DRM
framework expects that the vsync interrupts are left running to feed
the internal software counter. Currently the HDLCD is masking/unmasking
the vsync interrupt on vblank enable/disable calls, which break that
expectation. Fix
Harden the plane_check() code to drop attempts at scaling because
that is not supported. Make hdlcd_plane_atomic_update() set the pitch
and line length registers that correctly reflect the plane's values.
And make hdlcd_crtc_mode_set_nofb() a helper function for
hdlcd_crtc_enable() rather than an
From: Daniel Vetter
event_list just reimplemented what drm_crtc_arm_vblank_event does. And
we also need to send out drm events when shutting down a pipe.
With this it's possible to use the new nonblocking commit support in
the helpers.
Signed-off-by: Daniel Vetter
Because the HDLCD driver acts as a component master it can end
up enabling the runtime PM functionality before the encoders
are initialised. This can cause crashes if the component slave
never probes (missing module) or if the PM operations kick in
before the probe finishes.
Move the enabling of
Hello,
Here are a series of patches that I would like to add to v4.7. It fixes issues
with suspend/resume on Juno (support for which has been added in v4.7-rc1).
When doing the work I've noticed some breakage on the vsync behaviour so I've
fixed that as well. In order to ease the introduction of
On Wed, Jun 1, 2016 at 11:46 AM, Jani Nikula
wrote:
> On Wed, 01 Jun 2016, Daniel Vetter wrote:
>> There's still something very fishy going on with some of these, e.g.
>> the drm_modeset_lock Example: and the "Standard GTF Parameters:" Line
>> somehow get treated as heading when just appending a
From: Christian König
vm_flush() now comes directly after vm_grab_id().
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 31 +++
2 files changed, 11 insertions(+),
From: Christian König
Just wait for any fence to become available, instead
of waiting for the last entry of the LRU.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 10 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 2 +-
From: Christian König
This fixes a fairness problem with the GPU scheduler. VM having lot of
jobs could previously starve VM with less jobs.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 113 +
1 file
From: Christian König
Prefer to use a VMIDs which are idle on the ring we want to submit to. This
also removes bubbling idle VMIDs up on the LRU, which is actually not
beneficial.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 24
From: Christian König
Check if the sync object is idle depending on the ring a submission works with.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 2 +-
From: Christian König
Stop hiding bugs, instead print a proper error when the scheduler
doesn't handle all dependencies.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 6 +-
From: Christian König
Make it two events, one for the job being scheduled and one when it is finished.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 4 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 4 +-
From: Christian König
It's not obvious what it should do.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
From: Christian König
If @signal_on_any is true the fence array signals if any fence in the array
signals, otherwise it signals when all fences in the array signal.
v2: fix signaled test and add comment suggested by Chris Wilson.
Signed-off-by: Christian König
---
From: Gustavo Padovan
struct fence_collection inherits from struct fence and carries a
collection of fences that needs to be waited together.
It is useful to translate a sync_file to a fence to remove the complexity
of dealing with sync_files on DRM drivers. So
From: Christian König
Fence contexts are created on the fly (for example) by the GPU scheduler used
in the amdgpu driver as a result of an userspace request. Because of this
userspace could in theory force a wrap around of the 32bit context number
if it doesn't behave
Hi guys,
this is the next iteration of the fence array patch set.
Daniel suggested that I provide an example on how this functionality might be
used by a driver. So I added a few additional patches in this series to show
what I want to do with this in the amdgpu driver.
The main idea is that
Hi Javier,
2016ë
05ì 31ì¼ 07:58ì Javier Martinez Canillas ì´(ê°) ì´ ê¸:
> Hello Inki,
>
> On 04/05/2016 04:27 AM, Inki Dae wrote:
>> This patch adds HW trigger support on i80 mode.
>>
>> Until now, Exynos DRM only supported SW trigger which was set
>> SWTRGCMD bit of TRIGCON register
This patch fixes a regression that Display panel doesn't work
since HW trigger mode was supported.
The trigger mode should be changed on PSR(Panel Self Refresh)
mode of Panel device according to HW guy's saying. However,
with previous HW trigger support, trigger mode could been changed
in normal
On Wed, 1 Jun 2016 08:21:09 +0900 Minchan Kim wrote:
> Recently, I got many reports about perfermance degradation in embedded
> system(Android mobile phone, webOS TV and so on) and easy fork fail.
>
> The problem was fragmentation caused by zram and GPU driver mainly.
> With memory pressure,
On Wed, May 25, 2016 at 03:43:42PM +0200, Daniel Vetter wrote:
> On Wed, May 25, 2016 at 12:51 PM, Lukas Wunner wrote:
> > On Tue, May 24, 2016 at 11:30:42PM +0200, Daniel Vetter wrote:
> >> On Tue, May 24, 2016 at 06:03:27PM +0200, Lukas Wunner wrote:
> >> > When a drm_crtc structure is
Don't disable the vsync interrupt, as the hardware lacks hardware
counters for vsync time stamping and that breaks the DRM assumptions.
Also harden the plane_check() code to drop attempts at scaling because
that is not supported. Make hdlcd_plane_atomic_update() set the pitch
and line length
Hi Dave,
This pull request contains 2 trivial fixes for the atmel-hlcdc driver.
The first one is making use of __drm_atomic_helper_crtc_destroy_state()
instead of duplicating its logic in atmel_hlcdc_crtc_reset() and
risking memory leaks if other objects are added to the common CRTC
state.
The
Ack-by: Benjamin Gaignard
2016-05-30 15:31 GMT+02:00 Arnaud Pouliquen :
> Add the interface needed by audio hdmi-codec driver.
>
> Signed-off-by: Arnaud Pouliquen
> ---
> drivers/gpu/drm/sti/Kconfig| 1 +
> drivers/gpu/drm/sti/sti_hdmi.c | 294
> ++---
The driver is only enabling scaling, but never disabling it, thus, if you
enable the scaling feature once it stays enabled forever.
Signed-off-by: Boris Brezillon
Reported-by: Alex Vazquez
Fixes: 1a396789f65a ("drm: add Atmel HLCDC Display Controller support")
Cc:
---
On Wed, Jun 01, 2016 at 10:47:51AM +0100, Chris Wilson wrote:
> On Wed, Jun 01, 2016 at 12:43:53PM +0300, Ville Syrjälä wrote:
> > On Wed, Jun 01, 2016 at 10:34:36AM +0100, Chris Wilson wrote:
> > > The intention of using video=: is primarily to select
> > > the user's preferred resolution at
On Wed, 01 Jun 2016, Daniel Vetter wrote:
> There's still something very fishy going on with some of these, e.g.
> the drm_modeset_lock Example: and the "Standard GTF Parameters:" Line
> somehow get treated as heading when just appending a :: at the end of
> those lines. But it seems to work
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