Am 14.07.20 um 10:25 schrieb Dan Carpenter:
> On Tue, Jul 14, 2020 at 03:39:13AM +0200, Roland Scheidegger wrote:
>> Am 26.06.20 um 12:39 schrieb Dan Carpenter:
>>> These if statements are supposed to be true if we ended the
>>> list_for_each_entry() loops without hitting a break statement but
https://bugzilla.kernel.org/show_bug.cgi?id=207383
Duncan (1i5t5.dun...@cox.net) changed:
What|Removed |Added
Kernel Version|5.7-rc1 - 5.7 - 5.8-rc4+|5.7-rc1 - 5.7 - 5.8-rc5+
From: Christophe JAILLET
Date: Tue, 14 Jul 2020 20:35:01 +0200
> The wrappers in include/linux/pci-dma-compat.h should go away.
>
> The patch has been generated with the coccinelle script below and has been
> hand modified to replace GFP_ with a correct flag.
> It has been compile tested.
>
>
On Tue, Jul 14, 2020 at 10:33 AM Jeffrey Hugo wrote:
>
> On Mon, Jul 13, 2020 at 5:50 PM Doug Anderson wrote:
> >
> > Hi,
> >
> > On Mon, Jul 13, 2020 at 1:25 PM Rob Herring wrote:
> > >
> > > On Mon, Jul 13, 2020 at 9:08 AM Doug Anderson
> > > wrote:
> > > >
> > > > Hi,
> > > >
> > > > On
From: Bas Nieuwenhuizen
Calltree:
timeline_fence_release
drm_sched_entity_wakeup
dma_fence_signal_locked
sync_timeline_signal
sw_sync_ioctl
Releasing the reference to the fence in the fence signal callback
seems reasonable to me, so this patch avoids the locking issue in
sw_sync.
While sw_sync is purely a debug facility for userspace to create fences
and timelines it can control, nevertheless it has some tricky locking
semantics of its own. In particular, Bas Nieuwenhuizen reported that we
had reintroduced a deadlock if a signal callback attempted to destroy
the fence. So
Since we decouple the sync_pt from the timeline tree upon release, in
order to allow releasing the sync_pt from a signal callback we need to
separate the sync_pt signaling lock from the timeline tree lock.
v2: Mark up the unlocked read of the current timeline value.
v3: Store a timeline pointer
Take 2. dma_fence_parent() relied on fence->lock pointing into the
sync_timeline which is no more, so we need a sync_pt->timeline
backpointer instead.
-Chris
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dri-devel@lists.freedesktop.org
Get clock info from DT and enable it during initialization.
Also changed name of the driver to "kmb,display" to match other
entries in the DT.
v2: fixed error in clk_disable
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_drv.c | 41
name change
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/Makefile | 4 ++--
drivers/gpu/drm/kmb/kmb_drv.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/kmb/Makefile b/drivers/gpu/drm/kmb/Makefile
index
Print messages for LCD DMA FIFO errors.
v2: corrected spelling
Signed-off-by: Anitha Chrisanthus
---
drivers/gpu/drm/kmb/kmb_drv.c | 68 +++--
drivers/gpu/drm/kmb/kmb_plane.h | 2 ++
2 files changed, 60 insertions(+), 10 deletions(-)
diff --git
of probe and return probe_defer early on, so that all the other
initializations can be done after adv driver is loaded successfully.
Signed-off-by: Anitha Chrisanthus
---
drivers/gpu/drm/kmb/kmb_drv.c | 74 +-
drivers/gpu/drm/kmb/kmb_dsi.c | 144
v2: code review changes
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_plane.c | 14 +-
drivers/gpu/drm/kmb/kmb_regs.h | 1 +
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/kmb/kmb_plane.c
This initializes the multichannel fifo in the mipi transmitter and
sets the LCD to mipi interconnect which connects LCD to MIPI ctrl #6
v2: code review changes to make code simpler
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_drv.h | 25
System clock is different for A0 and B0 silicons, so get it directly
from clk_PLL0 through SCMI calls.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_drv.c | 11 +++
drivers/gpu/drm/kmb/kmb_drv.h | 1 +
drivers/gpu/drm/kmb/kmb_dsi.c | 12
Disable ping pong mode otherwise video corruption results,
use continuous mode and also fetch the dma
addresses before disabling dma. For now, only initialize the dma and
planes once and for next plane updates only update the addresses for
dma.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob
This is part2 of DPHY initialization- sets up DPHY PLLs.
v2: simplified mipi_tx_get_vco_params() based on review
v3: added WARN_ON for invalid freq
v4: fixed bug in mipi_tx_get_vco_params
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_dsi.c | 194
This is to keep track of the id of the plane as there are 4 planes in
Kmb and when update() is called, we need to know which plane need to be
updated so that the corresponding plane's registers can be programmed.
v2: moved extern to .h, upclassed dev_private,
minor changes from code review.
cleanup code
Signed-off-by: Anitha Chrisanthus
---
drivers/gpu/drm/kmb/kmb_drv.c | 5 +++--
drivers/gpu/drm/kmb/kmb_drv.h | 1 -
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c
index 71fdb94..78cb91b 100644
---
Initial issue was that display remains shifted after undeflow, this fix is
to recover the dma after underflow so display is clean. Major changes are
reduce LCD_CLK to 200Mhz and some changes in the lcd timing params
run recovery sequence at the EOF after underflow happens
do nothing in
Added handlers for lcd and mipi, it only finds and clears the interrupt
as of now, more functionality can be added as needed.
v2: upclassed dev_private
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_drv.c | 55 +++---
Also moved num_planes init before load, time out for dsi
fixed kmb regs read/write to only pass dev_p and few other minor
changes.
Signed-off-by: Anitha Chrisanthus
---
drivers/gpu/drm/kmb/kmb_drv.c | 32 ++--
drivers/gpu/drm/kmb/kmb_drv.h | 34
Fix test_mode_send and dphy_wait_fsm for 2-lane MIPI
- Fix test_mode_send when sending normal mode test codes
- Change dphy_wait_fsm to check for IDLE status rather than LOCK
status for 2-lane MIPI
v2: upclassed dev_private
Signed-off-by: Anitha Chrisanthus
Signed-off-by: Edmund Dea
---
Find ADV 7535 from the device tree and get the bridge driver and attach
it to the DRM and the MIPI encoder.
v2: check for valid encoder node
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_drv.c | 27 ++-
Enabled vblank interrupts for LCD.
v2: upclassed dev_private
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_crtc.c | 36 +++-
drivers/gpu/drm/kmb/kmb_drv.c | 41 +
name change
Signed-off-by: Anitha Chrisanthus
---
drivers/gpu/drm/kmb/kmb_drv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c
index 78cb91b..4afdb9c 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.c
+++
Check if format is supported and size is within limits.
v2: simplified the code as per code review
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_plane.c | 111 +++-
1 file changed, 65 insertions(+), 46 deletions(-)
This completes the DPHY initialization and Tx initialization.
v2: minor code review changes
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_dsi.c | 65 ++
drivers/gpu/drm/kmb/kmb_dsi.h | 18
These changes are ported from Myriadx which has additional registers
updated for planes. This change does the following
reinitialize plane interrupts
program Cb/Cr for planar formats
set LCD_CTRL_VHSYNC_IDLE_LVL
set output format and configure csc
v2: code review changes
v3: corrected spelling
The issue was that spurious interrupts were happening before the LCD
controller was enabled and system hangs. Fix is to
clear LCD interrupts and disable them before modeset
and re enable them after enabling LCD controller.
v2: upclassed dev_private
Signed-off-by: Anitha Chrisanthus
Reviewed-by:
Also added debug messages
Signed-off-by: Anitha Chrisanthus
---
drivers/gpu/drm/kmb/kmb_drv.c | 16 ++--
drivers/gpu/drm/kmb/kmb_regs.h | 6 +++---
2 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c
index
This code is commented out until firmware is updated to
redirect LCD IRQ from MSSCPU to A53.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_drv.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git
Also free dsi resources on driver unload. System clock frequency change
for llp ratio calculation.
v2: upclassed dev_private
Signed-off-by: Anitha Chrisanthus
---
drivers/gpu/drm/kmb/kmb_crtc.c | 25
drivers/gpu/drm/kmb/kmb_drv.c | 6 +-
drivers/gpu/drm/kmb/kmb_drv.h | 1 +
From: Edmund Dea
Added test pattern generator function. Enable this at compile time to
test if mipi is working. mipi->hdmi section
Signed-off-by: Edmund Dea
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_dsi.c | 31 +++
drivers/gpu/drm/kmb/kmb_dsi.h | 7
Removed hardcoded timings, set timings based on the current mode's
input timings. Also calculate and set the lane rate based on the
timings.
Signed-off-by: Anitha Chrisanthus
---
drivers/gpu/drm/kmb/kmb_crtc.c | 9 +++-
drivers/gpu/drm/kmb/kmb_dsi.c | 93
From: Edmund Dea
Note that we enable clk_msscam but do not set clk_msscam. However, we do
enable and set clk_mipi_ecfg and clk_mipi_cfg.
Verify that LCD and MIPI clocks are set successfully.
Signed-off-by: Edmund Dea
---
drivers/gpu/drm/kmb/kmb_drv.c | 112
This is part1 of DPHY initialization.
v2: remove kmb_write() as the function provides no benefit over
calling writel() directly.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_drv.h | 5 -
drivers/gpu/drm/kmb/kmb_dsi.c | 346
From: Edmund Dea
Made it conditionally compiled.
Signed-off-by: Edmund Dea
---
drivers/gpu/drm/kmb/kmb_drv.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c
index 90db07c..861aa97 100644
---
From: Edmund Dea
- Removed deprecated code blocks within probe functions
- In kmb_remove, unregister MIPI DSI host
- In kmb_probe, if kmb_load fails, then unregister MIPI DSI host
- Change kmb_dsi_host_bridge_init to return error codes using ERR_PTR
- Do clock intitialization earlier
- Rename
Set swap bit for the colors to display correctly
when the format is RGB and not set when its BGR.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_plane.c | 36 ++--
1 file changed, 18 insertions(+), 18 deletions(-)
diff
Myriadx code has it set to these values.
v2: upclassed dev_private
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_crtc.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c
This initializes the interrupts for DSI. This is the final part of mipi
DSI initialization.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_drv.c | 1 +
drivers/gpu/drm/kmb/kmb_drv.h | 30 +++-
drivers/gpu/drm/kmb/kmb_dsi.c | 46
Mipi TX frame section configuration
This is the first part in the MIPI controller initialization.
Compute and set the right values in MIPI TX frame section configuration
registers like packet header(PH), unpacked bytes and line config.
v2: added more comments to clarify assumptions
v3: improved
general cleaning
Signed-off-by: Anitha Chrisanthus
---
drivers/gpu/drm/kmb/kmb_dsi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c
index 6e38f16..2599ed2 100644
--- a/drivers/gpu/drm/kmb/kmb_dsi.c
+++
Enable clocks for LCD, mipi common and mipi tx0
Renamed MSS_CAM_CLK_CTRL and also fixed bug in the
call to set this register.
Signed-off-by: Anitha Chrisanthus
---
drivers/gpu/drm/kmb/kmb_drv.c | 8
drivers/gpu/drm/kmb/kmb_drv.h | 14 ++
drivers/gpu/drm/kmb/kmb_dsi.c |
unmap MSSCAM registers
Signed-off-by: Anitha Chrisanthus
---
drivers/gpu/drm/kmb/kmb_drv.c | 15 +++
drivers/gpu/drm/kmb/kmb_drv.h | 1 -
drivers/gpu/drm/kmb/kmb_regs.h | 2 +-
3 files changed, 4 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c
This initializes the mipi high speed transmitter CTRL and SYNC
configuration registers.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_dsi.c | 55 --
drivers/gpu/drm/kmb/kmb_regs.h | 29 +-
2
KMB display pipeline is LCD->Mipi->HDMI. Mipi->HDMI converter chip only
accepts 4-lane input from mipi.
With 4-lane mipi, KMB hardware can only support 1080p resolution.
Therefore, limit supported mode to 1080p.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
From: Edmund Dea
revert dsi_host to static and instead add dsi_host_unregister.
Signed-off-by: Edmund Dea
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_drv.c | 6 +++---
drivers/gpu/drm/kmb/kmb_drv.h | 1 -
drivers/gpu/drm/kmb/kmb_dsi.c | 9 +++--
drivers/gpu/drm/kmb/kmb_dsi.h | 1
Register physical addresses are remapped and the register mmio
addresses for lcd,mipi and msscam are saved in drm_private.
All register reads/writes are updated to get the mmio offset
from this structure. We are using hardcoded values for register
physical addresses and this will be modified to
From: Edmund Dea
to remove compiler warnings and general clean up
v2: minor code review changes
v3: upclassed dev_private, corrected spelling
Signed-off-by: Edmund Dea
---
drivers/gpu/drm/kmb/kmb_crtc.c | 46 +-
drivers/gpu/drm/kmb/kmb_crtc.h |6 +-
drivers/gpu/drm/kmb/kmb_drv.c |
When disabling/enabling LCD layers, the change takes effect
immediately and does not wait for EOF (end of frame). If we
disable an LCD layer in kmb_plane_atomic_disable, then the frame
reappears with incorrect display offsets.
The solution is to mark the plane as disabled when
Register DSI host first and then defer probe until ADV bridge is
initialized.
Signed-off-by: Anitha Chrisanthus
---
drivers/gpu/drm/kmb/kmb_drv.c | 144 ++
drivers/gpu/drm/kmb/kmb_dsi.c | 46 --
drivers/gpu/drm/kmb/kmb_dsi.h | 3 +-
3 files
From: Edmund Dea
Video artifacts appear during playback as horizontal lines that
sporadically appear every few frames. Issue was caused by writing to
LCD_LAYERn_CFG register twice during plane updates. Issue is fixed by
writing to LCD_LAYERn_CFG only once.
Removed plane_init_status so that
setbits instead of write dword for LCD_CONTROL register
this was inadvertantly disabling the LCD controller.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_plane.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git
Set the DMA Vstride and Line width for U and V planes to the same as the
Y plane and not the actual pitch.
Bit18 of layer config does not have any effect when U and V planes are
swapped, so swap it in the driver.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Edmund Dea
---
Mipi input expects the memory layout to be unpacked with 8 bits per
pixel in RGB (BRG) order. If the LCD is not configured properly,
corrupted output results, changed dma_unpacked to 0 in mipi FG.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_crtc.c |
To run modetest without ADV driver, enable LCD_TEST and FCC_TEST.
Also made front porches 0, and some changes in the plane init.
v2: upclassed dev_private
Signed-off-by: Anitha Chrisanthus
---
drivers/gpu/drm/kmb/kmb_crtc.c | 13 +++
drivers/gpu/drm/kmb/kmb_drv.c | 6 +--
The issue was video starts fine, but towards the end, the color disappers.
Do the layer initializations only once, but update the DMA registers
for every frame. Also changed DRM_INFO to DRM_DEBUG.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_plane.c |
This is a new DRM driver for Intel's KeemBay SOC.
The SoC couples an ARM Cortex A53 CPU with an Intel
Movidius VPU.
This driver is tested with the KMB EVM board which is the refernce baord
for Keem Bay SOC. The SOC's display pipeline is as follows
+--++-+
Mipi TX Frame generator timing configuration
Compute and set frame generator timings like hactive, front porch,
back porch etc.
v2: minor code review changes
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_dsi.c | 132
Did some general clean up and organization.
v2: corrected spelling
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_drv.c | 3 +-
drivers/gpu/drm/kmb/kmb_regs.h | 852 +++--
2 files changed, 307 insertions(+), 548
Initial check-in for basic display driver for KeemBay family of SOCs.
This is not tested and does not work and also there are many TBDs in the
code which will be implemented in future commits.
v2: moved extern to .h, removed license text
use drm_dev_init, upclassed dev_private, removed
During update plane, set the layer format, bpp, fifo level,
RGB order, Cb/Cr order etc. in the LAYER_CFG register.
v2: Return val in set_pixel and set_bpp instead of passing in pointer,
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_plane.c | 145
Mipi HS registers start at an additional offset of 0x400 which needs to be
added at the register macro definition and not at the read/write function
level.
v2: replaced calculations with macro to make code simpler
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
Added mipi DSI host initialization functions
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_dsi.c | 59 +++
drivers/gpu/drm/kmb/kmb_dsi.h | 4 +++
2 files changed, 63 insertions(+)
diff --git
Also added separate macros for lcd and mipi register accesses that
use the corrected mmio offset. mmio oofset will be read from the device
tree in the future.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/kmb_crtc.c | 49
Basic frame work for mipi encoder and connector.
More hardware specific details will be added in the future commits.
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/kmb/Makefile | 2 +-
drivers/gpu/drm/kmb/kmb_drv.c | 2 +
drivers/gpu/drm/kmb/kmb_dsi.c | 94
Awsome, thanks for adding the tests!
Got to say I'm not that familiar with the self-test framework idioms,
but from my perspective patches 2 and 3 are
Reviewed-by: Bas Nieuwenhuizen
as well.
On Tue, Jul 14, 2020 at 10:06 PM Chris Wilson wrote:
>
> While sw_sync is purely a debug facility for
Thanks for updating the patch. LGTM
On Tue, Jul 14, 2020 at 10:07 PM Chris Wilson wrote:
>
> From: Bas Nieuwenhuizen
>
> Calltree:
> timeline_fence_release
> drm_sched_entity_wakeup
> dma_fence_signal_locked
> sync_timeline_signal
> sw_sync_ioctl
>
> Releasing the reference to the
Since we decouple the sync_pt from the timeline tree upon release, in
order to allow releasing the sync_pt from a signal callback we need to
separate the sync_pt signaling lock from the timeline tree lock.
v2: Mark up the unlocked read of the current timeline value.
Suggested-by: Bas
While sw_sync is purely a debug facility for userspace to create fences
and timelines it can control, nevertheless it has some tricky locking
semantics of its own. In particular, Bas Nieuwenhuize reported that we
had reintroduced a deadlock if a signal callback attempted to destroy
the fence. So
Since we decouple the sync_pt from the timeline tree upon release, in
order to allow releasing the sync_pt from a signal callback we need to
separate the sync_pt signaling lock from the timeline tree lock.
Suggested-by: Bas Nieuwenhuizen
Signed-off-by: Chris Wilson
Cc: Bas Nieuwenhuizen
---
From: Bas Nieuwenhuizen
Calltree:
timeline_fence_release
drm_sched_entity_wakeup
dma_fence_signal_locked
sync_timeline_signal
sw_sync_ioctl
Releasing the reference to the fence in the fence signal callback
seems reasonable to me, so this patch avoids the locking issue in
sw_sync.
Quoting Chris Wilson (2020-07-14 19:30:39)
> Quoting Bas Nieuwenhuizen (2020-07-14 19:17:21)
> > On Tue, Jul 14, 2020 at 6:26 PM Chris Wilson
> > wrote:
> > >
> > > Quoting Bas Nieuwenhuizen (2020-07-14 16:41:02)
> > > > Calltree:
> > > > timeline_fence_release
> > > >
Noralf Trønnes wrote:
> > In all cases, the driver on the host knows/has available how many bytes
> > were successfully transfered.
>
> I was thinking about the device, that it could get out of sync. Let's
> say the host sends a 1k framebuffer and half of it gets transferred and
> the rest fails
Den 14.07.2020 19.40, skrev Peter Stuge:
> Hi Noralf,
>
> Noralf Trønnes wrote:
>> I would like to keep the SET_BUFFER request since it will serve as a
>> syncing point between the host and the device. I'm no USB expert but I
>> assume that a bulk transfer can fail halfway through and result in
On 07/14, Daniel Vetter wrote:
> On Tue, Jul 14, 2020 at 07:39:42AM -0300, Melissa Wen wrote:
> > On Tue, Jul 14, 2020 at 7:20 AM Melissa Wen wrote:
> > >
> > > On 07/13, Daniel Vetter wrote:
> > > > On Fri, Jul 10, 2020 at 02:05:33PM -0300, Melissa Wen wrote:
> > > > > On 07/02, Daniel Vetter
From: Colin Ian King
Currently there are two places where the return status in ret is being
checked for an error however the assignment of ret has been omitted
making the checks redundant. Fix this by adding in the missing assignments
of ret.
Addresses-Coverity: ("Logically dead code")
Fixes:
This matches my understanding for what it's worth. In my little bit
of synchronization work in drm, I've gone out of my way to ensure we
can maintain this constraint.
Acked-by: Jason Ekstrand
On Thu, Jul 9, 2020 at 7:33 AM Daniel Vetter wrote:
>
> Comes up every few years, gets somewhat
On Tue, Jul 14, 2020 at 10:10 AM Matthias Kaehlcke wrote:
>
> On Tue, Jul 14, 2020 at 06:55:30PM +0530, Akhil P Oommen wrote:
> > On targets where GMU is available, GMU takes over the ownership of GX GDSC
> > during its initialization. So, take a refcount on the GX PD on behalf of
> > GMU before
Quoting Bas Nieuwenhuizen (2020-07-14 19:17:21)
> On Tue, Jul 14, 2020 at 6:26 PM Chris Wilson wrote:
> >
> > Quoting Bas Nieuwenhuizen (2020-07-14 16:41:02)
> > > Calltree:
> > > timeline_fence_release
> > > drm_sched_entity_wakeup
> > > dma_fence_signal_locked
> > > sync_timeline_signal
On Tue, Jul 14, 2020 at 6:26 PM Chris Wilson wrote:
>
> Quoting Bas Nieuwenhuizen (2020-07-14 16:41:02)
> > Calltree:
> > timeline_fence_release
> > drm_sched_entity_wakeup
> > dma_fence_signal_locked
> > sync_timeline_signal
> > sw_sync_ioctl
> >
> > Releasing the reference to the
Hi Noralf,
Noralf Trønnes wrote:
> I would like to keep the SET_BUFFER request since it will serve as a
> syncing point between the host and the device. I'm no USB expert but I
> assume that a bulk transfer can fail halfway through and result in the
> next update starting where the previous one
On Tue, Jul 14, 2020 at 06:55:30PM +0530, Akhil P Oommen wrote:
> On targets where GMU is available, GMU takes over the ownership of GX GDSC
> during its initialization. So, take a refcount on the GX PD on behalf of
> GMU before we initialize it. This makes sure that nobody can collapse the
> GX
Signed-off-by: kernel test robot
---
i915_irq.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9812a8051c5ea..79a3118f918a1 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++
Hi Karthik,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip drm-exynos/exynos-drm-next
tegra-drm/drm/tegra/for-next v5.8-rc5 next-20200714]
[cannot apply to drm/drm-next]
[If your patch
Quoting Bas Nieuwenhuizen (2020-07-14 16:41:02)
> Calltree:
> timeline_fence_release
> drm_sched_entity_wakeup
> dma_fence_signal_locked
> sync_timeline_signal
> sw_sync_ioctl
>
> Releasing the reference to the fence in the fence signal callback
> seems reasonable to me, so this patch
On Tue, Jul 14, 2020 at 04:39:47PM +0530, kalya...@codeaurora.org wrote:
> On 2020-07-14 06:42, Matthias Kaehlcke wrote:
> > On Thu, Jun 18, 2020 at 07:38:41PM +0530, Kalyan Thota wrote:
> > > This change adds support to scale src clk and bandwidth as
> > > per composition requirements.
> > >
> >
From: Sean Paul
Instead of doing a full modeset to enable/disable content protection,
simply go through the update_pipe flow which was introduced in the
related patch below. This avoids flashing the screen every time the user
starts viewing protected content.
Related: 634852d1f468 ("drm/i915:
On Tue, Jul 14, 2020 at 4:20 AM wrote:
>
> On 2020-07-13 22:50, Rob Clark wrote:
> > On Mon, Jul 13, 2020 at 8:59 AM wrote:
> >>
> >> On 2020-07-10 22:38, Rob Clark wrote:
> >> > On Thu, Jun 18, 2020 at 7:09 AM Kalyan Thota
> >> > wrote:
> >> >>
> >> >> This change adds support to scale src clk
Calltree:
timeline_fence_release
drm_sched_entity_wakeup
dma_fence_signal_locked
sync_timeline_signal
sw_sync_ioctl
Releasing the reference to the fence in the fence signal callback
seems reasonable to me, so this patch avoids the locking issue in
sw_sync.
d3862e44daa7
Hi,
On Fri, Jul 10, 2020 at 10:11 AM Steev Klimaszewski wrote:
>
>
> On 7/10/20 9:47 AM, Doug Anderson wrote:
> > Hi,
> >
> >
> > But should I continue on this path,
> > It's probably worth getting dithering working on your sdm845 anyway in
> > case anyone actually does put a 6bpp panel on this
Den 02.06.2020 13.46, skrev Noralf Trønnes:
>
>
> Den 02.06.2020 04.32, skrev Alan Stern:
>> On Tue, Jun 02, 2020 at 12:12:07AM +, Peter Stuge wrote:
>>
>> ...
>>
>>> The way I read composite_setup() after try_fun_setup: it calls f->setup()
>>> when available, and that can return < 0 to
On Tue, Jul 14, 2020 at 4:56 PM Melissa Wen wrote:
>
> Hi,
>
> On 07/14, Daniel Vetter wrote:
> > On Tue, Jul 14, 2020 at 11:57 AM Melissa Wen wrote:
> > >
> > > On 07/12, Rodrigo Siqueira wrote:
> > > > Hi,
> > > >
> > > > Everything looks fine to me, I just noticed that the amdgpu patches did
to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Karthik-B-S/Asynchronous-flip-implementation-for-i915/20200714-095304
base: git
On Thu, Jul 9, 2020 at 8:48 AM Hans de Goede wrote:
>
> Hi,
>
> On 7/8/20 11:25 PM, Alex Deucher wrote:
> > On Wed, Jul 8, 2020 at 12:43 PM Hans de Goede wrote:
> >>
> >> Hi All,
> >>
> >> Here is the privacy-screen related code which we discussed a while ago.
> >> This series consists of a
On Tue, Jul 14, 2020 at 06:55:30PM +0530, Akhil P Oommen wrote:
> On targets where GMU is available, GMU takes over the ownership of GX GDSC
> during its initialization. So, take a refcount on the GX PD on behalf of
> GMU before we initialize it. This makes sure that nobody can collapse the
> GX
Hi,
On 07/14, Daniel Vetter wrote:
> On Tue, Jul 14, 2020 at 11:57 AM Melissa Wen wrote:
> >
> > On 07/12, Rodrigo Siqueira wrote:
> > > Hi,
> > >
> > > Everything looks fine to me, I just noticed that the amdgpu patches did
> > > not apply smoothly, however it was trivial to fix the issues.
> >
From: Ben Skeggs
[ Upstream commit 0156e76d388310a490aeb0f2fbb5b284ded3aecc ]
Tegra TRM says worst-case reply time is 1216us, and this should fix some
spurious timeouts that have been popping up.
Signed-off-by: Ben Skeggs
Signed-off-by: Sasha Levin
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