Hi, Christian
Thanks for the reply.
On 12/10/20 11:53 AM, Christian König wrote:
Am 09.12.20 um 17:46 schrieb Thomas Hellström (Intel):
On 12/9/20 5:37 PM, Jason Gunthorpe wrote:
On Wed, Dec 09, 2020 at 05:36:16PM +0100, Thomas Hellström (Intel)
wrote:
Jason, Christian
In most
On 2020-12-10 at 11:56:40 +0530, Anshuman Gupta wrote:
> Enable HDCP 2.2 over DP MST.
> Authenticate and enable port encryption only once for
> an active HDCP 2.2 session, once port is authenticated
> and encrypted enable encryption for each stream that
> requires encryption on this port.
>
>
On 2020-12-10 at 11:56:39 +0530, Anshuman Gupta wrote:
> Add support for HDCP 2.2 DP MST shim callback.
> This adds existing DP HDCP shim callback for Link Authentication
> and Encryption and HDCP 2.2 stream encryption
> callback.
>
> v2:
> - Added a WARN_ON() instead of drm_err. [Uma]
> -
> -Original Message-
> From: Imre Deak
> Sent: Tuesday, December 1, 2020 4:05 AM
> To: Chery, Nanley G ; Chris Wilson wilson.co.uk>; Ville Syrjälä
> Cc: Daniel Vetter ; intel-...@lists.freedesktop.org; Nikula,
> Jani ; Daniel Vetter ;
> Kondapally, Kalyan ; Pandiyan, Dhinakaran
> ;
On 2020-12-10 at 11:56:36 +0530, Anshuman Gupta wrote:
> Add support for multiple mst stream in hdcp port data
> which will be used by RepeaterAuthStreamManage msg and
> HDCP 2.2 security f/w for m' validation.
>
> Security f/w doesn't have any provision to mark the
> stream_type for each stream
On 2020-12-10 at 11:56:31 +0530, Anshuman Gupta wrote:
> Enable HDCP 1.4 over DP MST for Gen12.
>
> v2:
> - Enable HDCP for <= Gen12 platforms. [Ram]
>
> Cc: Ramalingam C
> Tested-by: Karthik B S
> Signed-off-by: Anshuman Gupta
> ---
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 6 ++
>
On 2020-12-10 at 11:56:30 +0530, Anshuman Gupta wrote:
> Enable HDCP 1.4 DP MST stream encryption.
IMHO tile of "Configure HDCP1.4 MST steram encryption status" would suit
more.
But i leave that to your call.
>
> Enable stream encryption once encryption is enabled on
> the DP transport driving
On 2020-12-10 at 11:56:26 +0530, Anshuman Gupta wrote:
> There can be situation when DP MST connector is created without
> mst modeset being done, in those cases connector->encoder will be
> NULL. MST connector->encoder initializes after modeset.
> Don't enable HDCP in such cases to prevent any
https://bugzilla.kernel.org/show_bug.cgi?id=210543
--- Comment #4 from Ancheng (acyel...@gmail.com) ---
(In reply to Alex Deucher from comment #1)
> Please attach your full dmesg output.
Thanks for your response, attachment please find the dmesg output. There are
some differences in the call
https://bugzilla.kernel.org/show_bug.cgi?id=210543
--- Comment #3 from Ancheng (acyel...@gmail.com) ---
Created attachment 294095
--> https://bugzilla.kernel.org/attachment.cgi?id=294095=edit
dmesg file1
--
You are receiving this mail because:
You are watching the assignee of the bug.
https://bugzilla.kernel.org/show_bug.cgi?id=210543
--- Comment #2 from Ancheng (acyel...@gmail.com) ---
Created attachment 294093
--> https://bugzilla.kernel.org/attachment.cgi?id=294093=edit
dmesg file
--
You are receiving this mail because:
You are watching the assignee of the bug.
Hello Simon,
Hope you are doing well,
I was helping out Aurabindo and the team with the design, so I have taken the
liberty of adding some comments on behalf of the team, Inline.
On 11/12/20 3:31 am, Simon Ser wrote:
> Hi,
>
> (CC dri-devel, Pekka and Martin who might be interested in this as
On Thu, 10 Dec 2020 17:07:38 +0800, Yongqiang Niu wrote:
> add description for mt8183 display
>
> Signed-off-by: Yongqiang Niu
> ---
> Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Acked-by: Rob Herring
On Thu, Dec 10, 2020 at 05:07:37PM +0800, Yongqiang Niu wrote:
> rdma fifo size may be different even in same SOC, add this
> property to the corresponding rdma
>
> Signed-off-by: Yongqiang Niu
> ---
> .../bindings/display/mediatek/mediatek,disp.txt | 16
>
> 1 file
On Wed, 09 Dec 2020 14:24:27 +0800, Liu Ying wrote:
> Add support for Mixel MIPI DPHY + LVDS PHY combo IP
> as found on Freescale i.MX8qxp SoC.
>
> Cc: Guido Günther
> Cc: Kishon Vijay Abraham I
> Cc: Vinod Koul
> Cc: Rob Herring
> Cc: NXP Linux Team
> Signed-off-by: Liu Ying
> ---
>
On Wed, 09 Dec 2020 14:24:26 +0800, Liu Ying wrote:
> This patch converts the mixel,mipi-dsi-phy binding to
> DT schema format using json-schema.
>
> Comparing to the plain text version, the new binding adds
> the 'assigned-clocks', 'assigned-clock-parents' and
> 'assigned-clock-rates'
: i386-randconfig-r005-20201210 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
reproduce (this is a W=1 build):
git remote add radeon-alex git://people.freedesktop.org/~agd5f/linux.git
git fetch --no-tags radeon-alex amd-staging-drm-next
git checkout
Hi Linus,
Last week of fixes, just amdgpu and i915 collections. We had a i915
regression reported by HJ Lu reported this morning, and this contains
a fix for that he has tested.
There are a fair few other fixes, but they are spread across the two
drivers, and all fairly self contained.
I'm
On 12/10/20 2:26 PM, Thomas Gleixner wrote:
> All event channel setups bind the interrupt on CPU0 or the target CPU for
> percpu interrupts and overwrite the affinity mask with the corresponding
> cpumask. That does not make sense.
>
> The XEN implementation of irqchip::irq_set_affinity()
On 12/10/20 2:26 PM, Thomas Gleixner wrote:
> Signed-off-by: Thomas Gleixner
> Cc: Boris Ostrovsky
> Cc: Juergen Gross
> Cc: Stefano Stabellini
> Cc: xen-de...@lists.xenproject.org
> ---
> drivers/xen/events/events_base.c |6 --
> 1 file changed, 6 deletions(-)
>
> ---
On Thu, Dec 10, 2020 at 1:42 PM Thomas Gleixner wrote:
>
> Going through a full irq descriptor lookup instead of just using the proper
> helper function which provides direct access is suboptimal.
>
> In fact it _is_ wrong because the chip callback needs to get the chip data
> which is relevant
On Thu, Dec 10, 2020 at 1:42 PM Thomas Gleixner wrote:
>
> Going through a full irq descriptor lookup instead of just using the proper
> helper function which provides direct access is suboptimal.
>
> In fact it _is_ wrong because the chip callback needs to get the chip data
> which is relevant
Hi,
(CC dri-devel, Pekka and Martin who might be interested in this as well.)
On Thursday, December 10th, 2020 at 7:48 PM, Aurabindo Pillai
wrote:
> This patchset enables freesync video mode usecase where the userspace
> can request a freesync compatible video mode such that switching to this
On 10/12/2020 18:32, Ville Syrjälä wrote:
>>> @@ -1053,18 +1052,9 @@ static int setcmap_atomic(struct fb_cmap *cmap,
>>> struct fb_info *info)
>>> goto out_state;
>>> }
>>>
>>> - crtc_state = drm_atomic_get_crtc_state(state, crtc);
>>> - if
On Thu, Dec 10, 2020 at 08:25:49PM +0100, Thomas Gleixner wrote:
> Nothing uses the result and nothing should ever use it in driver code.
>
> Signed-off-by: Thomas Gleixner
> Cc: Jani Nikula
> Cc: Joonas Lahtinen
> Cc: Rodrigo Vivi
> Cc: David Airlie
> Cc: Daniel Vetter
> Cc: Pankaj
On 10/12/2020 17:27, Daniel Vetter wrote:
>> diff --git a/drivers/gpu/drm/drm_fb_helper.c
>> b/drivers/gpu/drm/drm_fb_helper.c
>> index e82db0f4e771..80e3797f0f01 100644
>> --- a/drivers/gpu/drm/drm_fb_helper.c
>> +++ b/drivers/gpu/drm/drm_fb_helper.c
>> @@ -46,6 +46,7 @@
>> #include
>>
Dma-buf is a standard cross-driver buffer sharing mechanism that can be
used to support peer-to-peer access from RDMA devices.
Device memory exported via dma-buf is associated with a file descriptor.
This is passed to the user space as a property associated with the
buffer allocation. When the
Dma-buf based memory region requires one extra parameter and is processed
quite differently. Adding a separate method allows clean separation from
regular memory regions.
Signed-off-by: Jianxin Xiong
Reviewed-by: Sean Hefty
Acked-by: Michael J. Ruhl
Acked-by: Christian Koenig
Acked-by: Daniel
Implement a new uverbs ioctl method for memory registration with file
descriptor as an extra parameter.
Signed-off-by: Jianxin Xiong
Reviewed-by: Sean Hefty
Acked-by: Michael J. Ruhl
Acked-by: Christian Koenig
Acked-by: Daniel Vetter
Reviewed-by: Leon Romanovsky
---
Implement the new driver method 'reg_user_mr_dmabuf'. Utilize the core
functions to import dma-buf based memory region and update the mappings.
Add code to handle dma-buf related page fault.
Signed-off-by: Jianxin Xiong
Reviewed-by: Sean Hefty
Acked-by: Michael J. Ruhl
Acked-by: Christian
This is the fifteenth version of the patch set. Changelog:
v15:
* Rebase to the latest linux-rdma 'for-next' branch (commit 0583531bb9ef)
to pick up RDMA core and mlx5 updates
* Let ib_umem_dmabuf_get() return 'struct ib_umem_dmabuf *' instead of
'struct ib_umem *'
* Move the check of on
On Fri 2020-11-13 12:54:41, Sakari Ailus wrote:
> Add a printk modifier %p4cc (for pixel format) for printing V4L2 and DRM
> pixel formats denoted by fourccs. The fourcc encoding is the same for both
> so the same implementation can be used.
>
> Suggested-by: Mauro Carvalho Chehab
>
The DRM core handles legacy gamma-set ioctl by setting GAMMA_LUT and
clearing CTM and DEGAMMA_LUT.
This works fine on HW where we have either:
degamma -> ctm -> gamma -> out
or
ctm -> gamma -> out
However, if the HW has gamma table before ctm, the atomic property
should be DEGAMMA_LUT, and
Hi,
Another try.
I dropped the has_gamma_prop and has_degamma_prop variables and use
drm_mode_obj_find_prop_id() instead.
I also changed the order of the patches, and added a new helper for
setting the gamma ramp to the properties.
Tomi
Tomi Valkeinen (2):
drm: automatic legacy gamma
To support legacy gamma ioctls the drivers need to set
drm_crtc_funcs.gamma_set either to a custom implementation or to
drm_atomic_helper_legacy_gamma_set. Most of the atomic drivers do the
latter.
We can simplify this by making the core handle it automatically.
Add three functions to
Hi Tomi,
I love your patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on linus/master v5.10-rc7]
[cannot apply to drm-tip/drm-tip anholt/for-next next-20201210]
[If your patch is applied to the wrong git tree, kindly drop us
Hi, bumping the discussion again here because we just ran into this again, as we
just had a laptop OEM try to fix another issue by adding an OSI check for these
strings instead of helping us fix the issue in nouveau. Note as well the issue
I'm referring to is entirely independent of runtime D3,
Hi Maxime,
On 2020-12-10 13:46, Maxime Ripard wrote:
The BCM2711 uses a number of instances of the bcmstb-l2 controller in
its
display engine. Let's allow the driver to be enabled through KConfig.
Signed-off-by: Maxime Ripard
---
drivers/irqchip/Kconfig | 2 +-
1 file changed, 1
On 10/12/2020 17:44, Thomas Gleixner wrote:
On Thu, Dec 10 2020 at 17:09, Tvrtko Ursulin wrote:
On 10/12/2020 16:35, Thomas Gleixner wrote:
I'll send out a series addressing irq_to_desc() (ab)use all over the
place shortly. i915 is in there...
Yep we don't need atomic, my bad. And we would
On Thu, Dec 10, 2020 at 10:40:36PM +0800, Shawn Guo wrote:
> Hi Uwe,
>
> On Thu, Dec 10, 2020 at 9:05 PM Uwe Kleine-König
> wrote:
> > > > @@ -111,6 +118,8 @@
> > > >
> > > > #define SN_LINK_TRAINING_TRIES 10
> > > >
> > > > +#define SN_PWM_GPIO3
> > >
> > >
From: Rob Clark
[ 192.062000] [ cut here ]
[ 192.062498] WARNING: CPU: 3 PID: 2039 at drivers/gpu/drm/msm/msm_gem.c:381
put_iova_vmas+0x94/0xa0 [msm]
[ 192.062870] Modules linked in: snd_hrtimer snd_seq snd_seq_device rfcomm
algif_hash algif_skcipher af_alg bnep
On Thu, Dec 10, 2020 at 05:50:00PM +0100, Daniel Vetter wrote:
> On Thu, Dec 10, 2020 at 5:44 PM Thierry Reding
> wrote:
> >
> > On Thu, Dec 10, 2020 at 11:15:38AM +0100, Daniel Vetter wrote:
> > > On Wed, Dec 09, 2020 at 02:28:18PM -0600, Bjorn Andersson wrote:
> > > > On Tue 08 Dec 17:52 CST
On 10/12/2020 16:35, Thomas Gleixner wrote:
On Thu, Dec 10 2020 at 10:45, Tvrtko Ursulin wrote:
On 10/12/2020 07:53, Joonas Lahtinen wrote:
I think later in the thread there was a suggestion to replace this with
simple counter increment in IRQ handler.
It was indeed unsafe until recent
On Thu, Dec 10, 2020 at 5:44 PM Thierry Reding wrote:
>
> On Thu, Dec 10, 2020 at 11:15:38AM +0100, Daniel Vetter wrote:
> > On Wed, Dec 09, 2020 at 02:28:18PM -0600, Bjorn Andersson wrote:
> > > On Tue 08 Dec 17:52 CST 2020, Daniel Vetter wrote:
> > >
> > > > On Tue, Dec 08, 2020 at 04:02:16PM
On Thu, Dec 10, 2020 at 11:15:38AM +0100, Daniel Vetter wrote:
> On Wed, Dec 09, 2020 at 02:28:18PM -0600, Bjorn Andersson wrote:
> > On Tue 08 Dec 17:52 CST 2020, Daniel Vetter wrote:
> >
> > > On Tue, Dec 08, 2020 at 04:02:16PM -0600, Bjorn Andersson wrote:
> > > > On Tue 08 Dec 06:47 CST 2020,
On Thu, Dec 10, 2020 at 4:43 PM Tomi Valkeinen wrote:
>
> On 10/12/2020 17:27, Daniel Vetter wrote:
>
> >> diff --git a/drivers/gpu/drm/drm_fb_helper.c
> >> b/drivers/gpu/drm/drm_fb_helper.c
> >> index e82db0f4e771..80e3797f0f01 100644
> >> --- a/drivers/gpu/drm/drm_fb_helper.c
> >> +++
On Thu, Dec 10, 2020 at 04:27:39PM +0100, Daniel Vetter wrote:
> On Thu, Dec 10, 2020 at 04:08:51PM +0200, Tomi Valkeinen wrote:
> > To support legacy gamma ioctls the drivers need to set
> > drm_crtc_funcs.gamma_set either to a custom implementation or to
> > drm_atomic_helper_legacy_gamma_set.
On Thu, Dec 10, 2020 at 10:56 AM Daniel Vetter wrote:
>
> On Thu, Dec 10, 2020 at 4:45 PM Simon Ser wrote:
> > On Wednesday, December 9th, 2020 at 8:40 PM, Daniel Vetter
> > wrote:
> > > > But it's not enough, can't have two CRTCs with the same primary plane.
> > > > Well,
> > > > I give up,
From: CK Hu
Some ddp component exist in both display path and other path, so
sub driver should not directly call DRM driver's function. Moving
mtk_ddp_comp_init() from sub driver to DRM driver to achieve this.
Signed-off-by: CK Hu
Signed-off-by: Chun-Kuang Hu
---
From: CK Hu
Some ddp component exist in both display path and other path, so
sub driver should not directly call DRM driver's function. Let
DRM driver directly refer to sub driver's function so that sub
driver need not register these function to DRM driver.
Signed-off-by: CK Hu
Signed-off-by:
From: CK Hu
Some ddp component exist in both display path and other path, so
sub driver interface should get rid of display info. Using device
instead of mtk_ddp_comp make interface general.
Signed-off-by: CK Hu
Signed-off-by: Chun-Kuang Hu
---
drivers/gpu/drm/mediatek/mtk_disp_color.c |
From: CK Hu
Some ddp component exist in both display path and other path, so
sub driver should not directly call crtc function. crtc register
callback function to sub driver to prevent sub driver directly
call crtc function.
Signed-off-by: CK Hu
Signed-off-by: Chun-Kuang Hu
---
From: CK Hu
Some ddp component exist in both display path and other path, so data
belonged to sub driver should be moved into sub driver private data so it
could be used for multiple path. cmdq_reg info is one of sub driver data,
so move it.
Signed-off-by: CK Hu
Signed-off-by: Chun-Kuang Hu
From: CK Hu
struct cmdq_client_reg include subsys and offset, so use it to replace
these two variable.
Signed-off-by: CK Hu
Signed-off-by: Chun-Kuang Hu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 26 ++---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 4 ++--
2 files
From: CK Hu
irq in struct mtk_ddp_comp is useless, so remove it.
Signed-off-by: CK Hu
Signed-off-by: Chun-Kuang Hu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
From: CK Hu
Some ddp component exist in both display path and other path, so data
belonged to sub driver should be moved into sub driver private data so it
could be used for multiple path. regs info is one of sub driver data, so
move it.
Signed-off-by: CK Hu
Signed-off-by: Chun-Kuang Hu
---
From: CK Hu
Some ddp component exist in both display path and other path, so data
belonged to sub driver should be moved into sub driver private data so it
could be used for multiple path. clk info is one of sub driver data, so
move it.
Signed-off-by: CK Hu
Signed-off-by: Chun-Kuang Hu
---
From: CK Hu
To make the code cleaner, separate getting larb device to
a function.
Signed-off-by: CK Hu
Signed-off-by: Chun-Kuang Hu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 57 -
1 file changed, 32 insertions(+), 25 deletions(-)
diff --git
Some ddp component use mmsys device pointer to get CMDQ client
register, this would get mmsys' CMDQ client register, so use
each ddp component's device pointer to get.
Signed-off-by: Chun-Kuang Hu
---
drivers/gpu/drm/mediatek/mtk_disp_color.c | 2 +-
drivers/gpu/drm/mediatek/mtk_disp_ovl.c
Only OVL, RDMA,and WDMA get CMDQ client register information,
but all ddp component should work with CMDQ, so get this
information for all ddp component.
Signed-off-by: Chun-Kuang Hu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 29 +++--
1 file changed, 15 insertions(+), 14
mtk ccorr is controlled by DRM and MDP [1]. In order to share
mtk_ccorr driver for DRM and MDP, decouple Mediatek DRM sub driver
which include mtk_ccorr, so MDP could use this decoupled mtk_ccorr.
Changes in v2:
1. Fix iommu larb problem.
2. Based on mediatek-drm-next-5.11-2 [2].
[1]
On Thursday, December 10th, 2020 at 4:56 PM, Daniel Vetter
wrote:
> Huh so crtc are registered forward and planes backward? I guess adding
> amd people. And yeah sounds like defacto you can't figure out which
> primary plane goes to which crtc, and we just take whatever goes.
> Maybe that
On Thu, Dec 10, 2020 at 4:45 PM Simon Ser wrote:
> On Wednesday, December 9th, 2020 at 8:40 PM, Daniel Vetter
> wrote:
> > > But it's not enough, can't have two CRTCs with the same primary plane.
> > > Well,
> > > I give up, it's just simpler to use Daniel's criteria.
> >
> > Yeah, also with
If a CRTC is missing a legacy primary plane pointer, a lot of things
will be broken for user-space: fbdev stops working and the entire legacy
uAPI stops working.
Require all drivers to populate drm_crtc.primary to prevent these
issues. Warn if it's NULL.
Signed-off-by: Simon Ser
Cc: Daniel
If a primary or cursor plane is not compatible with a CRTC it's attached
to via the legacy primary/cursor field, things will be broken for legacy
user-space.
Signed-off-by: Simon Ser
Cc: Daniel Vetter
Cc: Pekka Paalanen
---
drivers/gpu/drm/drm_mode_config.c | 16
1 file
The previous wording could be understood by user-space evelopers as "a
primary/cursor plane is only compatible with a single CRTC" [1].
Reword the planes description to make it clear the DRM-internal
drm_crtc.primary and drm_crtc.cursor planes are for legacy uAPI.
[1]:
Hi, Yongqiang:
Yongqiang Niu 於 2020年12月10日 週四 下午5:08寫道：
>
> This patch add RDMA fifo size error handle
> rdma fifo size will not always bigger than the calculated threshold
> if that case happened, we need set fifo size as the threshold
>
> Signed-off-by: Yongqiang Niu
> ---
>
Additional note, I don't really want to add the same check for cursor
planes, because I don't want to forbid a driver from having the CRTC
without a cursor plane and the second CRTC with a cursor plane. I don't
know if such heterogeneous hardware exists, but it sounds like
something we should be
On Wednesday, December 9th, 2020 at 8:40 PM, Daniel Vetter
wrote:
> > But it's not enough, can't have two CRTCs with the same primary plane. Well,
> > I give up, it's just simpler to use Daniel's criteria.
>
> Yeah, also with the validation check we'll now real quick if any driver
> gets it
Hi, Yongqiang:
Yongqiang Niu 於 2020年12月10日 週四 下午5:22寫道：
>
> rdma fifo size may be different even in same SOC, add this
> property to the corresponding rdma
>
> Signed-off-by: Yongqiang Niu
> ---
> .../bindings/display/mediatek/mediatek,disp.txt | 16
>
> 1 file
Parts of the initialization that do not require the drm device can be
done once during probe instead of possibly multiple times during bind.
The bind function only creates the encoder.
Signed-off-by: Philipp Zabel
Acked-by: Daniel Vetter
---
drivers/gpu/drm/imx/parallel-display.c | 42
Use drmm_universal_plane_alloc() to align plane memory lifetime with
the drm device. drm_plane_cleanup() is called automatically before the
memory is freed.
Also move the call to ipu_plane_get_resources() into ipu_plane_init()
and use drm managed resources to put IPU resources automatically when
Parts of the initialization that do not require the drm device can be
done once during probe instead of possibly multiple times during bind.
The bind function only creates the encoder.
Signed-off-by: Philipp Zabel
Acked-by: Daniel Vetter
---
drivers/gpu/drm/imx/imx-tve.c | 42
Add an alternative to drm_universal_plane_init() that allocates
and initializes a plane and registers drm_plane_cleanup() with
drmm_add_action_or_reset().
Signed-off-by: Philipp Zabel
Reviewed-by: Laurent Pinchart
Reviewed-by: Daniel Vetter
---
Changes since v4:
- Mention that
Use drmm_simple_encoder_alloc() to align encoder memory lifetime with
the drm device. drm_encoder_cleanup() is called automatically before
the memory is freed.
Signed-off-by: Philipp Zabel
Acked-by: Daniel Vetter
---
drivers/gpu/drm/imx/parallel-display.c | 57 +-
1
Use drmm_simple_encoder_alloc() to align encoder memory lifetime with
the drm device. drm_encoder_cleanup() is called automatically before
the memory is freed.
Also fold imx_tve_register() into imx_tve_bind().
Signed-off-by: Philipp Zabel
Acked-by: Daniel Vetter
---
Introduce local variables for encoder and connector.
This simplifies the following commits.
Signed-off-by: Philipp Zabel
Acked-by: Daniel Vetter
---
drivers/gpu/drm/imx/imx-tve.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/imx/imx-tve.c
Avoid leaking the clock provider when the driver is unbound.
Signed-off-by: Philipp Zabel
Acked-by: Daniel Vetter
---
drivers/gpu/drm/imx/imx-tve.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/imx/imx-tve.c b/drivers/gpu/drm/imx/imx-tve.c
index
Add an alternative to drm_crtc_init_with_planes() that allocates
and initializes a crtc and registers drm_crtc_cleanup() with
drmm_add_action_or_reset().
Signed-off-by: Philipp Zabel
Reviewed-by: Laurent Pinchart
Reviewed-by: Daniel Vetter
---
Changes since v4:
- Mention that
Use local variables for bridge and connector.
This simplifies the following commits.
Signed-off-by: Philipp Zabel
Acked-by: Daniel Vetter
---
drivers/gpu/drm/imx/parallel-display.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git
Add an alternative to drm_encoder_init() that allocates and initializes
an encoder and registers drm_encoder_cleanup() with
drmm_add_action_or_reset().
Signed-off-by: Philipp Zabel
Reviewed-by: Laurent Pinchart
Reviewed-by: Daniel Vetter
---
Changes since v4:
- mention that
Use drmm_simple_encoder_alloc() to align encoder memory lifetime with
the drm device. drm_encoder_cleanup() is called automatically.
Signed-off-by: Philipp Zabel
Acked-by: Daniel Vetter
---
drivers/gpu/drm/imx/dw_hdmi-imx.c | 25 +
1 file changed, 17 insertions(+), 8
Use use drmm_crtc_alloc_with_planes() to align crtc memory lifetime
with the drm device. drm_crtc_cleanup() is called automatically before
the memory is freed.
Also use drmm_add_action_or_reset() to make sure IPU resources are
released automatically.
Signed-off-by: Philipp Zabel
Acked-by: Daniel
Use a local variable for the connector.
This simplifies the following commits.
Signed-off-by: Philipp Zabel
Acked-by: Daniel Vetter
---
drivers/gpu/drm/imx/imx-ldb.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/imx/imx-ldb.c
Use drmm_simple_encoder_alloc() to align encoder memory lifetime with
the drm device. drm_encoder_cleanup() is called automatically before
the memory is freed.
Signed-off-by: Philipp Zabel
Acked-by: Daniel Vetter
---
drivers/gpu/drm/imx/imx-ldb.c | 31 ++-
1 file
Parts of the initialization that do not require the drm device can be
done once during probe instead of possibly multiple times during bind.
The bind function only creates the encoder and attaches the bridge.
Signed-off-by: Philipp Zabel
Acked-by: Daniel Vetter
---
Parts of the initialization that do not require the drm device can be
done once during probe instead of possibly multiple times during bind.
The bind function only creates the encoders.
Signed-off-by: Philipp Zabel
Acked-by: Daniel Vetter
---
drivers/gpu/drm/imx/imx-ldb.c | 72
Add an alternative to drm_simple_encoder_init() that allocates and
initializes a simple encoder and registers drm_encoder_cleanup() with
drmm_add_action_or_reset().
Signed-off-by: Philipp Zabel
Reviewed-by: Laurent Pinchart
Reviewed-by: Daniel Vetter
---
Changes since v4:
- address FIXME in
Hi,
update of v4 [1] with review feedback integrated.
Changes since v4:
- Roll back drm_mode_config_cleanup() change, any encoders that are
kept on the mode_config.encoder_list until then are still required
to have funcs set.
- Mention that {encoder,plane,crtc}_funcs.destroy should
Simple managed encoders do not require the .destroy callback,
make the whole funcs structure optional.
Signed-off-by: Philipp Zabel
Reviewed-by: Laurent Pinchart
Reviewed-by: Daniel Vetter
---
Changes since v4:
- Roll back drm_mode_config_cleanup() change, any encoders that are
kept on the
Hi, Yongqiang:
Yongqiang Niu 於 2020年12月10日 週四 下午5:22寫道：
>
> add description for mt8183 display
Reviewed-by: Chun-Kuang Hu
>
> Signed-off-by: Yongqiang Niu
> ---
> Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>
On Thu, Dec 10, 2020 at 04:08:51PM +0200, Tomi Valkeinen wrote:
> To support legacy gamma ioctls the drivers need to set
> drm_crtc_funcs.gamma_set either to a custom implementation or to
> drm_atomic_helper_legacy_gamma_set. Most of the atomic drivers do the
> latter.
>
> We can simplify this by
Based on an idea from Dave, but cleaned up a bit.
We had multiple fields for essentially the same thing.
Now bo->base.size is the original size of the BO in
arbitrary units, usually bytes.
bo->mem.num_pages is the size in number of pages in the
resource domain of bo->mem.mem_type.
v2: use the
Hi all,
This patch set is a continuation of my previous work, which aimed
to add Energy Model to all devices [1]. This series is a follow up
for the patches which got merged to v5.9-rc1. It aims to change
the thermal devfreq cooling and use the Energy Model instead of
private power table and
On Fri, Dec 04, 2020 at 04:11:36PM +0100, Maxime Ripard wrote:
> @@ -893,12 +890,17 @@ static int vc4_pv_muxing_atomic_check(struct drm_device
> *dev,
> struct vc4_hvs_state *hvs_new_state;
> struct drm_crtc_state *old_crtc_state, *new_crtc_state;
> struct drm_crtc *crtc;
> +
From: Dom Cobley
Currently we call cec_phys_addr_invalidate on a hotplug deassert.
That may be due to a TV power cycling, or an AVR being switched
on (and switching edid).
This makes CEC unusable since our controller wouldn't have a physical
address anymore.
Set it back up again on the hotplug
As part of the enable sequence we might change the HSM clock rate if the
pixel rate is different than the one we were already dealing with.
On the BCM2835 however, the CEC clock derives from the HSM clock so any
rate change will need to be reflected in the CEC clock divider to output
40kHz.
The BCM2711 has two different interrupt sources to transmit and receive
CEC messages, provided through an external interrupt chip shared between
the two HDMI interrupt controllers.
The rest of the CEC controller is identical though so we need to change
a bit the code organisation to share the
add description for mt8183 display
Signed-off-by: Yongqiang Niu
---
Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
The CEC clock divider needs to output a frequency of 40kHz from the HSM
rate on the BCM2835. The driver used to have a fixed frequency for it,
but that changed and we now need to compute it dynamically to maintain
the proper rate.
Fixes: cd4cb49dc5bb ("drm/vc4: hdmi: Adjust HSM clock rate
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