Use new macro to create a sysfs control bitmap knob to control
print-to-trace in: /sys/module/drm/parameters/trace
todo: reconsider this api, ie a single macro expecting both debug &
trace terms (2 each), followed by a single description and the
bitmap-spec::
Good: declares bitmap once for both
clone DEFINE_DYNAMIC_DEBUG_CATEGORIES interface to enable pr_debug
output to tracefs.
Extend DEFINE_DYNAMIC_DEBUG_CATEGORIES to work for tracing, by
renaming it (with _FLAGS suffix), adding _flags param, and using it
2x; in original and new names, with "p" and "T" flags respectively.
TODO:
drm's debug system writes 10 distinct categories of messages to syslog
using a small API[1]: drm_dbg*(10 names), DRM_DEV_DEBUG*(3 names),
DRM_DEBUG*(8 names). There are thousands of these callsites, each
categorized in this systematized way.
These callsites can be enabled at runtime by their
Sean Paul proposed, in:
https://patchwork.freedesktop.org/series/78133/
drm/trace: Mirror DRM debug logs to tracefs
His patchset's objective is to be able to independently steer some of
the drm.debug stream to an alternate tracing destination, by splitting
drm_debug_enabled() into syslog & trace
Duplicate drm_debug_enabled() code into both "basic" and "dyndbg"
ifdef branches. Then add a pr_debug("todo: ...") into the "dyndbg"
branch.
Then convert the "dyndbg" branch's code to a macro, so that the
pr_debug() get its callsite info from the invoking function, instead
of from
Taking embedded spaces out of existing prefixes makes them better
class-prefixes; simplifying the extra quoting needed otherwise:
$> echo format "^gvt: core:" +p >control
Dropping the internal spaces means any trailing space in a query will
more clearly terminate the prefix being searched for.
The gvt component of this driver has ~120 pr_debugs, in 9 categories
quite similar to those in DRM. Following the interface model of
drm.debug, add a parameter to map bits to these categorizations.
DEFINE_DYNAMIC_DEBUG_CATEGORIES(debug_gvt, __gvt_debug,
"dyndbg bitmap desc",
[0]
logger_types.h defines many DC_LOG_*() categorized debug wrappers.
Most of these already use DRM debug API, so are controllable using
drm.debug, but others use a bare pr_debug("$prefix: .."), with 1 of 13
different class-prefixes matching [:uppercase:]
Use DEFINE_DYNAMIC_DEBUG_CATEGORIES to
allocates and initializes ...
Signed-off-by: Jim Cromie
---
include/drm/drm_drv.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/drm/drm_drv.h b/include/drm/drm_drv.h
index 0cd95953cdf5..4b29261c4537 100644
--- a/include/drm/drm_drv.h
+++ b/include/drm/drm_drv.h
@@
DEFINE_DYNAMIC_DEBUG_CATEGORIES(fsname, var, bitmap_desc, @bit_descs)
allows users to create a drm.debug style (bitmap) sysfs interface,
mapping each bit to a pr_debug "category".
Unlike drm, dyndbg has no coding of "category", but it can select a
set of pr_debugs with a substr match on their
This patchset has 3 separate but related parts:
1. DEFINE_DYNAMIC_DEBUG_CATEGORIES [patch 1/10]
Declares DRM.debug style bitmap, bits control pr_debugs by matching formats
Adds callback to translate bits to $cmd > dynamic_debug/control
This could obsolete
Hi AngeloGioacchino,
Thanks for your suggestion.
On Thu, 2021-10-14 at 12:35 +0200, AngeloGioacchino Del Regno wrote:
> > For lat and core architecture, lat thread will send message to core
> > thread when lat decode done. Core hardware will use the message
> > from lat to decode, then free
Hi AngeloGioacchino,
Thanks for your suggestion.
On Thu, 2021-10-14 at 12:44 +0200, AngeloGioacchino Del Regno wrote:
> > Generalizes power and clock on/off interfaces to support different
> > hardware.
> >
> > Signed-off-by: Yunfei Dong
> > ---
> >
Hi AngeloGioacchino,
Thanks for your suggestion.
On Thu, 2021-10-14 at 12:56 +0200, AngeloGioacchino Del Regno wrote:
> > Core thread:
> > 1. Gets lat_buf from core msg queue.
> > 2. Proceeds core decode.
> > 3. Puts the lat_buf back to lat msg queue.
> >
> > Both H264 and VP9 rely on the core
Hi AngeloGioacchino,
Thanks for your suggestion.
On Thu, 2021-10-14 at 13:02 +0200, AngeloGioacchino Del Regno wrote:
> > Use the dma_set_mask_and_coherent helper to set vdec
> > DMA bit mask to support 34bits iova space(16GB) that
> > the mt8192 iommu HW support.
> >
> > Whole the iova range
Hi Thomas,
I have tested the fix patch [1] and it works fine for me.
> Could you please try the patch at [1]? It fixes the problem for me.
Pass: 6d61a7c3bc2a ("arm: multi_v5_defconfig build fix")
arm (multi_v5_defconfig) with gcc-11
@ https://builds.tuxbuild.com/204SnLe1DFWQ4iAHpwAMiyUcpsL/
On Tue, 19 Oct 2021 08:52:38 +0200, Alexander Stein wrote:
> Add a VCC regulator which needs to be enabled before the EN pin is
> released.
>
> Reviewed-by: Sam Ravnborg
> Signed-off-by: Alexander Stein
> ---
> .../devicetree/bindings/display/bridge/ti,sn65dsi83.yaml | 4
> 1 file
On Tue, 19 Oct 2021 08:52:36 +0200, Alexander Stein wrote:
> From: Laurent Pinchart
>
> The SN65DSI8x EN signal may be tied to VCC, or otherwise controlled by
> means not available to the kernel. Make the GPIO optional.
>
> Signed-off-by: Laurent Pinchart
> Signed-off-by: Alexander Stein
>
These refinements include using standard mailbox callback interface,
timeout detection, and a fixed cmdq_handle.
Change in v5:
1. Move mbox_free_channel to a independent patch.
Change in v4:
1. Add cmdq_vblank_cnt initial value to 3.
2. Move mtk_drm_cmdq_pkt_create to the same define scope with
From: Chun-Kuang Hu
In mailbox rx_callback, it pass struct mbox_client to callback
function, but it could not map back to mtk_drm_crtc instance
because struct cmdq_client use a pointer to struct mbox_client:
struct cmdq_client {
struct mbox_client client;
struct mbox_chan *chan;
From: Yongqiang Niu
In cmdq mode, packet may be flushed before it is executed, so
the pending flag should be cleared after cmdq packet is done.
Signed-off-by: Yongqiang Niu
Signed-off-by: jason-jh.lin
Reviewed-by: Chun-Kuang Hu
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 51
From: Chun-Kuang Hu
rx_callback is a standard mailbox callback mechanism and could cover the
function of proprietary cmdq_task_cb, so use the standard one instead of
the proprietary one.
Signed-off-by: Chun-Kuang Hu
Signed-off-by: jason-jh.lin
Reviewed-by: Chun-Kuang Hu
---
From: Chun-Kuang Hu
CMDQ is used to update display register in vblank period, so
it should be execute in next 2 vblank. One vblank interrupt
before send message (occasionally) and one vblank interrupt
after cmdq done. If it fail to execute in next 3 vblank,
tiemout happen.
Signed-off-by:
Add mbox_free_channel in mtk_drm_crtc_destroy.
Signed-off-by: jason-jh.lin
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index ffa54b416ca7..31f05efc1bc0
From: Chun-Kuang Hu
One mtk_crtc need just one cmdq_handle, so add one cmdq_handle
in mtk_crtc to prevent frequently allocation and free of
cmdq_handle.
Signed-off-by: Chun-Kuang Hu
Signed-off-by: jason-jh.lin
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 62 +++--
1 file
On Mon, Oct 18, 2021 at 04:40:03PM +0200, AngeloGioacchino Del Regno wrote:
> Convert the Toshiba TC358764 txt documentation to YAML.
>
> Signed-off-by: AngeloGioacchino Del Regno
>
> ---
> Note: dtbs_check on exynos5250-arndale.dts will give some warnings after
> applying this patch:
Hi,
This bug can still be triggered repeatedly on the latest Linux.
HEAD commit: 519d81956ee2 Linux 5.15-rc6
git tree: upstream
console output:
https://drive.google.com/file/d/17xFIX8JgBxamy8iUnUTAdcVvaASuhqxr/view?usp=sharing
kernel config:
Hi Geert,
On 10/26/2021 1:12 PM, Geert Uytterhoeven wrote:
Hi George,
On Tue, Oct 26, 2021 at 5:48 PM George Kennedy
wrote:
On 10/26/2021 10:11 AM, Geert Uytterhoeven wrote:
On Tue, Oct 26, 2021 at 3:38 PM George Kennedy
wrote:
On 10/26/2021 4:30 AM, Geert Uytterhoeven wrote:
On Mon, Oct
On 10/26/21 11:21 AM, Thomas Zimmermann wrote:
Hi
Am 25.10.21 um 14:13 schrieb Naresh Kamboju:
Regression found on arm gcc-11 built with multi_v5_defconfig
Following build warnings / errors reported on linux next 20211025.
metadata:
git_describe: next-20211025
git_repo:
With GuC handling scheduling, i915 is not aware of the time that a
context is scheduled in and out of the engine. Since i915 pmu relies on
this info to provide engine busyness to the user, GuC shares this info
with i915 for all engines using shared memory. For each engine, this
info contains:
-
In preparation for GuC pmu stats, add a name to the execlists stats
structure so that it can be differentiated from the GuC stats.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 14 +++---
drivers/gpu/drm/i915/gt/intel_engine_stats.h | 33 +++--
Hi All,
I have an application I'm working on where I'm using OpenGLES / EGL and
dri/drm/kms. The main loop of my application looks like the code below. When
running htop, I see that the number of minor faults (memory) are increasing
over time at a rate of about 500 per second, due to the code
Hi Stephen,
I love your patch! Yet something to improve:
[auto build test ERROR on e4e737bb5c170df6135a127739a9e6148ee3da82]
url:
https://github.com/0day-ci/linux/commits/Stephen-Boyd/component-Make-into-an-aggregate-bus/20211026-080422
base: e4e737bb5c170df6135a127739a9e6148ee3da82
On Tue, Oct 19, 2021 at 04:39:05PM +0200, Marek Vasut wrote:
> On 10/19/21 8:49 AM, Laurent Pinchart wrote:
> > Hi Marek,
>
> Hi,
>
> >> diff --git
> >> a/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml
> >>
On Mon, 18 Oct 2021 08:40:12 +0200, Michal Simek wrote:
> Commit cea0f76a483d ("dt-bindings: phy: Add DT bindings for Xilinx ZynqMP
> PSGTR PHY") clearly defines #phy-cells as 4. In past 5 cells were used by
> it never went to upstream. That's why fix example by using only 4 cells
> instead of 5.
On Mon, 18 Oct 2021 11:03:23 +0800, Xin Ji wrote:
> Add 'bus-type' and 'data-lanes' define for port0. Add DP tx lane0,
> lane1 swing register setting array, and audio enable flag.
>
> The device which cannot pass DP tx PHY CTS caused by long PCB trace or
> embedded MUX, adjusting ANX7625 PHY
Hi Andrzej,
On Mon, Oct 25, 2021 at 10:11:47PM +0200, Andrzej Hajda wrote:
> On 25.10.2021 13:21, Laurent Pinchart wrote:
> > On Mon, Oct 25, 2021 at 01:00:10PM +0200, Andrzej Hajda wrote:
> >> On 21.10.2021 22:21, Sam Ravnborg wrote:
> >>> On Thu, Oct 21, 2021 at 12:29:01PM -0700, Douglas
Hi Julian,
Thank you for the patch.
On Mon, Oct 25, 2021 at 10:36:38PM -0400, Julian Braha wrote:
> When DRM_CHIPONE_ICN6211 is selected, and DRM_KMS_HELPER is not selected,
> Kbuild gives the following warning:
>
> WARNING: unmet direct dependencies detected for DRM_PANEL_BRIDGE
> Depends on
21. 10. 27. 오전 7:28에 Inki Dae 이(가) 쓴 글:
> Hi,
>
> 21. 10. 17. 오전 3:42에 Claudio Suarez 이(가) 쓴 글:
>> Once EDID is parsed, the monitor HDMI support information is available
>> through drm_display_info.is_hdmi. Retriving the same information with
>> drm_detect_hdmi_monitor() is less efficient.
Hi Dave & Daniel,
This is the main pull for v5.16:
* eDP support in DP sub-driver (for newer SoCs with native eDP output)
* dpu irq handling cleanup
* CRC support for making igt happy
* Support for NO_CONNECTOR bridges
* dsi: 14nm phy support for msm8953
* mdp5: support for msm8x53, sdm450,
Hi,
21. 10. 17. 오전 3:42에 Claudio Suarez 이(가) 쓴 글:
> Once EDID is parsed, the monitor HDMI support information is available
> through drm_display_info.is_hdmi. Retriving the same information with
> drm_detect_hdmi_monitor() is less efficient. Change to
> drm_display_info.is_hdmi
>
>
Now that we've added support to i915 for controlling panel backlights that
need PWM to be enabled/disabled, let's finalize this and add support for
controlling brightness levels via PWM as well. This should hopefully put us
towards the path of supporting _ALL_ backlights via VESA's DPCD interface
Hooray! We've managed to hit enough bugs upstream that I've been able to
come up with a pretty solid explanation for how backlight controls are
actually supposed to be detected and used these days. As well, having the
rest of the PWM bits in VESA's backlight interface implemented seems to
have
As it turns out, apparently some machines will actually leave additional
backlight functionality like dynamic backlight control on before the OS
loads. Currently we don't take care to disable unsupported features when
writing back the backlight mode, which can lead to some rather strange
looking
Since we don't support hybrid AUX/PWM backlights in nouveau right now,
let's add some explicit checks so that we don't break nouveau once we
enable support for these backlights in other drivers.
Signed-off-by: Lyude Paul
---
drivers/gpu/drm/nouveau/nouveau_backlight.c | 5 -
1 file changed,
This simply adds proper support for panel backlights that can be controlled
via VESA's backlight control protocol, but which also require that we
enable and disable the backlight via PWM instead of via the DPCD interface.
We also enable this by default, in order to fix some people's backlights
When I originally moved all of the VESA backlight code in i915 into DRM
helpers, one of the things I didn't have the hardware or time for
testing was machines that used a combination of PWM and DPCD in order to
control their backlights. This has since then caused some breakages and
resulted in us
On 10/20/2021 14:47, Matthew Brost wrote:
A weak implementation of parallel submission (multi-bb execbuf IOCTL) for
execlists. Doing as little as possible to support this interface for
execlists - basically just passing submit fences between each request
generated and virtual engines are not
Conventionally, panel is listed under the root of the device tree.
When userland asks for display mode, ps8640 bridge is responsible
for returning EDID when ps8640_bridge_get_edid() is called.
Now enable a new option of listing panel under "aux-bus" of ps8640
bridge node in the device tree. In
Fit ps8640 driver into runtime power management framework:
First, break _poweron() to 3 parts: (1) turn on power and wait for
ps8640's internal MCU to finish init (2) check panel HPD (which is
proxied by GPIO9) (3) the other configs. As runtime_resume() can be
called before panel is powered, we
Hi "Maíra,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on lee-backlight/for-backlight-next]
[also build test ERROR on v5.15-rc7 next-20211026]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest t
Hi
On Tue, Oct 26, 2021 at 12:36 PM Stephen Boyd wrote:
>
> Quoting Philip Chen (2021-10-26 12:11:09)
> > Fit ps8640 driver into runtime power management framework:
> >
> > First, break _poweron() to 3 parts: (1) turn on power and wait for
> > ps8640's internal MCU to finish init (2) check panel
On 10/21/2021 23:23, Thomas Hellström wrote:
On 10/21/21 22:37, Matthew Brost wrote:
On Thu, Oct 21, 2021 at 08:15:49AM +0200, Thomas Hellström wrote:
Hi, Matthew,
On Mon, 2021-10-11 at 16:47 -0700, Matthew Brost wrote:
The hangcheck selftest blocks per engine resets by setting magic bits
in
On 10/11/2021 16:47, Matthew Brost wrote:
The hangcheck selftest blocks per engine resets by setting magic bits in
the reset flags. This is incorrect for GuC submission because if the GuC
fails to reset an engine we would like to do a full GT reset. Do no set
these magic bits when using GuC
Quoting Philip Chen (2021-10-26 12:11:09)
> Fit ps8640 driver into runtime power management framework:
>
> First, break _poweron() to 3 parts: (1) turn on power and wait for
> ps8640's internal MCU to finish init (2) check panel HPD (which is
> proxied by GPIO9) (3) the other configs. As
Comments below
On Tue, 2021-10-26 at 03:50 +, Lin, Wayne wrote:
> [Public]
>
> Hi Lyude!
> Apologize for replying late and really thanks for elaborating in such
> details!
> Following are some of my thoughts : )
>
> > -Original Message-
> > From: Lyude Paul
> > Sent: Saturday,
Quoting kernel test robot (2021-10-26 07:02:03)
>
>drivers/base/component.c: In function '__component_add':
> >> drivers/base/component.c:858:13: error: variable 'ret' set but not used
> >> [-Werror=unused-but-set-variable]
> 858 | int ret;
> | ^~~
>cc1:
new patch: https://patchwork.freedesktop.org/series/96314/
On Tue, Oct 26, 2021 at 3:24 PM Mark Yacoub wrote:
>
> On Tue, Oct 26, 2021 at 8:02 AM Paul Menzel wrote:
> >
> > Dear Mark,
> >
> >
> > Thank you for your patch.
> >
> > On 13.10.21 20:12, Mark Yacoub wrote:
> > > From: Mark Yacoub
>
On Mon, Oct 25, 2021 at 9:26 PM Sean Paul wrote:
>
> On Wed, Oct 13, 2021 at 02:12:20PM -0400, Mark Yacoub wrote:
> > From: Mark Yacoub
> >
> > [Why]
> > 1. drm_atomic_helper_check doesn't check for the LUT sizes of either Gamma
> > or Degamma props in the new CRTC state, allowing any invalid
On Tue, Oct 26, 2021 at 8:02 AM Paul Menzel wrote:
>
> Dear Mark,
>
>
> Thank you for your patch.
>
> On 13.10.21 20:12, Mark Yacoub wrote:
> > From: Mark Yacoub
> >
> > [Why]
> > 1. drm_atomic_helper_check doesn't check for the LUT sizes of either Gamma
> > or Degamma props in the new CRTC
From: Mark Yacoub
[Why]
drm_atomic_helper_check_crtc now verifies both legacy and non-legacy LUT
sizes. There is no need to check it within amdgpu_dm_atomic_check.
[How]
Remove the local call to verify LUT sizes and use DRM Core function
instead.
Tested on ChromeOS Zork.
v1:
Remove
From: Mark Yacoub
[Why]
1. drm_atomic_helper_check doesn't check for the LUT sizes of either Gamma
or Degamma props in the new CRTC state, allowing any invalid size to
be passed on.
2. Each driver has its own LUT size, which could also be different for
legacy users.
[How]
1. Create
From: Mark Yacoub
[Why]
This function and enum do not do generic checking on the luts but they
test color channels in the LUTs.
Keeping the name explicit as more generic LUT checks will follow.
Tested on Eldrid ChromeOS (TGL).
Signed-off-by: Mark Yacoub
---
drivers/gpu/drm/drm_color_mgmt.c
Hi
On Mon, Oct 25, 2021 at 1:05 PM Stephen Boyd wrote:
>
> Quoting Philip Chen (2021-10-21 14:05:59)
> > Fit ps8640 driver into runtime power management framework:
> >
> > First, break _poweron() to 3 parts: (1) turn on power and wait for
> > ps8640's internal MCU to finish init (2) check panel
Hi Nikolaus,
On Tue, Oct 26, 2021 at 08:50:19PM +0200, H. Nikolaus Schaller wrote:
> Hi Paul,
>
> > Am 26.10.2021 um 20:12 schrieb Paul Cercueil :
> >
> > Hi,
> >
> > I resend the V3 of my patchset for drm/ingenic, verbatim.
> >
> > The previous submission of my V3 received a lot of replies,
Conventionally, panel is listed under the root of the device tree.
When userland asks for display mode, ps8640 bridge is responsible
for returning EDID when ps8640_bridge_get_edid() is called.
Now enable a new option of listing panel under "aux-bus" of ps8640
bridge node in the device tree. In
Fit ps8640 driver into runtime power management framework:
First, break _poweron() to 3 parts: (1) turn on power and wait for
ps8640's internal MCU to finish init (2) check panel HPD (which is
proxied by GPIO9) (3) the other configs. As runtime_resume() can be
called before panel is powered, we
Hi Mario,
On Tue, Oct 26, 2021 at 01:27:37PM +0200, Mario wrote:
> Fixes screen orientation for GPD Win 3 handheld gaming console.
>
> Signed-off-by: Mario Risoldi
Thanks for the resend.
A couple of points for your, hopefully soonish, next contribution:
1) Use the same name/email in the
Hi,
On Mon, Oct 25, 2021 at 1:10 PM Stephen Boyd wrote:
>
> Quoting Philip Chen (2021-10-21 14:06:00)
> > diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c
> > b/drivers/gpu/drm/bridge/parade-ps8640.c
> > index 220ca3b03d24..f99a2e0808b7 100644
> > --- a/drivers/gpu/drm/bridge/parade-ps8640.c
Hi Stephen,
On 2021-10-21 23:32, Stephen Boyd wrote:
Quoting Sankeerth Billakanti (2021-10-20 05:14:10)
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c
b/drivers/gpu/drm/msm/dp/dp_ctrl.c
index 62e75dc..9fea49c 100644
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
Hi Paul,
> Am 26.10.2021 um 20:12 schrieb Paul Cercueil :
>
> Hi,
>
> I resend the V3 of my patchset for drm/ingenic, verbatim.
>
> The previous submission of my V3 received a lot of replies, but none of
> these replies were actually talking about the patches themselves.
Indeed. And since we
Hi Thomas,
On Tue, Oct 26, 2021 at 07:57:00PM +0200, Thomas Zimmermann wrote:
> Linking the CMA frambuffer helpers into a CMA helper library in
> commit 4b2b5e142ff4 ("drm: Move GEM memory managers into modules")
> results in linker errors:
>
> arm-linux-gnueabihf-ld:
Hi
Am 25.10.21 um 14:13 schrieb Naresh Kamboju:
Regression found on arm gcc-11 built with multi_v5_defconfig
Following build warnings / errors reported on linux next 20211025.
metadata:
git_describe: next-20211025
git_repo: https://gitlab.com/Linaro/lkft/mirrors/next/linux-next
Attach a top-level bridge to each encoder, which will be used for
negociating the bus format and flags.
All the bridges are now attached with DRM_BRIDGE_ATTACH_NO_CONNECTOR.
Signed-off-by: Paul Cercueil
---
drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 92 +--
1 file changed,
When using C8 color mode, make sure that the palette is always uploaded
before a frame; otherwise the very first frame will have wrong colors.
Do that by changing the link order of the DMA descriptors.
v3: Fix ingenic_drm_get_new_priv_state() called instead of
ingenic_drm_get_priv_state()
Setting the DMA descriptor chain register in the probe function has been
fine until now, because we only ever had one descriptor per foreground.
As the driver will soon have real descriptor chains, and the DMA
descriptor chain register updates itself to point to the current
descriptor being
Hi,
I resend the V3 of my patchset for drm/ingenic, verbatim.
The previous submission of my V3 received a lot of replies, but none of
these replies were actually talking about the patches themselves.
Cheers,
-Paul
Paul Cercueil (6):
drm/ingenic: Simplify code by using hwdescs array
The IPU scaling information is computed in the plane's ".atomic_check"
callback, and used in the ".atomic_update" callback. As such, it is
state-specific, and should be moved to a private state structure.
Signed-off-by: Paul Cercueil
---
drivers/gpu/drm/ingenic/ingenic-ipu.c | 73
Until now, the ingenic-drm as well as the ingenic-ipu drivers used to
put state-specific information in their respective private structure.
Add boilerplate code to support private objects in the two drivers, so
that state-specific information can be put in the state-specific private
structure.
Instead of having one 'hwdesc' variable for the plane #0, one for the
plane #1 and one for the palette, use a 'hwdesc[3]' array, where the
DMA hardware descriptors are indexed by the plane's number.
v2: dma_hwdesc_addr() extended to support palette hwdesc. The palette
hwdesc is now hwdesc[3]
Hi
Am 25.10.21 um 16:01 schrieb Naresh Kamboju:
On Mon, 25 Oct 2021 at 17:43, Naresh Kamboju wrote:
Regression found on arm gcc-11 built with multi_v5_defconfig
Following build warnings / errors reported on linux next 20211025.
metadata:
git_describe: next-20211025
git_repo:
Linking the CMA frambuffer helpers into a CMA helper library in
commit 4b2b5e142ff4 ("drm: Move GEM memory managers into modules")
results in linker errors:
arm-linux-gnueabihf-ld: drivers/gpu/drm/drm_fb_cma_helper.o: \
in function `drm_fb_cma_get_gem_obj': \
Hi "Thomas,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-tip/drm-tip]
[cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next
tegra-drm/drm/tegra/for-next airlied/drm-next v5.15-rc7 next-20211026]
[If your patch is applied to the wron
Hi George,
On Tue, Oct 26, 2021 at 5:48 PM George Kennedy
wrote:
> On 10/26/2021 10:11 AM, Geert Uytterhoeven wrote:
> > On Tue, Oct 26, 2021 at 3:38 PM George Kennedy
> > wrote:
> >> On 10/26/2021 4:30 AM, Geert Uytterhoeven wrote:
> >>> On Mon, Oct 25, 2021 at 9:37 PM George Kennedy
> >>>
sbios settings
given suggestion this may be a BIOS issue, I've posted this issue as a question
@,
https://forum.asrock.com/forum_posts.asp?TID=19749=x470d4u-p4-20-ryzen5600g-fatal-error-gpu-boot
and pinged ASRockRack tech support via their online tech supp form.
If anyone _here_ knows an
The huge page functionality in TTM does not work safely because PUD and
PMD entries do not have a special bit.
get_user_pages_fast() considers any page that passed pmd_huge() as
usable:
if (unlikely(pmd_trans_huge(pmd) || pmd_huge(pmd) ||
pmd_devmap(pmd))) {
And
Hi, Jason:
jason-jh.lin 於 2021年10月26日 週二 下午1:29寫道：
>
> From: Yongqiang Niu
>
> In cmdq mode, packet may be flushed before it is executed, so
> the pending flag should be cleared after cmdq packet is done.
Reviewed-by: Chun-Kuang Hu
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by:
Am 2021-10-25 um 12:16 a.m. schrieb Alistair Popple:
> MIGRATE_PFN_LOCKED is used to indicate to migrate_vma_prepare() that a
> source page was already locked during migrate_vma_collect(). If it
> wasn't then the a second attempt is made to lock the page. However if
> the first attempt failed it's
Hi, Jason:
jason-jh.lin 於 2021年10月26日 週二 下午1:29寫道：
>
> From: Chun-Kuang Hu
>
> One mtk_crtc need just one cmdq_handle, so add one cmdq_handle
> in mtk_crtc to prevent frequently allocation and free of
> cmdq_handle.
>
> Signed-off-by: Chun-Kuang Hu
> Signed-off-by: jason-jh.lin
> ---
>
On 2021-10-21 at 17:27:08 +0300, Lisovskiy, Stanislav wrote:
> On Thu, Oct 21, 2021 at 07:56:23PM +0530, Ramalingam C wrote:
> > From: Stanislav Lisovskiy
> >
> > TileF(Tile4 in bspec) format is 4K tile organized into
> > 64B subtiles with same basic shape as for legacy TileY
> > which will be
Hi, Jason:
jason-jh.lin 於 2021年10月26日 週二 下午1:29寫道：
>
> From: Chun-Kuang Hu
>
> CMDQ is used to update display register in vblank period, so
> it should be execute in next 2 vblank. One vblank interrupt
> before send message (occasionally) and one vblank interrupt
> after cmdq done. If it fail
Hi, Jason:
jason-jh.lin 於 2021年10月26日 週二 下午1:29寫道：
>
> From: Chun-Kuang Hu
>
> In mailbox rx_callback, it pass struct mbox_client to callback
> function, but it could not map back to mtk_drm_crtc instance
> because struct cmdq_client use a pointer to struct mbox_client:
>
> struct cmdq_client {
On Tue, Oct 26, 2021 at 11:59:35AM +0300, Joonas Lahtinen wrote:
> Quoting Matthew Brost (2021-10-25 18:15:09)
> > On Mon, Oct 25, 2021 at 12:37:02PM +0300, Joonas Lahtinen wrote:
> > > Quoting Matthew Brost (2021-10-22 19:42:19)
> > > > On Fri, Oct 22, 2021 at 12:35:04PM +0300, Joonas Lahtinen
Hi, Jason:
jason-jh.lin 於 2021年10月26日 週二 下午1:29寫道：
>
> From: Chun-Kuang Hu
>
> rx_callback is a standard mailbox callback mechanism and could cover the
> function of proprietary cmdq_task_cb, so use the standard one instead of
> the proprietary one.
Reviewed-by: Chun-Kuang Hu
>
>
On Tue, Oct 26, 2021 at 11:59:35AM +0300, Joonas Lahtinen wrote:
> Quoting Matthew Brost (2021-10-25 18:15:09)
> > On Mon, Oct 25, 2021 at 12:37:02PM +0300, Joonas Lahtinen wrote:
> > > Quoting Matthew Brost (2021-10-22 19:42:19)
> > > > On Fri, Oct 22, 2021 at 12:35:04PM +0300, Joonas Lahtinen
Hi Geert,
On 10/26/2021 10:11 AM, Geert Uytterhoeven wrote:
Hi George,
On Tue, Oct 26, 2021 at 3:38 PM George Kennedy
wrote:
On 10/26/2021 4:30 AM, Geert Uytterhoeven wrote:
On Mon, Oct 25, 2021 at 9:37 PM George Kennedy
wrote:
On 10/25/2021 3:07 PM, Greg KH wrote:
On Mon, Oct 25, 2021
On 2021-10-25 at 14:20:02 +0300, Juha-Pekka Heikkila wrote:
> On 21.10.2021 17.35, Ville Syrjälä wrote:
> > On Thu, Oct 21, 2021 at 07:56:24PM +0530, Ramalingam C wrote:
> > > From: Matt Roper
> > >
> > > DG2 unifies render compression and media compression into a single
> > > format for the
On 2021-10-12 16:58, Shankar, Uma wrote:
>
>
>> -Original Message-
>> From: Pekka Paalanen
>> Sent: Tuesday, October 12, 2021 4:01 PM
>> To: Shankar, Uma
>> Cc: intel-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org;
>> harry.wentl...@amd.com;
On 2021-10-14 15:44, Shankar, Uma wrote:
>
>
>> -Original Message-
>> From: Pekka Paalanen
>> Sent: Wednesday, October 13, 2021 2:01 PM
>> To: Shankar, Uma
>> Cc: harry.wentl...@amd.com; ville.syrj...@linux.intel.com; intel-
>> g...@lists.freedesktop.org;
Il 23/10/21 13:14, Flora Fu ha scritto:
Add driver for control APU tinysys
APU integrated subsystem having MD32RV33 (MD32) that runs tinysys
The tinsys is running on a micro processor in APU.
Its firmware is load and boot from Kernel side. Kernel and tinysys use
IPI to tx/rx messages.
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