On Sat, Apr 15, 2023 at 12:27:13AM +0100, Lorenzo Stoakes wrote:
> No invocation of get_user_pages() uses the vmas parameter, so remove
> it.
>
> The GUP API is confusing and caveated. Recent changes have done much to
> improve that, however there is more we can do. Exporting vmas is a prime
>
Commit 41d351f29528 ("drm/nouveau: stop using ttm_bo_wait")
converted from ttm_bo_wait_ctx() to dma_resv_wait_timeout().
However, dma_resv_wait_timeout() returns greater than zero on
success as opposed to ttm_bo_wait_ctx(). As a result, relocs
will fail and log errors even when it was a success.
Commit 41d351f29528 ("drm/nouveau: stop using ttm_bo_wait")
converted from ttm_bo_wait_ctx() to dma_resv_wait_timeout().
However, dma_resv_wait_timeout() returns greater than zero on
success as opposed to ttm_bo_wait_ctx(). As a result, relocs
will fail and log errors even when it was a success.
From: John Harrison
If the GuC load is taking an excessively long time, the wait loop
currently prints the GT frequency. Extend that to include the GuC
status as well so we can see if the GuC is actually making progress or
not.
Signed-off-by: John Harrison
---
From: John Harrison
It was noticed that duplicte entries in the firmware table could cause
an infinite loop in the firmware loading code if that entry failed to
load. Duplicate entries are a bug anyway and so should never happen.
Ensure they don't by tweaking the table validation code to reject
From: John Harrison
When reduced version firmware files were added (matching major
component being the only strict requirement), the minor version was
still tracked and a notification reported if it was older. However,
the patch version should really be tracked as well for the same
reasons. The
From: John Harrison
Explain another potential firmware failure mode and early exit the
long wait if hit.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h | 1 +
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 6 ++
2 files changed, 7 insertions(+)
diff
From: John Harrison
The validation of the firmware table was being done inside the code
for scanning the table for the next available firmware blob. Which is
unnecessary. Potentially, it should be a selftest. But either way, the
first step is pulling it out into a separate function that can be
From: John Harrison
Enhance the firmware table verification code to catch more potential
errors and to generally improve the code itself.
Track patch level version even on reduced version files to allow user
notification of missing bug fixes.
Detect another immediate failure case when loading
From: John Harrison
GuC based register dumps in error capture logs were basically broken
for virtual engines. This can be seen in igt@gem_exec_balancer@hang:
[IGT] gem_exec_balancer: starting subtest hang
[drm] GPU HANG: ecode 12:4:e1524110, in gem_exec_balanc [6388]
[drm] GT0: GUC: No
On Fri, 14 Apr 2023 15:34:15 -0700, Vinay Belgaumkar wrote:
>
> @@ -457,6 +458,34 @@ int intel_guc_slpc_get_max_freq(struct intel_guc_slpc
> *slpc, u32 *val)
> return ret;
> }
>
> +int intel_guc_slpc_set_ignore_eff_freq(struct intel_guc_slpc *slpc, bool val)
> +{
> + struct
On 4/14/2023 3:52 PM, Marijn Suijten wrote:
On 2023-04-14 14:03:23, Abhinav Kumar wrote:
[..]
Yes, ofcourse git send-email was used to send the patch, not any other
mail client.
Yes i am also aware that send-email converts rb to CC.
But if you keep working on the local branch, then you
On 4/14/2023 3:53 PM, Dmitry Baryshkov wrote:
On Sat, 15 Apr 2023 at 00:03, Abhinav Kumar wrote:
On 4/14/2023 1:58 PM, Dmitry Baryshkov wrote:
On Fri, 14 Apr 2023 at 21:55, Abhinav Kumar wrote:
On 4/14/2023 10:28 AM, Marijn Suijten wrote:
On 2023-04-14 08:41:37, Abhinav Kumar
On 4/14/2023 4:11 PM, Marijn Suijten wrote:
On 2023-04-14 10:57:45, Abhinav Kumar wrote:
On 4/14/2023 10:34 AM, Marijn Suijten wrote:
On 2023-04-14 08:48:43, Abhinav Kumar wrote:
On 4/14/2023 12:35 AM, Marijn Suijten wrote:
On 2023-04-12 10:33:15, Abhinav Kumar wrote:
[..]
What happens
On 2023-04-14 10:57:45, Abhinav Kumar wrote:
> On 4/14/2023 10:34 AM, Marijn Suijten wrote:
> > On 2023-04-14 08:48:43, Abhinav Kumar wrote:
> >> On 4/14/2023 12:35 AM, Marijn Suijten wrote:
> >>> On 2023-04-12 10:33:15, Abhinav Kumar wrote:
> >>> [..]
> > What happens if a device boots
On 2023-04-14 09:46:17, Kuogee Hsieh wrote:
> In current code, the dsc active bits are set only if the cfg->dsc is set.
This is the old sentence from v1 again, did you accidentally send the
wrong patch as the improvements from v2 are missing?
> However, for displays which are hot-pluggable,
On Sat, 15 Apr 2023 at 00:03, Abhinav Kumar wrote:
>
>
>
> On 4/14/2023 1:58 PM, Dmitry Baryshkov wrote:
> > On Fri, 14 Apr 2023 at 21:55, Abhinav Kumar
> > wrote:
> >>
> >>
> >>
> >> On 4/14/2023 10:28 AM, Marijn Suijten wrote:
> >>> On 2023-04-14 08:41:37, Abhinav Kumar wrote:
>
>
On 2023-04-14 14:03:23, Abhinav Kumar wrote:
[..]
> >> Yes, ofcourse git send-email was used to send the patch, not any other
> >> mail client.
> >>
> >> Yes i am also aware that send-email converts rb to CC.
> >>
> >> But if you keep working on the local branch, then you would have to
> >>
On Fri, 2023-04-14 at 13:35 +0300, Jani Nikula wrote:
> On Fri, 14 Apr 2023, Jeff Layton wrote:
> > On Fri, 2023-04-14 at 04:40 +, Lin, Wayne wrote:
> > > [Public]
> > >
> > > Hi Jeff,
> > >
> > > Thanks. I might need more information to understand why we can't retrieve
> > > the drm atomic
From: Cong Liu
This patch fixes memory leaks on error escapes in function fake_get_pages
Fixes: c3bfba9a2225 ("drm/i915: Check for integer truncation on scatterlist
creation")
Signed-off-by: Cong Liu
Reviewed-by: Andrzej Hajda
Reviewed-by: Andi Shyti
Signed-off-by: Andi Shyti
---
Hi,
just
SLPC enables use of efficient freq at init by default. It is
possible for GuC to request frequencies that are higher than
the 'software' max if user has set it lower than the efficient
level.
Scenarios/tests that require strict fixing of freq below the efficient
level will need to disable it
SLPC enables use of efficient freq at init by default. It is
possible for GuC to request frequencies that are higher than
the 'software' max if user has set it lower than the efficient
level.
Scenarios/tests that require strict fixing of freq below the efficient
level will need to disable it
Applied. Thanks!
Alex
On Fri, Apr 14, 2023 at 8:04 AM Tom Rix wrote:
>
> gcc with W=1 reports
> In file included from
> drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0.c:36:
> ./drivers/gpu/drm/amd/amdgpu/../pm/swsmu/inc/smu_v13_0.h:66:18: error:
> ‘pmfw_decoded_link_width’ defined
On 4/14/2023 1:58 PM, Dmitry Baryshkov wrote:
On Fri, 14 Apr 2023 at 21:55, Abhinav Kumar wrote:
On 4/14/2023 10:28 AM, Marijn Suijten wrote:
On 2023-04-14 08:41:37, Abhinav Kumar wrote:
On 4/14/2023 12:48 AM, Marijn Suijten wrote:
Capitalize DSC in the title, as discussed in v1.
On
On Fri, 14 Apr 2023 at 19:46, Kuogee Hsieh wrote:
>
> In current code, the dsc active bits are set only if the cfg->dsc is set.
> However, for displays which are hot-pluggable, there can be a use-case
> of disconnecting a DSC supported sink and connecting a non-DSC sink.
>
> For those cases we
On Fri, 14 Apr 2023 at 21:55, Abhinav Kumar wrote:
>
>
>
> On 4/14/2023 10:28 AM, Marijn Suijten wrote:
> > On 2023-04-14 08:41:37, Abhinav Kumar wrote:
> >>
> >> On 4/14/2023 12:48 AM, Marijn Suijten wrote:
> >>> Capitalize DSC in the title, as discussed in v1.
> >>>
> >>> On 2023-04-13
Hi Dave, Daniel,
Last few changes for 6.4.
The following changes since commit 55bf14961db9da61220e6f04bc9919c94b1a6585:
Merge tag 'mediatek-drm-next-6.4' of
https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into
drm-next (2023-04-11 12:28:10 +0200)
are available in the Git
Hi Francesco,
On 14-Apr-23 14:00, Francesco Dolcini wrote:
> Hello Aradhya,
>
> On Fri, Apr 14, 2023 at 01:19:38PM +0530, Aradhya Bhatia wrote:
>> On 30-Mar-23 22:47, Francesco Dolcini wrote:
>>> Hello,
>>> chiming in in this *old* email thread.
>>>
>>> Adding in copy a few more *@ti.com people
AIC100 does not initialize the SOC_HW_VERSION MHI register as expected.
Some instances of AIC100 are observed to have 0x in this register
which makes the controller think that the link is down and return an error
up to MHI. This results in a failed initialization.
Allow these cards to
Some devices might require special handling due to flawed implementations
or other reasons. Implement a quirk framework to handle these situations.
Implement the first quirk in this framework -
MHI_QUIRK_SOC_HW_VERSION_UNRELIABLE
The MHI spec indicates that the MHI device must initialize the
With the QAIC driver in -next, I'd like to suggest some MHI changes that
specific to AIC100 devices, but perhaps provide a framework for other
device oddities.
AIC100 devices technically violate the MHI spec in two ways. Sadly, these
issues comes from the device hardware, so host SW needs to work
Currently, we allow the framebuffer for a given plane to move between
memory domains, however when that happens it causes the screen to
flicker, it is even possible for the framebuffer to change memory
domains on every plane update (causing a continuous flicker effect). So,
to fix this, don't
Before commit bc0d7fdefec6 ("drm: vkms: Supports to the case where
primary plane doesn't match the CRTC"), the composition was executed on
top of the primary plane. Therefore, the primary plane was not able to
support the alpha channel. After commit bc0d7fdefec6, this is possible,
as the
Now that VKMS supports full alpha blending on all planes, drop the
"ARGB format on primary plane" and "Full alpha blending on all planes"
tasks from the TODO list.
Signed-off-by: Maíra Canal
---
Documentation/gpu/vkms.rst | 5 -
1 file changed, 5 deletions(-)
diff --git
On 4/14/2023 11:55 AM, Abhinav Kumar wrote:
On 4/14/2023 10:28 AM, Marijn Suijten wrote:
On 2023-04-14 08:41:37, Abhinav Kumar wrote:
On 4/14/2023 12:48 AM, Marijn Suijten wrote:
Capitalize DSC in the title, as discussed in v1.
On 2023-04-13 08:56:41, Kuogee Hsieh wrote:
In current
On 14/04/23 10:51, Maíra Canal wrote:
> Currently, the pixel conversion functions repeat the same loop to
> iterate the rows. Instead of repeating the same code for each pixel
> format, create a function to wrap the loop and isolate the pixel
> conversion functionality.
>
> Suggested-by:
On 4/14/2023 10:28 AM, Marijn Suijten wrote:
On 2023-04-14 08:41:37, Abhinav Kumar wrote:
On 4/14/2023 12:48 AM, Marijn Suijten wrote:
Capitalize DSC in the title, as discussed in v1.
On 2023-04-13 08:56:41, Kuogee Hsieh wrote:
In current code, the DSC active bits are written only if
On 4/14/2023 10:34 AM, Marijn Suijten wrote:
On 2023-04-14 08:48:43, Abhinav Kumar wrote:
On 4/14/2023 12:35 AM, Marijn Suijten wrote:
On 2023-04-12 10:33:15, Abhinav Kumar wrote:
[..]
What happens if a device boots without DSC panel connected? Will
CTL_DSC_FLUSH be zero and not
Hi Daniele,
> > MTL features a dedicated media engine that operates on its
> > independent GT, requiring activation of its specific interrupt
> > set.
> >
> > Enable the necessary interrupts in a single action when the media
> > engine is present, bypassing the need to iterate through all the
>
On 4/14/23 11:46, Ville Syrjälä wrote:
On Fri, Apr 14, 2023 at 11:37:17AM -0300, Maíra Canal wrote:
On 4/14/23 11:24, Ville Syrjälä wrote:
On Fri, Apr 14, 2023 at 10:51:50AM -0300, Maíra Canal wrote:
Currently, vkms only support the reflect-x property. Therefore, add the
reflect-y property to
On 2023-04-14 08:48:43, Abhinav Kumar wrote:
>
> On 4/14/2023 12:35 AM, Marijn Suijten wrote:
> > On 2023-04-12 10:33:15, Abhinav Kumar wrote:
> > [..]
> >>> What happens if a device boots without DSC panel connected? Will
> >>> CTL_DSC_FLUSH be zero and not (unnecessarily, I assume) flush any
On 2023-04-14 08:41:37, Abhinav Kumar wrote:
>
> On 4/14/2023 12:48 AM, Marijn Suijten wrote:
> > Capitalize DSC in the title, as discussed in v1.
> >
> > On 2023-04-13 08:56:41, Kuogee Hsieh wrote:
> >> In current code, the DSC active bits are written only if cfg->dsc is set.
> >> However, for
On 4/14/2023 9:25 AM, Andi Shyti wrote:
MTL features a dedicated media engine that operates on its
independent GT, requiring activation of its specific interrupt
set.
Enable the necessary interrupts in a single action when the media
engine is present, bypassing the need to iterate through
Replace the use of ttm_execbuf_util helpers with the new drm_exec
helpers. They are only used when locking multiple objects.
Signed-off-by: Francois Dugast
---
drivers/gpu/drm/xe/xe_bo.c | 22 ++-
drivers/gpu/drm/xe/xe_bo_types.h | 1 -
drivers/gpu/drm/xe/xe_exec.c |
This commit only here for others to test and for CI to build. It
is a squash of work by Christian König and Danilo Krummrich:
https://patchwork.freedesktop.org/series/114464/
https://patchwork.freedesktop.org/patch/530670/?series=112994=4
---
Documentation/gpu/drm-mm.rst | 12 +
This makes Xe use the new drm_exec helpers provided
by this series, which is not merged yet:
https://patchwork.freedesktop.org/series/114464/
v2: add a first patch with squashed dependencies
Francois Dugast (2):
drm/xe: dependencies for next commit
drm/xe: switch to using drm_exec
On Thu, Apr 13, 2023 at 11:47:25AM -0700, Nathan Chancellor wrote:
> On Wed, Apr 12, 2023 at 11:22:13AM +1000, Stephen Rothwell wrote:
> select SND_HDA_COMPONENT if SND_HDA_CORE
> # !CC_IS_CLANG: https://github.com/ClangBuiltLinux/linux/issues/1752
> - select DRM_AMD_DC_DCN if
On 14/04/2023 10:33, Krzysztof Kozlowski wrote:
Lists (items) with one item should be just enum because it is shorter,
simpler and does not confuse, if one wants to add new entry with a
fallback. Convert all of them to enums. OTOH, leave unused "oneOf"
entries in anticipation of further
In current code, the dsc active bits are set only if the cfg->dsc is set.
However, for displays which are hot-pluggable, there can be a use-case
of disconnecting a DSC supported sink and connecting a non-DSC sink.
For those cases we need to clear DSC active bits during teardown.
As discuss at
On 14/04/2023 18:07, Guillaume Ranquet wrote:
The ret variable in mtk_hdmi_pll_calc() was used unitialized as reported
by the kernel test robot.
Fix the issue by removing the variable altogether and testing out the
return value of mtk_hdmi_pll_set_hw()
Fixes: 45810d486bb44 ("phy: mediatek:
There's Intel Arc now which is what most folks will be looking for.
Signed-off-by: Adam Borowski
Acked-by: Alexey Brodkin
---
drivers/gpu/drm/tiny/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
v2: added Alexey's ACK.
diff --git a/drivers/gpu/drm/tiny/Kconfig
MTL features a dedicated media engine that operates on its
independent GT, requiring activation of its specific interrupt
set.
Enable the necessary interrupts in a single action when the media
engine is present, bypassing the need to iterate through all the
GTs.
Signed-off-by: Andi Shyti
---
The clock rate calculus in mtk_hdmi_pll_calc() was wrong when it has
been replaced by 'div_u64'.
Fix the issue by multiplying the values in the denominator instead of
dividing them.
Fixes: 45810d486bb44 ("phy: mediatek: add support for phy-mtk-hdmi-mt8195")
Reviewed-by: AngeloGioacchino Del
The ret variable in mtk_hdmi_pll_calc() was used unitialized as reported
by the kernel test robot.
Fix the issue by removing the variable altogether and testing out the
return value of mtk_hdmi_pll_set_hw()
Fixes: 45810d486bb44 ("phy: mediatek: add support for phy-mtk-hdmi-mt8195")
Reported-by:
I've received a report from kernel test report [1] that a variable was used
unitialized in the mtk8195 hdmi phy code.
I've upon fixing that issue found out that the clock rate calculation
was erroneous since the calculus was moved to div_u64.
I'm providing those two fixes on top of 45810d486bb44
Hi Luca,
I just encountered an error in this patch, so I have rejected the PR I made.
See below for the details:
On 07/04/2023 15:38, Luca Ceresoli wrote:
> The CSI module does not handle all the MIPI lane calibration procedure,
> leaving a small part of it to the VI module. In doing this,
>
On Fri, Apr 14, 2023 at 08:22:53AM -0400, Tom Rix wrote:
> clang reports
> drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:298:6: error: variable
> 'ret' is uninitialized when used here [-Werror,-Wuninitialized]
> if (ret)
> ^~~
> ret should have been set by the preceding call to
On 4/14/2023 12:35 AM, Marijn Suijten wrote:
On 2023-04-12 10:33:15, Abhinav Kumar wrote:
[..]
What happens if a device boots without DSC panel connected? Will
CTL_DSC_FLUSH be zero and not (unnecessarily, I assume) flush any of the
DSC blocks? Or could this flush uninitialized state to
On 14/04/2023 17:43, Matthias Brugger wrote:
On 14/04/2023 14:22, Tom Rix wrote:
clang reports
drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:298:6: error: variable
'ret' is uninitialized when used here [-Werror,-Wuninitialized]
if (ret)
^~~
ret should have been set by
On 14/04/2023 14:22, Tom Rix wrote:
clang reports
drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:298:6: error: variable
'ret' is uninitialized when used here [-Werror,-Wuninitialized]
if (ret)
^~~
ret should have been set by the preceding call to mtk_hdmi_pll_set_hw.
On 4/14/2023 12:48 AM, Marijn Suijten wrote:
Capitalize DSC in the title, as discussed in v1.
On 2023-04-13 08:56:41, Kuogee Hsieh wrote:
In current code, the DSC active bits are written only if cfg->dsc is set.
However, for displays which are hot-pluggable, there can be a use-case
of
Hi Lionel, does this patch work for you?
On Mon, 2023-04-10 at 10:22 -0700, Ceraolo Spurio, Daniele wrote:
> On 4/6/2023 10:44 AM, Alan Previn wrote:
alan:snip
> > +/*
> > + * Query the status of PXP support in i915.
> > + *
> > + * The query can fail in the following scenarios with the listed
On 11/04/23 11:36, Krzysztof Kozlowski wrote:
On 05/04/2023 16:24, Jayesh Choudhary wrote:
From: Rahul T R
The mhdp bridge can work without its HPD pin hooked up to the connector,
but the current bridge driver throws an error when hpd line is not
connected to the connector. For such cases,
On 06/04/23 07:22, Laurent Pinchart wrote:
Hi Jayesh,
Thank you for the patch.
On Wed, Apr 05, 2023 at 07:54:40PM +0530, Jayesh Choudhary wrote:
From: Rahul T R
In J721S2 EVMs DP0 hpd is not connected to correct
hpd pin on SOC, to handle such cases, Add support for
"no-hpd" property in
cpp_check reports
drivers/gpu/drm/amd/display/modules/freesync/freesync.c:1143:17: style: Variable
'oldest_index' is assigned a value that is never used. [unreadVariable]
oldest_index = 0;
^
This variable is not used so remove.
Signed-off-by: Tom Rix
---
On Tue, Apr 11, 2023 at 10:40 PM Mikhail Gavrilov
wrote:
>
> Hi,
> KASAN continues to find problems in the drm_sched_job_cleanup code at 6.3rc6.
> I not got any feedback in the thread
> https://lore.kernel.org/lkml/cabxgcsmvub2ra4d+k5cna0_2521tox++d4nmoukki4x2-q_...@mail.gmail.com/
> Therefore, I
On Fri, Apr 14, 2023 at 11:37:17AM -0300, Maíra Canal wrote:
> On 4/14/23 11:24, Ville Syrjälä wrote:
> > On Fri, Apr 14, 2023 at 10:51:50AM -0300, Maíra Canal wrote:
> >> Currently, vkms only support the reflect-x property. Therefore, add the
> >> reflect-y property to vkms through a software
On 06/04/23 07:10, Laurent Pinchart wrote:
Hi Jayesh,
Thank you for the patch.
On Wed, Apr 05, 2023 at 07:54:39PM +0530, Jayesh Choudhary wrote:
From: Rahul T R
The mhdp bridge can work without its HPD pin hooked up to the connector,
but the current bridge driver throws an error when hpd
gpu->mmu_context is the MMU context of the last job in the HW queue, which
isn't necessarily the same as the context from the bad job. Dump the MMU
context from the scheduler determined bad submit to make it work as intended.
Fixes: 17e4660ae3d7 ("drm/etnaviv: implement per-process address spaces
On 4/14/23 11:24, Ville Syrjälä wrote:
On Fri, Apr 14, 2023 at 10:51:50AM -0300, Maíra Canal wrote:
Currently, vkms only support the reflect-x property. Therefore, add the
reflect-y property to vkms through a software implementation of the
operation. This is possible by reverse reading the y
Hi,
On Thu 13 Apr 23, 10:27, Chris Morgan wrote:
> On Thu, Apr 13, 2023 at 04:43:47PM +0200, Sascha Hauer wrote:
> > During a suspend/resume cycle the VO power domain will be disabled and
> > the VOP2 registers will reset to their default values. After that the
> > cached register values will be
Hi Christian, hi Thomas,
On Fri, Mar 10, 2023 at 11:42:56AM +0100, Thomas Hellström (Intel) wrote:
> Nice. This seems to have all we need for now for Xe as well, although not
> for i915 ATM.
A series to use drm_exec in Xe has been sent for review:
https://patchwork.freedesktop.org/series/116477/
On Fri, Apr 14, 2023 at 10:51:50AM -0300, Maíra Canal wrote:
> Currently, vkms only support the reflect-x property. Therefore, add the
> reflect-y property to vkms through a software implementation of the
> operation. This is possible by reverse reading the y axis during the
> blending.
>
> Now,
On 4/14/23 12:44 AM, Christian Gmeiner wrote:
Hi Andrew
Am Di., 4. Apr. 2023 um 17:02 Uhr schrieb Christian Gmeiner
:
Hi Andrew
Okay, will split for v2.
Was there a follow-up v2 of this patchset? AFAICT this series did not
make it into the mainline kernel.
Do you have any plans to
Now that VKMS supports all values of rotation and reflection, drop the
"Rotation" task from the TODO list.
Signed-off-by: Maíra Canal
---
Documentation/gpu/vkms.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/gpu/vkms.rst b/Documentation/gpu/vkms.rst
index
Currently, vkms only support the reflect-x property. Therefore, add the
reflect-y property to vkms through a software implementation of the
operation. This is possible by reverse reading the y axis during the
blending.
Now, vkms support all possible rotation values.
Tested with
Currently, vkms doesn't support any reflection property. Therefore, add
the reflect-x property to vkms through a software implementation of the
operation. This is possible by reverse reading the x axis during the
blending.
Tested with igt@kms_rotation_crc@primary-reflect-x and
Currently, vkms only supports the rotate-90 and rotate-180 properties.
Therefore, improve the vkms IGT test coverage by adding the rotate-270
property to vkms. The rotation was implement by software: rotate the way
the blending occurs by making the source x axis be the destination y axis
and the
Currently, vkms only supports the rotate-180 property. Therefore,
improve the vkms IGT test coverage by adding the rotate-90 property to
vkms. The rotation was implement by software: rotate the way the
blending occurs by making the source x axis be the destination y axis and
the source y axis be
Currently, vkms doesn't support any rotation property. Therefore,
improve the vkms IGT test coverage by adding the rotate-0 and rotate-180
properties to vkms. The rotation was implemented by software: invert the
way the blending occurs by reverse reading the x and y axis.
Tested with
This patchset implements all possible rotation value in vkms. All operations
were implemented by software by changing the way the pixels are read. The way
the blending is performed can be depicted as:
- rotate-0:
(x) >
--
(y) ||
|
Currently, the pixel conversion functions repeat the same loop to
iterate the rows. Instead of repeating the same code for each pixel
format, create a function to wrap the loop and isolate the pixel
conversion functionality.
Suggested-by: Arthur Grillo
Signed-off-by: Maíra Canal
---
On Fri, Apr 14, 2023 at 1:57 AM Tvrtko Ursulin
wrote:
>
>
> On 13/04/2023 21:05, Daniel Vetter wrote:
> > On Thu, Apr 13, 2023 at 05:40:21PM +0100, Tvrtko Ursulin wrote:
> >>
> >> On 13/04/2023 14:27, Daniel Vetter wrote:
> >>> On Thu, Apr 13, 2023 at 01:58:34PM +0100, Tvrtko Ursulin wrote:
>
Hi all,
Today's linux-next merge of the drm-misc tree got a conflict in:
drivers/gpu/drm/ttm/ttm_pool.c
between commit:
23baf831a32c0 ("mm, treewide: redefine MAX_ORDER sanely")
from the mm-stable tree and commit:
56e51681246e5 ("drm/ttm: revert "Reduce the number of used allocation
On Fri, 14 Apr 2023 12:31, AngeloGioacchino Del Regno
wrote:
>Il 13/04/23 14:46, Guillaume Ranquet ha scritto:
>> The ret variable in mtk_hdmi_pll_calc() was used unitialized as reported
>> by the kernel test robot.
>>
>> Fix the issue by removing the variable altogether and testing out the
>>
clang reports
drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:298:6: error: variable
'ret' is uninitialized when used here [-Werror,-Wuninitialized]
if (ret)
^~~
ret should have been set by the preceding call to mtk_hdmi_pll_set_hw.
Fixes: 45810d486bb4 ("phy: mediatek: add
gcc with W=1 reports
In file included from
drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0.c:36:
./drivers/gpu/drm/amd/amdgpu/../pm/swsmu/inc/smu_v13_0.h:66:18: error:
‘pmfw_decoded_link_width’ defined but not used
[-Werror=unused-const-variable=]
66 | static const int
Hi,
On 2023/4/14 15:56, Daniel Vetter wrote:
On Fri, 14 Apr 2023 at 09:34, Thomas Zimmermann wrote:
Hi
Am 14.04.23 um 07:36 schrieb Daniel Vetter:
On Fri, 14 Apr 2023 at 06:24, Sui Jingfeng <15330273...@189.cn> wrote:
Hi,
On 2023/4/14 04:01, Daniel Vetter wrote:
On Thu, Apr 13, 2023 at
Hi,
On 2023/4/14 03:16, Thomas Zimmermann wrote:
Hi,
thanks for the patch. This is effectively a revert of commit
8fbc9af55de0 ("drm/fbdev-generic: Set screen size to size of GEM
buffer"). Please add a Fixes tag.
Am 13.04.23 um 20:06 schrieb Sui Jingfeng:
From: Sui Jingfeng
The crazy
On 2023/04/14 19:13, Jani Nikula wrote:
> On Fri, 14 Apr 2023, Tetsuo Handa wrote:
>> On 2023/03/15 19:47, Luca Coelho wrote:
>>> On Tue, 2023-03-14 at 20:21 +0900, Tetsuo Handa wrote:
Like commit c4f135d643823a86 ("workqueue: Wrap flush_workqueue() using a
macro") says,
Lists (items) with one item should be just const or enum because it is
shorter and simpler.
Signed-off-by: Krzysztof Kozlowski
---
Rebased on next-20230406. I hope it applies cleanly...
---
.../display/bridge/analogix,anx7625.yaml | 3 +--
.../display/panel/sharp,lq101r1sx01.yaml |
Hi Tvrtko,
On Wed, Apr 12, 2023 at 04:45:13PM +0100, Tvrtko Ursulin wrote:
[snip]
> >
> > [snip]
> > > However I am unsure if disabling pagefaulting is needed or not. Thomas,
> > > Matt, being the last to touch this area, perhaps you could have a look?
> > > Because I notice we have a fallback
On Fri, 14 Apr 2023, Jeff Layton wrote:
> On Fri, 2023-04-14 at 04:40 +, Lin, Wayne wrote:
>> [Public]
>>
>> Hi Jeff,
>>
>> Thanks. I might need more information to understand why we can't retrieve
>> the drm atomic state. Also , "Failed to create MST payload for port"
>> indicates
>>
Il 13/04/23 14:46, Guillaume Ranquet ha scritto:
The clock rate calculus in mtk_hdmi_pll_calc() was wrong when it has
been replaced by 'div_u64'.
Fix the issue by multiplying the values in the denominator instead of
dividing them.
Fixes: 45810d486bb44 ("phy: mediatek: add support for
Il 13/04/23 14:46, Guillaume Ranquet ha scritto:
The ret variable in mtk_hdmi_pll_calc() was used unitialized as reported
by the kernel test robot.
Fix the issue by removing the variable altogether and testing out the
return value of mtk_hdmi_pll_set_hw()
Fixes: 45810d486bb44 ("phy: mediatek:
On 12/04/2023 13:27, AngeloGioacchino Del Regno wrote:
> Add a compatible string for MediaTek Helio X10 MT6795's display PWM
> block: this is the same as MT8173.
>
> Signed-off-by: AngeloGioacchino Del Regno
>
Acked-by: Krzysztof Kozlowski
Best regards,
Krzysztof
On 14/04/2023 12:25, AngeloGioacchino Del Regno wrote:
> Il 14/04/23 10:34, Krzysztof Kozlowski ha scritto:
>> On 14/04/2023 10:30, Uwe Kleine-König wrote:
>>> On Fri, Apr 14, 2023 at 10:21:05AM +0200, Krzysztof Kozlowski wrote:
On 12/04/2023 13:27, AngeloGioacchino Del Regno wrote:
> Add
Il 14/04/23 10:46, Krzysztof Kozlowski ha scritto:
On 12/04/2023 13:27, AngeloGioacchino Del Regno wrote:
I have added more than 800 lines to this devicetree: adding myself to
the copyright header.
Signed-off-by: AngeloGioacchino Del Regno
---
arch/arm64/boot/dts/mediatek/mt6795.dtsi | 3
Il 14/04/23 10:34, Krzysztof Kozlowski ha scritto:
On 14/04/2023 10:30, Uwe Kleine-König wrote:
On Fri, Apr 14, 2023 at 10:21:05AM +0200, Krzysztof Kozlowski wrote:
On 12/04/2023 13:27, AngeloGioacchino Del Regno wrote:
Add a compatible string for MediaTek Helio X10 MT6795's display PWM
On Fri, 2023-04-14 at 04:40 +, Lin, Wayne wrote:
> [Public]
>
> Hi Jeff,
>
> Thanks. I might need more information to understand why we can't retrieve
> the drm atomic state. Also , "Failed to create MST payload for port" indicates
> error while configuring DPCD payload ID table. Could you
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