Add MTL's function for ARB session creation using PXP firmware
version 4.3 ABI structure format.
While relooking at the ARB session creation flow in intel_pxp_start,
let's address missing UAPI documentation. Without actually changing
backward compatible behavior, update i915's drm-uapi comments
Add GSC engine based method for sending PXP firmware packets
to the GSC firmware for MTL (and future) products.
Use the newly added helpers to populate the GSC-CS memory
header and send the message packet to the FW by dispatching
the GSC_HECI_CMD_PKT instruction on the GSC engine.
We use
Add helper functions into a new file for heci-packet-submission.
The helpers will handle generating the MTL GSC-CS Memory-Header
and submission of the Heci-Cmd-Packet instructions to the engine.
NOTE1: These common functions for heci-packet-submission will be used
by different i915 callers:
On legacy platforms, KCR HW enabling is done at the time the mei
component interface is bound. It's also disabled during unbind.
However, for MTL onwards, we don't depend on a tee component
to start sending GSC-CS firmware messages.
Thus, immediately enable (or disable) KCR HW on PXP's init,
fini
For MTL, the PXP back-end transport uses the GSC engine to submit
HECI packets through the HW to the GSC firmware for PXP arb
session management. This submission uses a non-priveleged
batch buffer, a buffer for the command packet and of course
a context targeting the GSC-CS.
Thus for MTL, we need
Because of the additional firmware, component-driver and
initialization depedencies required on MTL platform before a
PXP context can be created, UMD calling for PXP creation as a
way to get-caps can take a long time. An actual real world
customer stack has seen this happen in the 4-to-8 second
Enable PXP with MTL-GSC-CS: add the has_pxp into device info
and increase the debugfs teardown timeouts to align with
new GSC-CS + firmware specs.
Now that we have 3 places that are selecting pxp timeouts
based on tee vs gsccs back-end, let's add a helper.
Signed-off-by: Alan Previn
Add MTL hw-plumbing enabling for KCR operation under PXP
which includes:
1. Updating 'pick-gt' to get the media tile for
KCR interrupt handling
2. Adding MTL's KCR registers for PXP operation
(init, status-checking, etc.).
While doing #2, lets create a separate registers header file for
This series enables PXP on MTL. On ADL/TGL platforms, we rely on
the mei driver via the i915-mei PXP component interface to establish
a connection to the security firmware via the HECI device interface.
That interface is used to create and teardown the PXP ARB session.
PXP ARB session is created
Hi Kuogee,
kernel test robot noticed the following build warnings:
[auto build test WARNING on drm-misc/drm-misc-next]
[also build test WARNING on drm/drm-next drm-exynos/exynos-drm-next
drm-intel/for-linux-next drm-intel/for-linux-next-fixes drm-tip/drm-tip
linus/master v6.3-rc7 next-20230420
On Thu, 2023-04-20 at 23:07 +0300, Dmitry Baryshkov wrote:
> On Thu, 20 Apr 2023 at 23:01, Janne Grunau wrote:
> >
> > On 2023-03-28 10:31:29 +0800, Zongmin Zhou wrote:
> > > When drivers call drm_kms_helper_poll_disable from
> > > their device suspend implementation without enabled output
> > >
The pull request you sent on Fri, 21 Apr 2023 11:27:42 +1000:
> git://anongit.freedesktop.org/drm/drm tags/drm-fixes-2023-04-21
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/2af3e53a4dc08657f1b46f97f04ff4a0ab3cad8d
Thank you!
--
Deet-doot-dot, I am a bot.
fix Smatch static checker warning
- uninitialized symbol comp_pdev in mtk_ddp_comp_init.
Fixes: 0d9eee9118b7 ("drm/mediatek: Add drm ovl_adaptor sub driver for MT8195")
Signed-off-by: Nancy.Lin
---
v2: add Fixes tag
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 5 -
1 file changed, 4
Hi Linus,
Back from my trip physically, my jet lag is still strong however so
mentally I'm probably a few more days away!
This is the regular and hopefully last round of fixes for 6.3. Pretty
small, a few amdgpu, one i915, one nouveau, one rockchip and one gpu
scheduler fix.
Dave.
On Thu, Apr 20, 2023 at 6:11 AM Tvrtko Ursulin
wrote:
>
>
> On 19/04/2023 15:38, Rob Clark wrote:
> > On Wed, Apr 19, 2023 at 7:06 AM Tvrtko Ursulin
> > wrote:
> >>
> >>
> >> On 18/04/2023 17:08, Rob Clark wrote:
> >>> On Tue, Apr 18, 2023 at 7:58 AM Tvrtko Ursulin
> >>> wrote:
> On
On Thu, Apr 20, 2023 at 6:14 AM Tvrtko Ursulin
wrote:
>
>
> On 19/04/2023 15:32, Rob Clark wrote:
> > On Wed, Apr 19, 2023 at 6:16 AM Tvrtko Ursulin
> > wrote:
> >>
> >>
> >> On 18/04/2023 18:18, Rob Clark wrote:
> >>> On Mon, Apr 17, 2023 at 8:56 AM Tvrtko Ursulin
> >>> wrote:
>
>
From: John Harrison
If the DEBUG_GEM config option is set then escalate the 'unexpected
firmware version' message from a notice to an error. This will ensure
that the CI system treats such occurences as a failure and logs a bug
about it (or fails the pre-merge testing).
Signed-off-by: John
From: John Harrison
The validation of the firmware table was being done inside the code
for scanning the table for the next available firmware blob. Which is
unnecessary. So pull it out into a separate function that is only
called once per blob type at init time.
Also, drop the CONFIG_SELFTEST
From: John Harrison
Enhance the firmware table verification code to catch more potential
errors and to generally improve the code itself.
Track patch level version even on reduced version files to allow user
notification of missing bug fixes.
Detect another immediate failure case when loading
From: John Harrison
Explain another potential firmware failure mode and early exit the
long wait if hit.
Signed-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h | 1 +
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 6 ++
2
From: John Harrison
When reduced version firmware files were added (matching major
component being the only strict requirement), the minor version was
still tracked and a notification reported if it was older. However,
the patch version should really be tracked as well for the same
reasons. The
From: John Harrison
If the GuC load is taking an excessively long time, the wait loop
currently prints the GT frequency. Extend that to include the GuC
status as well so we can see if the GuC is actually making progress or
not.
Signed-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
From: John Harrison
It was noticed that duplicate entries in the firmware table could cause
an infinite loop in the firmware loading code if that entry failed to
load. Duplicate entries are a bug anyway and so should never happen.
Ensure they don't by tweaking the table validation code to reject
On 4/20/2023 5:12 PM, Dmitry Baryshkov wrote:
On 21/04/2023 02:25, Kuogee Hsieh wrote:
At current implementation, topology configuration is thrown away after
dpu_rm_reserve(). This patch save the topology so that it can be used
for DSC related calculation later.
Please take a look at
ARM architecture only has 'memory', so all devices are accessed by
MMIO if possible.
Signed-off-by: Jammy Huang
Reviewed-by: Thomas Zimmermann
---
v2 changes:
- Use MMIO after AST2500 which enable MMIO by default.
v3 changes:
- Correct comments
---
drivers/gpu/drm/ast/ast_main.c | 9
On 21/04/2023 02:25, Kuogee Hsieh wrote:
During DSC preparation, add run time calculation to figure out what
usage modes, split mode and merge mode, is going to be setup.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 56 -
1 file
I think we are also bottom-ing on the opens fo this patch too:
On Thu, 2023-04-20 at 13:21 -0700, Ceraolo Spurio, Daniele wrote:
> On 4/20/2023 11:49 AM, Teres Alexis, Alan Previn wrote:
> > On Wed, 2023-03-29 at 09:56 -0700, Ceraolo Spurio, Daniele wrote:
> > > The GSC notifies us of a proxy
On 21/04/2023 02:25, Kuogee Hsieh wrote:
At current implementation, topology configuration is thrown away after
dpu_rm_reserve(). This patch save the topology so that it can be used
for DSC related calculation later.
Please take a look at
On 21/04/2023 02:25, Kuogee Hsieh wrote:
From: Abhinav Kumar
Add DSC 1.2 hardware blocks to the catalog with necessary
sub-block and feature flag information.
Each display compression engine (DCE) contains dual hard
slice DSC encoders so both share same base address but with
its own different
i guess we are settled with this patch...
On Thu, 2023-04-20 at 15:04 -0700, Ceraolo Spurio, Daniele wrote:
> On 4/18/2023 11:57 PM, Teres Alexis, Alan Previn wrote:
> > On Wed, 2023-03-29 at 09:56 -0700, Ceraolo Spurio, Daniele wrote:
> > > From: Alexander Usyskin
> > >
> > > Add GSC proxy
On 21/04/2023 02:25, Kuogee Hsieh wrote:
Current DSC flush update is piggyback inside dpu_hw_ctl_intf_cfg_v1().
This patch separate DSC flush away from dpu_hw_ctl_intf_cfg_v1() by
adding dpu_hw_ctl_update_pending_flush_dsc_v1() to handle both per
DSC engine and DSC flush bits at same time to
On 21/04/2023 02:25, Kuogee Hsieh wrote:
Add support for DSC 1.2 by providing the necessary hooks to program
the DPU DSC 1.2 encoder.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/Makefile | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 38 ++-
On 4/20/2023 3:04 PM, Ceraolo Spurio, Daniele wrote:
On 4/18/2023 11:57 PM, Teres Alexis, Alan Previn wrote:
On Wed, 2023-03-29 at 09:56 -0700, Ceraolo Spurio, Daniele wrote:
From: Alexander Usyskin
Add GSC proxy driver. It to allows messaging between GSC component
on Intel on board
On 4/17/2023 10:56 AM, Teres Alexis, Alan Previn wrote:
On Mon, 2023-04-10 at 09:10 -0700, Ceraolo Spurio, Daniele wrote:
alan:snip
+int
+intel_gsc_uc_heci_cmd_submit_nonpriv(struct intel_gsc_uc *gsc,
+struct intel_context *ce,
+
Add support for DSC 1.2 by providing the necessary hooks to program
the DPU DSC 1.2 encoder.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/Makefile | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 38 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h | 17 +-
During DSC preparation, add run time calculation to figure out what
usage modes, split mode and merge mode, is going to be setup.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 56 -
1 file changed, 32 insertions(+), 24 deletions(-)
At current implementation, topology configuration is thrown away after
dpu_rm_reserve(). This patch save the topology so that it can be used
for DSC related calculation later.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 32 ++---
1 file
From: Abhinav Kumar
Add DSC 1.2 hardware blocks to the catalog with necessary
sub-block and feature flag information.
Each display compression engine (DCE) contains dual hard
slice DSC encoders so both share same base address but with
its own different sub block address.
Signed-off-by: Abhinav
Current DSC flush update is piggyback inside dpu_hw_ctl_intf_cfg_v1().
This patch separate DSC flush away from dpu_hw_ctl_intf_cfg_v1() by
adding dpu_hw_ctl_update_pending_flush_dsc_v1() to handle both per
DSC engine and DSC flush bits at same time to make it consistent with
the location of flush
This series adds the DPU side changes to support DSC 1.2 encoder. This
was validated with both DSI DSC 1.2 panel and DP DSC 1.2 monitor.
The DSI and DP parts will be pushed later on top of this change.
Abhinav Kumar (1):
drm/msm/dpu: add DSC 1.2 hw blocks for relevant chipsets
Kuogee Hsieh
Now that VKMS supports full alpha blending on all planes, drop the
"ARGB format on primary plane" and "Full alpha blending on all planes"
tasks from the TODO list.
Signed-off-by: Maíra Canal
Reviewed-by: Melissa Wen
---
v1 -> v2:
Before commit bc0d7fdefec6 ("drm: vkms: Supports to the case where
primary plane doesn't match the CRTC"), the composition was executed on
top of the primary plane. Therefore, the primary plane was not able to
support the alpha channel. After commit bc0d7fdefec6, this is possible,
as the
On 21.04.2023 00:50, Dmitry Baryshkov wrote:
> On 21/04/2023 01:31, Konrad Dybcio wrote:
>> Add support for MDSS on SM6375.
>>
>> Signed-off-by: Konrad Dybcio
>> ---
>> drivers/gpu/drm/msm/msm_mdss.c | 10 ++
>> 1 file changed, 10 insertions(+)
>>
>> diff --git
On 21/04/2023 02:05, Konrad Dybcio wrote:
On 21.04.2023 00:41, Dmitry Baryshkov wrote:
On 21/04/2023 01:31, Konrad Dybcio wrote:
Add SM6350 support to the DPU1 driver to enable display output.
Signed-off-by: Konrad Dybcio
Signed-off-by: Konrad Dybcio
---
[...]
+
+static const struct
On 21.04.2023 00:41, Dmitry Baryshkov wrote:
> On 21/04/2023 01:31, Konrad Dybcio wrote:
>> Add SM6350 support to the DPU1 driver to enable display output.
>>
>> Signed-off-by: Konrad Dybcio
>> Signed-off-by: Konrad Dybcio
>> ---
[...]
>> +
>> +static const struct dpu_sspp_cfg sm6350_sspp[]
On 21/04/2023 01:31, Konrad Dybcio wrote:
It got broken at some point, fix it up.
Signed-off-by: Konrad Dybcio
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
This should probably come before patches 11 and 12.
diff --git
On 21/04/2023 01:31, Konrad Dybcio wrote:
Add the SM6375 DPU compatible to clients compatible list, as it also
needs the workarounds.
Signed-off-by: Konrad Dybcio
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
1 file changed, 1 insertion(+)
Acked-by: Dmitry Baryshkov
--
With best
On 20/04/2023 22:56, Marijn Suijten wrote:
On 2023-04-20 22:51:22, Dmitry Baryshkov wrote:
On 20/04/2023 22:47, Abhinav Kumar wrote:
On 4/20/2023 11:01 AM, Dmitry Baryshkov wrote:
On 20/04/2023 04:36, Konrad Dybcio wrote:
On 20.04.2023 03:28, Abhinav Kumar wrote:
On 4/19/2023 6:26 PM,
On 21/04/2023 01:31, Konrad Dybcio wrote:
From: Konrad Dybcio
Add the SM6350 DPU compatible to clients compatible list, as it also
needs the workarounds.
Signed-off-by: Konrad Dybcio
Signed-off-by: Konrad Dybcio
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
1 file changed, 1
On 21/04/2023 01:31, Konrad Dybcio wrote:
Add support for MDSS on SM6375.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/msm_mdss.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index
On 21/04/2023 01:31, Konrad Dybcio wrote:
Add support for MDSS on SM6375.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/msm_mdss.c | 10 ++
1 file changed, 10 insertions(+)
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
On 21/04/2023 01:31, Konrad Dybcio wrote:
Add basic SM6375 support to the DPU1 driver to enable display output.
Signed-off-by: Konrad Dybcio
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 5 -
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 152 +
On 21/04/2023 01:31, Konrad Dybcio wrote:
Add support for MDSS on SM6350.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/msm_mdss.c | 9 +
1 file changed, 9 insertions(+)
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
On 21/04/2023 01:31, Konrad Dybcio wrote:
Add SM6350 support to the DPU1 driver to enable display output.
Signed-off-by: Konrad Dybcio
Signed-off-by: Konrad Dybcio
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 191 +
It got broken at some point, fix it up.
Signed-off-by: Konrad Dybcio
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index
Add SM6350 support to the DPU1 driver to enable display output.
Signed-off-by: Konrad Dybcio
Signed-off-by: Konrad Dybcio
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 191 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 +
From: Konrad Dybcio
Add the SM6350 DPU compatible to clients compatible list, as it also
needs the workarounds.
Signed-off-by: Konrad Dybcio
Signed-off-by: Konrad Dybcio
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
1 file changed, 1 insertion(+)
diff --git
Document the SM6375 MDSS.
Signed-off-by: Konrad Dybcio
---
.../bindings/display/msm/qcom,sm6375-mdss.yaml | 216 +
1 file changed, 216 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml
Document SM6375 DPU.
Signed-off-by: Konrad Dybcio
---
.../bindings/display/msm/qcom,sm6375-dpu.yaml | 106 +
1 file changed, 106 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6375-dpu.yaml
Add the SM6375 DPU compatible to clients compatible list, as it also
needs the workarounds.
Signed-off-by: Konrad Dybcio
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
Add basic SM6375 support to the DPU1 driver to enable display output.
Signed-off-by: Konrad Dybcio
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 5 -
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 152 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |
Document the SM6350 MDSS.
Signed-off-by: Konrad Dybcio
---
.../bindings/display/msm/qcom,sm6350-mdss.yaml | 214 +
1 file changed, 214 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml
Add support for MDSS on SM6375.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/msm_mdss.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index 4e3a5f0c303c..f2470ce699f7 100644
---
Add support for MDSS on SM6350.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/msm_mdss.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index e8c93731aaa1..4e3a5f0c303c 100644
---
Add the DSI host found on SM6350.
Acked-by: Rob Herring
Signed-off-by: Konrad Dybcio
---
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
Document the SM6350 DPU.
Signed-off-by: Konrad Dybcio
---
.../bindings/display/msm/qcom,sm6350-dpu.yaml | 94 ++
1 file changed, 94 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml
Add the DSI host found on SM6375.
Acked-by: Rob Herring
Signed-off-by: Konrad Dybcio
---
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
v1 -> v2:
- Rebase on the DPU catalog rework and INTF_TE
- Fix QSEED(3L/4) discrepancies
- Fixed DMA/cursor discrepancies for 6350
- No deduplication, that's gonna be handled in catalogrework 2:
"the return of the catalogrework"
- Split MDSS & DPU binding additions
- Drop "Allow variable
On 21/04/2023 00:51, Marijn Suijten wrote:
On 2023-04-20 04:03:31, Dmitry Baryshkov wrote:
[..]
-static void dpu_hw_setup_vsync_source(struct dpu_hw_mdp *mdp,
+static void dpu_hw_setup_vsync_source_v1(struct dpu_hw_mdp *mdp,
struct dpu_vsync_source_cfg *cfg)
In my opinion _v1
On 21/04/2023 01:01, Marijn Suijten wrote:
Whoops, looks like I wrongly lost all the cc's when importing b4-am's
mbx file which is just a patch with a few but not all email headers.
Cc'ing everyone on this occasion with my review.
On 2023-04-20 23:33:07, Marijn Suijten wrote:
On 2023-04-20
Stop mapping the regdma region. The driver does not support regdma.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 6 --
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 2 +-
2 files changed, 1 insertion(+), 7 deletions(-)
diff --git
The regdma is currently not used by the current driver. We have no way
to practically verify that the regdma is described correctly. Drop it
now.
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 1 -
.../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h| 2 -
On 21/04/2023 00:39, Marijn Suijten wrote:
On 2023-04-20 08:46:46, Abhinav Kumar wrote:
On 4/20/2023 7:33 AM, Dmitry Baryshkov wrote:
On 18/04/2023 02:14, Marijn Suijten wrote:
Some of these members were initialized while never read, while others
were not even assigned any value at all.
On 4/18/2023 11:57 PM, Teres Alexis, Alan Previn wrote:
On Wed, 2023-03-29 at 09:56 -0700, Ceraolo Spurio, Daniele wrote:
From: Alexander Usyskin
Add GSC proxy driver. It to allows messaging between GSC component
on Intel on board graphics card and CSE device.
alan:nit: isn't "Intel
On 4/21/23 04:10, Bjorn Helgaas wrote:
> [+cc Damien, linux-ide]
>
> On Thu, Apr 20, 2023 at 09:08:48AM +0200, Thomas Zimmermann wrote:
>> Am 19.04.23 um 20:37 schrieb Bjorn Helgaas:
>>> On Wed, Apr 19, 2023 at 09:00:15AM +0200, Thomas Zimmermann wrote:
Am 19.04.23 um 00:57 schrieb Patrick
Whoops, looks like I wrongly lost all the cc's when importing b4-am's
mbx file which is just a patch with a few but not all email headers.
Cc'ing everyone on this occasion with my review.
On 2023-04-20 23:33:07, Marijn Suijten wrote:
> On 2023-04-20 23:07:42, Dmitry Baryshkov wrote:
> > The
On 2023-04-20 04:11:29, Dmitry Baryshkov wrote:
> On 17/04/2023 23:21, Marijn Suijten wrote:
> > All SoCs since DPU 5.0.0 have the tear interrupt registers moved out of
> > the PINGPONG block and into the INTF block. Wire up these interrupts
> > and IRQ masks on all supported hardware.
> >
> >
On Thu, Apr 20, 2023 at 8:43 AM Lucas Stach wrote:
>
> Am Donnerstag, dem 20.04.2023 um 08:24 -0500 schrieb Adam Ford:
> > On Thu, Apr 20, 2023 at 8:06 AM Lucas Stach wrote:
> > >
> > > Hi Adam,
> > >
> > > Am Mittwoch, dem 19.04.2023 um 05:47 -0500 schrieb Adam Ford:
> > > > On Mon, Apr 17,
On 2023-04-20 04:03:31, Dmitry Baryshkov wrote:
[..]
> >>> -static void dpu_hw_setup_vsync_source(struct dpu_hw_mdp *mdp,
> >>> +static void dpu_hw_setup_vsync_source_v1(struct dpu_hw_mdp *mdp,
> >>> struct dpu_vsync_source_cfg *cfg)
> >>
> >> In my opinion _v1 is not really
On 2023-04-20 03:47:57, Dmitry Baryshkov wrote:
> On 17/04/2023 23:21, Marijn Suijten wrote:
> > A bunch of registers were appended at the end in e.g. 91143873a05d
> > ("drm/msm/dpu: Add MISR register support for interface") rather than
> > being inserted in a place that maintains numerical
On Thu, Apr 20, 2023 at 02:23:22PM -0700, Matt Roper wrote:
> On Thu, Apr 20, 2023 at 11:13:52PM +0200, Andi Shyti wrote:
> > From: Madhumitha Tolakanahalli Pradeep
> >
> >
> > On MTL, GT can no longer allocate on LLC - only the CPU can.
> > This, along with addition of support for L4 cache
On 2023-04-20 08:46:46, Abhinav Kumar wrote:
>
>
> On 4/20/2023 7:33 AM, Dmitry Baryshkov wrote:
> > On 18/04/2023 02:14, Marijn Suijten wrote:
> >> Some of these members were initialized while never read, while others
> >> were not even assigned any value at all. Drop them to save some space,
On Thu, Apr 20, 2023 at 01:38:59PM +0200, Nirmoy Das wrote:
> From: Fei Yang
>
> This patch implements Wa_22016122933.
>
> In MTL, memory writes initiated by Media tile update the whole
> cache line even for partial writes. This creates a coherency
> problem for cacheable memory if both CPU and
On Thu, Apr 20, 2023 at 2:59 PM Christian König
wrote:
> Could you try drm-misc-next as well?
If as I assume I cloned right repo
$ git clone -b drm-misc-next
git://anongit.freedesktop.org/drm/drm-misc linux-drm-misc-next
for my hardware last commit on this branch is turned out completely
On Thu, Apr 20, 2023 at 11:13:52PM +0200, Andi Shyti wrote:
> From: Madhumitha Tolakanahalli Pradeep
>
>
> On MTL, GT can no longer allocate on LLC - only the CPU can.
> This, along with addition of support for L4 cache calls for
> a MOCS/PAT table update.
> Also the PAT index registers are
From: Madhumitha Tolakanahalli Pradeep
On MTL, GT can no longer allocate on LLC - only the CPU can.
This, along with addition of support for L4 cache calls for
a MOCS/PAT table update.
Also the PAT index registers are multicasted for primary GT,
and there is an address jump from index 7 to 8.
On Wed, Apr 19, 2023 at 04:00:56PM -0700, fei.y...@intel.com wrote:
> From: Fei Yang
>
> This patch is a preparation for replacing enum i915_cache_level with PAT
> index. Caching policy for buffer objects is set through the PAT index in
> PTE, the old i915_cache_level is not sufficient to
On Wed, Apr 19, 2023 at 04:00:55PM -0700, fei.y...@intel.com wrote:
> From: Fei Yang
>
> The design is to keep Buffer Object's caching policy immutable through
> out its life cycle. This patch ends the support for set caching ioctl
> from MTL onward. While doing that we also set BO's to be 1-way
On Wed, Apr 19, 2023 at 04:00:54PM -0700, fei.y...@intel.com wrote:
> From: Fei Yang
>
> This patch implements Wa_22016122933.
>
> In MTL, memory writes initiated by Media tile update the whole
> cache line even for partial writes. This creates a coherency
> problem for cacheable memory if both
On Wed, Apr 19, 2023 at 04:00:53PM -0700, fei.y...@intel.com wrote:
> From: Fei Yang
>
> PTE encode functions are platform dependent. This patch implements
> PTE functions for MTL, and ensures the correct PTE encode function
> is used by calling pte_encode function pointer instead of the
>
On Wed, Apr 19, 2023 at 04:00:52PM -0700, fei.y...@intel.com wrote:
> From: Madhumitha Tolakanahalli Pradeep
>
>
> On MTL, GT can no longer allocate on LLC - only the CPU can.
> This, along with addition of support for L4 cache calls for
> a MOCS/PAT table update.
> Also the PAT index registers
On Tue, 18 Apr 2023 10:06:57 -0500, Rob Herring wrote:
> The trailing "/" in "lvds.yaml/#" is not a valid JSON pointer. The existing
> jsonschema package allows it, but coming changes make allowed "$ref" URIs
> stricter.
>
> Signed-off-by: Rob Herring
> ---
>
On 4/20/2023 11:49 AM, Teres Alexis, Alan Previn wrote:
On Wed, 2023-03-29 at 09:56 -0700, Ceraolo Spurio, Daniele wrote:
The GSC notifies us of a proxy request via the HECI2 interrupt. The
alan:snip
@@ -256,6 +262,7 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
u32 irqs =
On 2023-03-28 10:31:29 +0800, Zongmin Zhou wrote:
> When drivers call drm_kms_helper_poll_disable from
> their device suspend implementation without enabled output polling before,
> following warning will be reported,due to work->func not be initialized:
we see the same warning with the wpork in
On 20/04/2023 22:53, Abhinav Kumar wrote:
On 4/20/2023 12:51 PM, Dmitry Baryshkov wrote:
On 20/04/2023 22:47, Abhinav Kumar wrote:
On 4/20/2023 11:01 AM, Dmitry Baryshkov wrote:
On 20/04/2023 04:36, Konrad Dybcio wrote:
On 20.04.2023 03:28, Abhinav Kumar wrote:
On 4/19/2023 6:26 PM,
The regdma is currently not used by the current driver. We have no way
to practically verify that the regdma is described correctly. Drop it
now.
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 2 -
.../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h| 2 -
On Thu, 20 Apr 2023 at 23:01, Janne Grunau wrote:
>
> On 2023-03-28 10:31:29 +0800, Zongmin Zhou wrote:
> > When drivers call drm_kms_helper_poll_disable from
> > their device suspend implementation without enabled output polling before,
> > following warning will be reported,due to work->func
On 2023-04-20 22:51:22, Dmitry Baryshkov wrote:
> On 20/04/2023 22:47, Abhinav Kumar wrote:
> >
> >
> > On 4/20/2023 11:01 AM, Dmitry Baryshkov wrote:
> >> On 20/04/2023 04:36, Konrad Dybcio wrote:
> >>>
> >>>
> >>> On 20.04.2023 03:28, Abhinav Kumar wrote:
>
>
> On 4/19/2023 6:26
On 4/20/2023 12:51 PM, Dmitry Baryshkov wrote:
On 20/04/2023 22:47, Abhinav Kumar wrote:
On 4/20/2023 11:01 AM, Dmitry Baryshkov wrote:
On 20/04/2023 04:36, Konrad Dybcio wrote:
On 20.04.2023 03:28, Abhinav Kumar wrote:
On 4/19/2023 6:26 PM, Konrad Dybcio wrote:
On 20.04.2023
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