On 2/10/2024 1:46 PM, Dmitry Baryshkov wrote:
On Sat, 10 Feb 2024 at 20:50, Abhinav Kumar wrote:
On 2/10/2024 10:14 AM, Abhinav Kumar wrote:
On 2/10/2024 2:09 AM, Dmitry Baryshkov wrote:
On Sat, 10 Feb 2024 at 03:52, Paloma Arellano
wrote:
Add support to pack and send the VSC SDP
On 2/10/2024 2:16 AM, Dmitry Baryshkov wrote:
On Sat, 10 Feb 2024 at 03:52, Paloma Arellano wrote:
DP controller can be setup to operate in either SDP update flush mode or
peripheral flush mode based on the DP controller hardware version.
Starting in DP v1.2, the hardware documents
-by: Paloma Arellano
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/display/drm_dp_helper.c | 21 +
include/drm/display/drm_dp_helper.h | 1 +
2 files changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dp_helper.c
b/drivers/gpu/drm/display/drm_dp_helper.c
On 2/10/2024 3:33 AM, Dmitry Baryshkov wrote:
On Sat, 10 Feb 2024 at 03:52, Paloma Arellano wrote:
All the components of YUV420 over DP are added. Therefore, let's mark the
connector property as true for DP connector when the DP type is not eDP
and when there is a CDM block available.
On 2/10/2024 10:14 AM, Abhinav Kumar wrote:
On 2/10/2024 2:09 AM, Dmitry Baryshkov wrote:
On Sat, 10 Feb 2024 at 03:52, Paloma Arellano
wrote:
Add support to pack and send the VSC SDP packet for DP. This therefore
allows the transmision of format information to the sinks which is
needed
On 2/10/2024 2:09 AM, Dmitry Baryshkov wrote:
On Sat, 10 Feb 2024 at 03:52, Paloma Arellano wrote:
Add support to pack and send the VSC SDP packet for DP. This therefore
allows the transmision of format information to the sinks which is
needed for YUV420 support over DP.
Changes in v2:
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 8
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h | 1 -
2 files changed, 9 deletions(-)
Reviewed-by: Abhinav Kumar
changed, 15 insertions(+), 49 deletions(-)
Nice cleanup !
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 8
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 -
2 files changed, 9 deletions(-)
Reviewed-by: Abhinav Kumar
changed, 8 insertions(+)
Reviewed-by: Abhinav Kumar
version of msm_ioremap_mdss for
vbif_nrt_phys?
Anyway, its not something to block this change. Hence,
Reviewed-by: Abhinav Kumar
++
1 file changed, 51 insertions(+)
Reviewed-by: Abhinav Kumar
insertions(+), 59 deletions(-)
+
+ crtc = conn_state->crtc;
+ if (!crtc)
+ return 0;
+
This should fix the crash and rest of the change LGTM
Reviewed-by: Abhinav Kumar
Please give us a couple of days to re-test this and give our Tested-by
as we plan to rebase
msm/dsi/dsi_host.c | 33 +++--
1 file changed, 31 insertions(+), 2 deletions(-)
Reviewed-by: Abhinav Kumar
On 2/8/2024 5:46 AM, Abel Vesa wrote:
On 24-02-08 15:42:04, Dmitry Baryshkov wrote:
On Thu, 8 Feb 2024 at 15:37, Abel Vesa wrote:
On 24-01-29 17:11:25, Dmitry Baryshkov wrote:
On Mon, 29 Jan 2024 at 15:19, Abel Vesa wrote:
Add support for MDSS on X1E80100.
Signed-off-by: Abel Vesa
On 2/7/2024 11:56 AM, Dmitry Baryshkov wrote:
On Wed, 7 Feb 2024 at 20:48, Abhinav Kumar wrote:
On 1/5/2024 3:34 PM, Dmitry Baryshkov wrote:
Existing MDP5 devices have slightly different bindings. The main
register region is called `mdp_phys' instead of `mdp'. Also vbif
register regions
but certainly
not all, but based on whatever I checked all the entries were correct in
the catalog.
Reviewed-by: Abhinav Kumar
platforms supported by both drivers are by default handled by the
MDP5 driver. To let them be handled by the DPU driver pass the
`msm.prefer_mdp5=false` kernel param.
Reviewed-by: Stephen Boyd
Signed-off-by: Dmitry Baryshkov
---
Reviewed-by: Abhinav Kumar
On 1/5/2024 3:34 PM, Dmitry Baryshkov wrote:
Existing MDP5 devices have slightly different bindings. The main
register region is called `mdp_phys' instead of `mdp'. Also vbif
register regions are a part of the parent, MDSS device. Add support for
handling this binding differences.
On 1/5/2024 3:34 PM, Dmitry Baryshkov wrote:
Older (mdp5) platforms do not use per-SoC compatible strings. Instead
they use a single compat entry 'qcom,mdss'. To facilitate migrating
these platforms to the DPU driver provide a way to generate the MDSS /
UBWC data at runtime, when the DPU
On 10/5/2023 3:06 PM, Dmitry Baryshkov wrote:
The frame event callback is always set to dpu_crtc_frame_event_cb() (or
to NULL) and the data is always either the CRTC itself or NULL
(correpondingly). Thus drop the event callback registration, call the
dpu_crtc_frame_event_cb() directly and
up to maintain this
Reviewed-by: Abhinav Kumar
---
.../devicetree/bindings/display/bridge/ti,sn65dsi86.yaml| 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml
b/Documentation/devicetree/bindings/display
On 1/31/2024 8:36 PM, Dmitry Baryshkov wrote:
On Thu, 1 Feb 2024 at 03:56, Abhinav Kumar wrote:
On 1/27/2024 9:39 PM, Dmitry Baryshkov wrote:
On Sun, 28 Jan 2024 at 07:34, Paloma Arellano wrote:
On 1/25/2024 1:48 PM, Dmitry Baryshkov wrote:
On 25/01/2024 21:38, Paloma Arellano
On 1/31/2024 7:17 PM, Dmitry Baryshkov wrote:
On Thu, 1 Feb 2024 at 03:30, Abhinav Kumar wrote:
On 1/29/2024 3:44 PM, Dmitry Baryshkov wrote:
On Mon, 29 Jan 2024 at 09:08, Abhinav Kumar wrote:
On 1/28/2024 10:12 PM, Dmitry Baryshkov wrote:
On Mon, 29 Jan 2024 at 07:03, Abhinav Kumar
On 1/27/2024 9:39 PM, Dmitry Baryshkov wrote:
On Sun, 28 Jan 2024 at 07:34, Paloma Arellano wrote:
On 1/25/2024 1:48 PM, Dmitry Baryshkov wrote:
On 25/01/2024 21:38, Paloma Arellano wrote:
Add support to pack and send the VSC SDP packet for DP. This therefore
allows the transmision of
On 1/29/2024 3:44 PM, Dmitry Baryshkov wrote:
On Mon, 29 Jan 2024 at 09:08, Abhinav Kumar wrote:
On 1/28/2024 10:12 PM, Dmitry Baryshkov wrote:
On Mon, 29 Jan 2024 at 07:03, Abhinav Kumar wrote:
On 1/28/2024 7:42 PM, Dmitry Baryshkov wrote:
On Mon, 29 Jan 2024 at 04:58, Abhinav
On 1/31/2024 5:05 PM, Dmitry Baryshkov wrote:
On Thu, 1 Feb 2024 at 02:48, Abhinav Kumar wrote:
Currently INTF_CFG2_DATA_HCTL_EN is coupled with the enablement
of widebus but this is incorrect because we should be enabling
this bit independent of widebus except for cases where compression
and enabling
INTF_CFG2_DATA_HCTL_EN for all other cases when supported by DPU.
Fixes: 3309a7563971 ("drm/msm/dpu: revise timing engine programming to support
widebus feature")
Suggested-by: Dmitry Baryshkov
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
On 1/29/2024 9:28 PM, Dmitry Baryshkov wrote:
On Tue, 30 Jan 2024 at 06:10, Abhinav Kumar wrote:
On 1/29/2024 5:43 PM, Dmitry Baryshkov wrote:
On Tue, 30 Jan 2024 at 03:07, Abhinav Kumar wrote:
On 1/29/2024 4:03 PM, Dmitry Baryshkov wrote:
On Tue, 30 Jan 2024 at 01:51, Abhinav
On 1/29/2024 5:43 PM, Dmitry Baryshkov wrote:
On Tue, 30 Jan 2024 at 03:07, Abhinav Kumar wrote:
On 1/29/2024 4:03 PM, Dmitry Baryshkov wrote:
On Tue, 30 Jan 2024 at 01:51, Abhinav Kumar wrote:
On 1/27/2024 9:33 PM, Dmitry Baryshkov wrote:
On Sun, 28 Jan 2024 at 07:16, Paloma
On 1/29/2024 4:03 PM, Dmitry Baryshkov wrote:
On Tue, 30 Jan 2024 at 01:51, Abhinav Kumar wrote:
On 1/27/2024 9:33 PM, Dmitry Baryshkov wrote:
On Sun, 28 Jan 2024 at 07:16, Paloma Arellano wrote:
On 1/25/2024 1:26 PM, Dmitry Baryshkov wrote:
On 25/01/2024 21:38, Paloma Arellano
On 1/27/2024 9:33 PM, Dmitry Baryshkov wrote:
On Sun, 28 Jan 2024 at 07:16, Paloma Arellano wrote:
On 1/25/2024 1:26 PM, Dmitry Baryshkov wrote:
On 25/01/2024 21:38, Paloma Arellano wrote:
INTF_CONFIG2 register cannot have widebus enabled when DP format is
YUV420. Therefore, program the
Hi Maxime
On 1/26/2024 4:45 AM, Maxime Ripard wrote:
On Wed, Jan 17, 2024 at 09:36:20AM -0800, Abhinav Kumar wrote:
Hi Jani and Maxime
On 1/17/2024 2:16 AM, Jani Nikula wrote:
On Wed, 17 Jan 2024, Maxime Ripard wrote:
Hi,
On Tue, Jan 16, 2024 at 02:22:03PM -0800, Jessica Zhang wrote
On 1/28/2024 10:12 PM, Dmitry Baryshkov wrote:
On Mon, 29 Jan 2024 at 07:03, Abhinav Kumar wrote:
On 1/28/2024 7:42 PM, Dmitry Baryshkov wrote:
On Mon, 29 Jan 2024 at 04:58, Abhinav Kumar wrote:
On 1/27/2024 9:55 PM, Dmitry Baryshkov wrote:
On Sun, 28 Jan 2024 at 07:48, Paloma
On 1/28/2024 9:05 PM, Dmitry Baryshkov wrote:
On Mon, 29 Jan 2024 at 06:30, Abhinav Kumar wrote:
On 1/28/2024 7:52 PM, Dmitry Baryshkov wrote:
On Mon, 29 Jan 2024 at 05:17, Abhinav Kumar wrote:
On 1/25/2024 2:05 PM, Dmitry Baryshkov wrote:
On 25/01/2024 21:38, Paloma Arellano
On 1/28/2024 7:42 PM, Dmitry Baryshkov wrote:
On Mon, 29 Jan 2024 at 04:58, Abhinav Kumar wrote:
On 1/27/2024 9:55 PM, Dmitry Baryshkov wrote:
On Sun, 28 Jan 2024 at 07:48, Paloma Arellano wrote:
On 1/25/2024 1:57 PM, Dmitry Baryshkov wrote:
On 25/01/2024 21:38, Paloma Arellano
On 1/28/2024 8:12 PM, Dmitry Baryshkov wrote:
On Mon, 29 Jan 2024 at 06:01, Abhinav Kumar wrote:
On 1/28/2024 7:23 PM, Dmitry Baryshkov wrote:
On Mon, 29 Jan 2024 at 05:06, Abhinav Kumar wrote:
On 1/26/2024 4:39 PM, Paloma Arellano wrote:
On 1/25/2024 1:14 PM, Dmitry Baryshkov
On 1/28/2024 7:52 PM, Dmitry Baryshkov wrote:
On Mon, 29 Jan 2024 at 05:17, Abhinav Kumar wrote:
On 1/25/2024 2:05 PM, Dmitry Baryshkov wrote:
On 25/01/2024 21:38, Paloma Arellano wrote:
All the components of YUV420 over DP are added. Therefore, let's mark the
connector property
On 1/28/2024 7:23 PM, Dmitry Baryshkov wrote:
On Mon, 29 Jan 2024 at 05:06, Abhinav Kumar wrote:
On 1/26/2024 4:39 PM, Paloma Arellano wrote:
On 1/25/2024 1:14 PM, Dmitry Baryshkov wrote:
On 25/01/2024 21:38, Paloma Arellano wrote:
Generalize dpu_encoder_helper_phys_setup_cdm
On 1/25/2024 2:05 PM, Dmitry Baryshkov wrote:
On 25/01/2024 21:38, Paloma Arellano wrote:
All the components of YUV420 over DP are added. Therefore, let's mark the
connector property as true for DP connector when the DP type is not eDP
and when VSC SDP is supported.
Signed-off-by: Paloma
On 1/26/2024 4:39 PM, Paloma Arellano wrote:
On 1/25/2024 1:14 PM, Dmitry Baryshkov wrote:
On 25/01/2024 21:38, Paloma Arellano wrote:
Generalize dpu_encoder_helper_phys_setup_cdm to be compatible with DP.
Signed-off-by: Paloma Arellano
---
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
On 1/27/2024 9:55 PM, Dmitry Baryshkov wrote:
On Sun, 28 Jan 2024 at 07:48, Paloma Arellano wrote:
On 1/25/2024 1:57 PM, Dmitry Baryshkov wrote:
On 25/01/2024 21:38, Paloma Arellano wrote:
Adjust the encoder format programming in the case of video mode for DP
to accommodate CDM related
On 1/26/2024 6:40 PM, Dmitry Baryshkov wrote:
On Sat, 27 Jan 2024 at 02:58, Paloma Arellano wrote:
On 1/25/2024 1:23 PM, Dmitry Baryshkov wrote:
On 25/01/2024 21:38, Paloma Arellano wrote:
YUV420 format is supported only in the VSC SDP packet and not through
MSA. Hence add an API which
On 1/5/2024 3:50 PM, Dmitry Baryshkov wrote:
We have several reports of vblank timeout messages. However after some
debugging it was found that there might be different causes to that.
Include the actual CTL_FLUSH value into the timeout message. This allows
us to identify the DPU block that
On 1/10/2024 12:18 PM, Kuogee Hsieh wrote:
Since the value of DP_TEST_BIT_DEPTH_8 is already left shifted, in the
BPC unknown case, the additional shift causes spill over to the other
bits of the [DP_CONFIGURATION_CTRL] register.
Fix this by changing the return value of
'
Signed-off-by: Randy Dunlap
Cc: Rob Clark
Cc: Abhinav Kumar
Cc: Dmitry Baryshkov
Cc: Sean Paul
Cc: Marijn Suijten
Cc: linux-arm-...@vger.kernel.org
Cc: dri-devel@lists.freedesktop.org
Cc: freedr...@lists.freedesktop.org
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Thomas Zimmermann
Cc
On 12/18/2023 9:57 AM, Abhinav Kumar wrote:
On 12/16/2023 4:01 PM, Dmitry Baryshkov wrote:
Drop obsolete kerneldoc for several fields in struct dpu_encoder_virt
Reported-by: kernel test robot
Closes:
https://lore.kernel.org/oe-kbuild-all/202312170641.5exlvqqx-...@intel.com/
Fixes
On 12/25/2023 5:08 AM, Dmitry Baryshkov wrote:
dpu_encoder_phys_wb is the only user of encoder's atomic_check callback.
Move corresponding checks to drm_writeback_connector's implementation
and drop the dpu_encoder_phys_wb_atomic_check() function.
Signed-off-by: Dmitry Baryshkov
---
the other conditional block by making sure hw_pp is valid
before dereferencing it.
Reported-by: Dan Carpenter
Fixes: ae4d721ce100 ("drm/msm/dpu: add an API to reset the encoder related hw
blocks")
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4 ++-
Hi Jani and Maxime
On 1/17/2024 2:16 AM, Jani Nikula wrote:
On Wed, 17 Jan 2024, Maxime Ripard wrote:
Hi,
On Tue, Jan 16, 2024 at 02:22:03PM -0800, Jessica Zhang wrote:
This series introduces a simulated MIPI DSI panel.
Currently, the only way to validate DSI connectors is with a physical
files changed, 1 insertion(+), 24 deletions(-)
Reviewed-by: Abhinav Kumar
2 files changed, 7 insertions(+), 8 deletions(-)
Reviewed-by: Abhinav Kumar
. If someone wants to add that
support, I guess they have to start by reverting this commit first. If
thats the plan and agreement,
Reviewed-by: Abhinav Kumar
++
drivers/gpu/drm/msm/dsi/dsi_manager.c | 8 +++-
3 files changed, 6 insertions(+), 12 deletions(-)
Reviewed-by: Abhinav Kumar
s changed, 40 deletions(-)
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/dsi.h | 6 --
drivers/gpu/drm/msm/dsi/dsi_manager.c | 5 -
2 files changed, 11 deletions(-)
Reviewed-by: Abhinav Kumar
| 8 +---
drivers/gpu/drm/msm/dsi/dsi.h | 7 ++-
drivers/gpu/drm/msm/dsi/dsi_manager.c | 19 ---
3 files changed, 15 insertions(+), 19 deletions(-)
Reviewed-by: Abhinav Kumar
On 1/9/2024 7:31 AM, Rob Clark wrote:
On Mon, Jan 8, 2024 at 6:13 PM Rob Clark wrote:
On Mon, Jan 8, 2024 at 2:58 PM Abhinav Kumar wrote:
On 1/8/2024 11:50 AM, Rob Clark wrote:
From: Rob Clark
The msm tests should skip on non-msm hw, so I think it should be safe to
enable
On 1/8/2024 11:50 AM, Rob Clark wrote:
From: Rob Clark
The msm tests should skip on non-msm hw, so I think it should be safe to
enable everywhere.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/ci/testlist.txt | 49 +
1 file changed, 49 insertions(+)
I
On 12/25/2023 5:08 AM, Dmitry Baryshkov wrote:
The dpu_encoder_phys_ops::atomic_mode_set() callback is mostly
redundant. Implementations only set the IRQ indices there. Move
statically allocated IRQs to dpu_encoder_phys_*_init() and set
dynamically allocated IRQs in the irq_enable() callback.
/dpu_encoder.c | 15 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 4
2 files changed, 19 deletions(-)
Same comment as prev change but otherwise
Reviewed-by: Abhinav Kumar
(-)
I am fine with this change with respect to how the code is today.
Hence,
Reviewed-by: Abhinav Kumar
But if we start noticing a pattern like below in dpu_encoder.c's
atomic_check,
if (INTF_WB)
.
else if (INTF_DP || INTF_DSI)
.
then, it will demand bringing back a phys specific
+
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 12 --
2 files changed, 37 insertions(+), 20 deletions(-)
Reviewed-by: Abhinav Kumar
++---
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 62 ++
6 files changed, 158 insertions(+), 86 deletions(-)
Reviewed-by: Abhinav Kumar
path")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 1 +
1 file changed, 1 insertion(+)
Reviewed-by: Abhinav Kumar
tatus to standard encoder debugfs
dir")
Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4
1 file changed, 4 deletions(-)
Reviewed-by: Abhinav Kumar
es changed, 22 insertions(+), 33 deletions(-)
Reviewed-by: Abhinav Kumar
deletions(-)
Reviewed-by: Abhinav Kumar
en = 0x2c8,
+ .features = WB_SDM845_MASK,
+ .format_list = wb2_formats,
+ .num_formats = ARRAY_SIZE(wb2_formats),
+ .clk_ctrl = DPU_CLK_CTRL_WB2,
This should now be wb2_formats_rgb.
With that fixed,
Reviewed-by: Abhinav Kumar
+ .
en = 0x2c8,
+ .features = WB_SDM845_MASK,
+ .format_list = wb2_formats,
+ .num_formats = ARRAY_SIZE(wb2_formats),
This should now be wb2_formats_rgb.
With that fixed,
Reviewed-by: Abhinav Kumar
+ .clk_ctrl = DPU_CLK_CTRL_WB2,
+ .
en = 0x2c8,
+ .features = WB_SDM845_MASK,
+ .format_list = wb2_formats,
+ .num_formats = ARRAY_SIZE(wb2_formats),
This should now be wb2_formats_rgb.
With that fixed,
Reviewed-by: Abhinav Kumar
+ .clk_ctrl = DPU_CLK_CTRL_WB2,
+ .
On 12/11/2023 10:23 PM, Dmitry Baryshkov wrote:
On Tue, 12 Dec 2023 at 02:30, Abhinav Kumar wrote:
On 12/2/2023 4:31 PM, Dmitry Baryshkov wrote:
I was not able to test it on my own, this is a call for testing for the
owners of these platforms. The git version of modetest now fully
On 12/13/2023 12:51 PM, Jessica Zhang wrote:
Set the input_sel bit for encoders as it was missed in the initial
implementation.
Reported-by: Rob Clark
Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/39
Fixes: 91143873a05d ("drm/msm/dpu: Add MISR register support for interface")
On 12/13/2023 12:51 PM, Jessica Zhang wrote:
Drop the enable and frame_count parameters from dpu_hw_setup_misr() as they
are always set to the same values.
In addition, replace MISR_FRAME_COUNT_MASK with MISR_FRAME_COUNT as
frame_count is always set to the same value.
Fixes: 7b37523fb1d1
/dpu_hw_util.h | 44 ++---
2 files changed, 47 insertions(+), 41 deletions(-)
Strange, I didnt hit this but change LGTM,
Reviewed-by: Abhinav Kumar
On 12/12/2023 2:03 PM, Dmitry Baryshkov wrote:
On Tue, 12 Dec 2023 at 23:30, Dmitry Baryshkov
wrote:
On Tue, 12 Dec 2023 at 22:53, Abhinav Kumar wrote:
In preparation for adding more formats to dpu writeback add
format validation to it to fail any unsupported formats.
changes in v4
into this change
changes in v2:
- use needs_cdm from topology struct
- drop fb related checks from atomic_mode_set()
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 37 +
1 file changed, 37 insertions
support for CDM block will use the newly added
wb2_formats_rgb_yuv array.
changes in v3:
- change type of wb2_formats_rgb/wb2_formats_rgb_yuv to u32
to fix checkpatch warnings
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog
Now that CDM block support has been added to DPU lets also add its
entry to the DPU snapshot to help debugging.
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/msm
as they both have been merged into enable()
- drop reduntant hw_cdm and hw_pp checks
Reported-by: kernel test robot
Closes:
https://lore.kernel.org/oe-kbuild-all/202312102149.qmbcdsg2-...@intel.com/
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1
-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
index 3e5dbaa9c896
nto enable()
Reported-by: kernel test robot
Closes:
https://lore.kernel.org/oe-kbuild-all/202312101815.b3zh7pfy-...@intel.com/
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/Makefile| 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c | 245
drivers/g
:
- remove unused empty line
- pass in cdm_num to update_pending_flush_cdm()
Reported-by: kernel test robot
Closes:
https://lore.kernel.org/oe-kbuild-all/202312102047.s0i69pcs-...@intel.com/
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp
Add the RM APIs necessary to initialize and allocate CDM
blocks to be used by the rest of the DPU pipeline.
changes in v2:
- treat cdm_init() failure as fatal
- fixed the commit text
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1
Add CDM blocks to the sm8250 dpu_hw_catalog to support
YUV format output from writeback block.
changes in v2:
- re-use the cdm definition from sc7280
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 1 +
1 file
struct
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 38 +++--
drivers/gpu/drm/msm/msm_drv.h | 2 ++
4
catalog file as its definition can be re-used
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 10 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
the extra wrapper and export the matrices directly
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 30
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 31 +
2 files changed, 31 insertions(+), 30
phys_* for
writeback")
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
b/drivers/gpu/drm/msm
For YUV cases, setting the required format bits was missed
out in the register programming. Lets fix it now in preparation
of adding YUV formats support for writeback.
changes in v2:
- dropped the fixes tag as its not a fix but adding
new functionality
Signed-off-by: Abhinav Kumar
drm_atomic_helper_check_wb_encoder_state() with
drm_atomic_helper_check_wb_connector_state() due to the
rebase
changes in v2:
- correct some grammar in the commit text
Fixes: d7d0e73f7de3 ("drm/msm/dpu: introduce the dpu_encoder_phys_* for
writeback")
Signed-off-by: Abhinav Kumar
---
drive
they both have been merged into enable()
- drop reduntant hw_cdm and hw_pp checks
- drop fb related checks from dpu_encoder::atomic_mode_set()
- introduce separate wb2_format arrays for rgb and yuv
Abhinav Kumar (15):
drm/msm/dpu: add formats check for writeback encoder
On 12/12/2023 1:40 AM, Dmitry Baryshkov wrote:
On Tue, 12 Dec 2023 at 02:23, Abhinav Kumar wrote:
CDM block comes with its own set of registers and operations
which can be done. In-line with other hardware blocks, this
change adds the dpu_hw_cdm abstraction for the CDM block.
changes
On 12/11/2023 10:40 PM, Dmitry Baryshkov wrote:
On Tue, 12 Dec 2023 at 02:23, Abhinav Kumar wrote:
In preparation for adding more formats to dpu writeback add
format validation to it to fail any unsupported formats.
changes in v3:
- rebase on top of msm-next
- replace
On 12/2/2023 4:31 PM, Dmitry Baryshkov wrote:
I was not able to test it on my own, this is a call for testing for the
owners of these platforms. The git version of modetest now fully
supports writeback.
Use libdrm >= 2.4.117, run modetest -ac to determine the writeback
connector, cat
Now that CDM block support has been added to DPU lets also add its
entry to the DPU snapshot to help debugging.
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/msm
support for CDM block will use the newly added
wb2_formats_rgb_yuv array.
changes in v3:
- change type of wb2_formats_rgb/wb2_formats_rgb_yuv to u32
to fix checkpatch warnings
Signed-off-by: Abhinav Kumar
---
.../msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 4 +-
.../msm/disp
as they both have been merged into enable()
- drop reduntant hw_cdm and hw_pp checks
Reported-by: kernel test robot
Closes:
https://lore.kernel.org/oe-kbuild-all/202312102149.qmbcdsg2-...@intel.com/
Signed-off-by: Abhinav Kumar
---
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 6
Add CDM blocks to the sm8250 dpu_hw_catalog to support
YUV format output from writeback block.
changes in v2:
- re-use the cdm definition from sc7280
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 1 +
1 file
:
- remove unused empty line
- pass in cdm_num to update_pending_flush_cdm()
Reported-by: kernel test robot
Closes:
https://lore.kernel.org/oe-kbuild-all/202312102047.s0i69pcs-...@intel.com/
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp
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