struct
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 38 +++--
drivers/gpu/drm/msm/msm_drv.h | 2 ++
4
For YUV cases, setting the required format bits was missed
out in the register programming. Lets fix it now in preparation
of adding YUV formats support for writeback.
changes in v2:
- dropped the fixes tag as its not a fix but adding
new functionality
Signed-off-by: Abhinav Kumar
- drop setup_csc_data() and setup_cdwn() ops as they
are merged into enable()
Reported-by: kernel test robot
Closes:
https://lore.kernel.org/oe-kbuild-all/202312101815.b3zh7pfy-...@intel.com/
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/Makefile| 1 +
drivers/gpu/dr
catalog file as its definition can be re-used
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 10 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
the extra wrapper and export the matrices directly
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 30
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 31 +
2 files changed, 31 insertions(+), 30 deletions(-)
diff --git
phys_* for
writeback")
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
b/drivers/gpu/drm/msm
to the
rebase
changes in v2:
- correct some grammar in the commit text
Fixes: d7d0e73f7de3 ("drm/msm/dpu: introduce the dpu_encoder_phys_* for
writeback")
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 7 +++
1 file changed, 7
- drop reduntant hw_cdm and hw_pp checks
- drop fb related checks from dpu_encoder::atomic_mode_set()
- introduce separate wb2_format arrays for rgb and yuv
Abhinav Kumar (15):
drm/msm/dpu: add formats check for writeback encoder
drm/msm/dpu: rename dpu_encoder_phys_wb
On 12/11/2023 1:42 PM, Dmitry Baryshkov wrote:
On Mon, 11 Dec 2023 at 23:32, Abhinav Kumar wrote:
On 12/11/2023 1:31 PM, Dmitry Baryshkov wrote:
On Mon, 11 Dec 2023 at 23:16, Abhinav Kumar wrote:
On 12/8/2023 3:19 AM, Dmitry Baryshkov wrote:
On Fri, 8 Dec 2023 at 07:07, Abhinav
On 12/11/2023 1:31 PM, Dmitry Baryshkov wrote:
On Mon, 11 Dec 2023 at 23:16, Abhinav Kumar wrote:
On 12/8/2023 3:19 AM, Dmitry Baryshkov wrote:
On Fri, 8 Dec 2023 at 07:07, Abhinav Kumar wrote:
Add CDM blocks to the sc7280 dpu_hw_catalog to support
YUV format output from writeback
() calls.
Fixes: cd42c56d9c0b ("drm/msm/dpu: use drmm-managed allocation for
dpu_encoder_virt")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 ---
1 file changed, 3 deletions(-)
Reviewed-by: Abhinav Kumar
Tested-by: Abhinav Kumar #sm8250 CI
On 12/8/2023 3:19 AM, Dmitry Baryshkov wrote:
On Fri, 8 Dec 2023 at 07:07, Abhinav Kumar wrote:
Add CDM blocks to the sc7280 dpu_hw_catalog to support
YUV format output from writeback block.
changes in v2:
- remove explicit zero assignment for features
- move sc7280_cdm
/dpu1/dpu_encoder.c | 5 -
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 +
2 files changed, 5 insertions(+), 1 deletion(-)
Reviewed-by: Abhinav Kumar
On 12/8/2023 12:45 PM, Dmitry Baryshkov wrote:
On Fri, 8 Dec 2023 at 19:53, Abhinav Kumar wrote:
On 12/8/2023 3:44 AM, Dmitry Baryshkov wrote:
On Fri, 8 Dec 2023 at 07:07, Abhinav Kumar wrote:
Lets rename the existing wb2_formats array wb2_formats_rgb to indicate
that it has only RGB
On 12/8/2023 12:55 PM, Dmitry Baryshkov wrote:
On Fri, 8 Dec 2023 at 19:28, Abhinav Kumar wrote:
On 12/8/2023 3:52 AM, Dmitry Baryshkov wrote:
On Fri, 8 Dec 2023 at 07:07, Abhinav Kumar wrote:
Add an API dpu_encoder_helper_phys_setup_cdm() which can be used by
the writeback encoder
On 12/2/2023 4:27 PM, Dmitry Baryshkov wrote:
Enable WB2 hardware block, enabling writeback support on this platform.
Signed-off-by: Dmitry Baryshkov
---
.../drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 18 ++
1 file changed, 18 insertions(+)
Reviewed-by: Abhinav Kumar
On 12/2/2023 4:27 PM, Dmitry Baryshkov wrote:
Enable WB2 hardware block, enabling writeback support on this platform.
Signed-off-by: Dmitry Baryshkov
---
.../drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 18 ++
1 file changed, 18 insertions(+)
Reviewed-by: Abhinav
files changed, 22 insertions(+), 2 deletions(-)
Reviewed-by: Abhinav Kumar
On 12/8/2023 3:44 AM, Dmitry Baryshkov wrote:
On Fri, 8 Dec 2023 at 07:07, Abhinav Kumar wrote:
Lets rename the existing wb2_formats array wb2_formats_rgb to indicate
that it has only RGB formats and can be used on any chipset having a WB
block.
Introduce a new wb2_formats_rgb_yuv array
On 12/8/2023 4:14 AM, Dmitry Baryshkov wrote:
On Fri, 8 Dec 2023 at 07:06, Abhinav Kumar wrote:
Chroma Down Sampling (CDM) block is a hardware block in the DPU pipeline
which among other things has a CSC block that can convert RGB input
from the DPU to YUV data.
This block is more
On 12/8/2023 3:52 AM, Dmitry Baryshkov wrote:
On Fri, 8 Dec 2023 at 07:07, Abhinav Kumar wrote:
Add an API dpu_encoder_helper_phys_setup_cdm() which can be used by
the writeback encoder to setup the CDM block.
Currently, this is defined and used within the writeback's physical
encoder
On 12/8/2023 4:06 AM, Dmitry Baryshkov wrote:
On Fri, 8 Dec 2023 at 07:07, Abhinav Kumar wrote:
CDM block comes with its own set of registers and operations
which can be done. In-line with other hardware sub-blocks, this
I always thought that sub-blocks refer to the dpu_foo_sub_blks data
On 12/8/2023 8:38 AM, Dmitry Baryshkov wrote:
On Fri, 8 Dec 2023 at 18:34, Abhinav Kumar wrote:
On 12/8/2023 3:54 AM, Dmitry Baryshkov wrote:
On Fri, 8 Dec 2023 at 07:07, Abhinav Kumar wrote:
Reserve CDM blocks for writeback if the format of the output fb
is YUV. At the moment
On 12/8/2023 8:27 AM, Dmitry Baryshkov wrote:
On Fri, 8 Dec 2023 at 18:24, Abhinav Kumar wrote:
On 12/8/2023 3:12 AM, Dmitry Baryshkov wrote:
On Fri, 8 Dec 2023 at 07:07, Abhinav Kumar wrote:
Since the type and usage of CSC matrices is spanning across DPU
lets introduce a helper
On 12/8/2023 3:54 AM, Dmitry Baryshkov wrote:
On Fri, 8 Dec 2023 at 07:07, Abhinav Kumar wrote:
Reserve CDM blocks for writeback if the format of the output fb
is YUV. At the moment, the reservation is done only for writeback
but can easily be extended by relaxing the checks once other
On 12/8/2023 3:12 AM, Dmitry Baryshkov wrote:
On Fri, 8 Dec 2023 at 07:07, Abhinav Kumar wrote:
Since the type and usage of CSC matrices is spanning across DPU
lets introduce a helper to the dpu_hw_util to return the CSC
corresponding to the request type. This will help to add more
Now that CDM block support has been added to DPU lets also add its
entry to the DPU snapshot to help debugging.
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/msm
support for CDM block will use the newly added
wb2_formats_rgb_yuv array.
Signed-off-by: Abhinav Kumar
---
.../msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 4 +-
.../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h| 4 +-
.../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h| 4 +-
.../msm/disp/dpu1/catalog
- drop fb related checks from atomic_mode_set()
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 27 +
1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index
-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
index 85429c62d727
as they both have been merged into enable()
- drop reduntant hw_cdm and hw_pp checks
Signed-off-by: Abhinav Kumar
---
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 3 +
.../drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 96 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
In preparation of setting up CDM block, add the logic to disable it
properly during encoder cleanup.
changes in v2:
- call update_pending_flush_cdm even when bind_pingpong_blk
is not present
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
/free
- some formatting fixes
- inline _setup_cdm_ops()
- protect bind_pingpong_blk with core_rev check
- drop setup_csc_data() and setup_cdwn() ops as they
are merged into enable()
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/Makefile
struct
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 38 +++--
drivers/gpu/drm/msm/msm_drv.h | 2 ++
4 files changed, 40 insertions
Add the RM APIs necessary to initialize and allocate CDM
blocks to be used by the rest of the DPU pipeline.
changes in v2:
- treat cdm_init() failure as fatal
- fixed the commit text
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 13
Add CDM blocks to the sm8250 dpu_hw_catalog to support
YUV format output from writeback block.
changes in v2:
- re-use the cdm definition from sc7280
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 1 +
1 file changed, 1 insertion(+)
diff
CDM block will need its own logic to program the flush and active
bits in the dpu_hw_ctl layer.
Make necessary changes in dpu_hw_ctl to support CDM programming.
changes in v2:
- remove unused empty line
- pass in cdm_num to update_pending_flush_cdm()
Signed-off-by: Abhinav Kumar
-by: Abhinav Kumar
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 10 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 13 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 5 +
4 files changed
Since the type and usage of CSC matrices is spanning across DPU
lets introduce a helper to the dpu_hw_util to return the CSC
corresponding to the request type. This will help to add more
supported CSC types such as the RGB to YUV one which is used in
the case of CDM.
Signed-off-by: Abhinav Kumar
phys_* for
writeback")
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
b/drivers/gpu/drm/msm
For YUV cases, setting the required format bits was missed
out in the register programming. Lets fix it now in preparation
of adding YUV formats support for writeback.
changes in v2:
- dropped the fixes tag as its not a fix but adding
new functionality
Signed-off-by: Abhinav Kumar
In preparation for adding more formats to dpu writeback add
format validation to it to fail any unsupported formats.
changes in v2:
- correct some grammar in the commit text
Fixes: d7d0e73f7de3 ("drm/msm/dpu: introduce the dpu_encoder_phys_* for
writeback")
Signed-off-by: Abh
()
- introduce separate wb2_format arrays for rgb and yuv
Abhinav Kumar (16):
drm/msm/dpu: add formats check for writeback encoder
drm/msm/dpu: rename dpu_encoder_phys_wb_setup_cdp to match its
functionality
drm/msm/dpu: fix writeback programming for YUV cases
drm/msm/dpu: move csc matrices
On 8/30/2023 5:26 PM, Dmitry Baryshkov wrote:
On Thu, 31 Aug 2023 at 01:50, Abhinav Kumar wrote:
Since CDM block support has now been added for writeback blocks
add NV12 in the list of supported WB formats.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
On 11/30/2023 3:47 PM, Abhinav Kumar wrote:
On 8/30/2023 4:48 PM, Dmitry Baryshkov wrote:
On Thu, 31 Aug 2023 at 01:50, Abhinav Kumar
wrote:
Add the RM APIs necessary to initialize and allocate CDM
blocks by the rest of the DPU pipeline.
... to be used by the rest?
Yes, thanks
On 12/5/2023 7:51 PM, Bjorn Andersson wrote:
On Mon, Dec 04, 2023 at 11:22:24AM -0800, Abhinav Kumar wrote:
On 12/3/2023 7:31 PM, Bjorn Andersson wrote:
On Fri, Dec 01, 2023 at 11:43:36AM -0800, Abhinav Kumar wrote:
On 12/1/2023 8:22 AM, Bjorn Andersson wrote:
On Fri, Dec 01, 2023
/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
LGTM now.
Reviewed-by: Abhinav Kumar
On 12/5/2023 3:46 AM, Maxime Ripard wrote:
On Tue, Dec 05, 2023 at 12:05:02PM +0300, Dan Carpenter wrote:
On Tue, Dec 05, 2023 at 09:37:05AM +0100, Maxime Ripard wrote:
Hi Naresh,
Thanks for the report
On Mon, Dec 04, 2023 at 11:05:36PM +0530, Naresh Kamboju wrote:
The Kunit
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 11 +--
11 files changed, 26 insertions(+), 35 deletions(-)
Reviewed-by: Abhinav Kumar
. In order to simplify the driver
codepath, merge these three feature bits into QSEED3_COMPATIBLE bin.
Signed-off-by: Dmitry Baryshkov
---
Reviewed-by: Abhinav Kumar
(+), 39 deletions(-)
For this change,
Reviewed-by: Abhinav Kumar
Looking more closely at other drivers, most of them (atleast what I
checked) were doing the same functionality in drm_encoder's
late_register / early_unregister as DPU.
This can be a wider cleanup across the tree if needed or we
iles changed, 46 insertions(+), 4 deletions(-)
I checked the values with corresponding DT files and they match,
Reviewed-by: Abhinav Kumar
On 12/2/2023 2:42 PM, Dmitry Baryshkov wrote:
There are just two places where we set the bandwidth: in the resume and
in the suspend paths. Drop the wrapping function
msm_mdss_icc_request_bw() and call icc_set_bw() directly.
Signed-off-by: Dmitry Baryshkov
---
Reviewed-by: Abhinav Kumar
check if (mdp_path) OR even better if
icc has some sort of bulk_set_bw with num of paths.
Nothing these down but nothing to block this patch:
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/msm_mdss.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/driv
-by: Abhinav Kumar
atch. Only compile tested.
---
drivers/gpu/drm/msm/dp/dp_display.c | 1 +
1 file changed, 1 insertion(+)
Reviewed-by: Abhinav Kumar
On 12/3/2023 7:31 PM, Bjorn Andersson wrote:
On Fri, Dec 01, 2023 at 11:43:36AM -0800, Abhinav Kumar wrote:
On 12/1/2023 8:22 AM, Bjorn Andersson wrote:
On Fri, Dec 01, 2023 at 10:34:50AM +0200, Dmitry Baryshkov wrote:
On Fri, 1 Dec 2023 at 05:47, Bjorn Andersson wrote:
On Thu, Nov 30
to be added back when features such as
autorefresh get added. But, as usual, we go by what in the driver today
so I am aware that this will be a lost argument.
Hence,
Reviewed-by: Abhinav Kumar
On 12/4/2023 9:57 AM, Simon Ser wrote:
On Monday, December 4th, 2023 at 18:51, Abhinav Kumar
wrote:
Where are the IGT and userspace for this uAPI addition?
Yes, we made IGT changes to test and validate this. We will post them on
the IGT dev list shortly and CC you.
We do not have
Hi Simon
On 12/3/2023 4:15 AM, Simon Ser wrote:
On Saturday, December 2nd, 2023 at 22:41, Dmitry Baryshkov
wrote:
On Fri, 27 Oct 2023 15:32:50 -0700, Jessica Zhang wrote:
Some drivers support hardware that have optimizations for solid fill
planes. This series aims to expose these
On 12/3/2023 10:14 AM, Dmitry Baryshkov wrote:
On Sun, 3 Dec 2023 at 16:24, Laurent Pinchart
wrote:
Hi Abhinav,
Thank you for the patch (and thank to Dmitry for pinging me on IRC, this
patch got burried in my inbox).
On Wed, Sep 20, 2023 at 01:13:58PM -0700, Abhinav Kumar wrote:
While
On 7/7/2023 6:03 PM, Dmitry Baryshkov wrote:
MDP4 and MDP5 drivers enumerate supported formats each time the plane is
created. As the list of supported image formats is constant, create
corresponding data arrays to be used by MDP4 and MDP5 drivers.
Signed-off-by: Dmitry Baryshkov
---
On 12/1/2023 5:25 PM, Abhinav Kumar wrote:
On 7/7/2023 6:04 PM, Dmitry Baryshkov wrote:
Drop the function mdp_get_formats(), which became unused after
converting both MDP4 and MDP5 planes to use static formats arrays.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp
/gpu/drm/msm/disp/mdp_kms.h| 1 -
2 files changed, 25 deletions(-)
Reviewed-by: Abhinav Kumar
file changed, 20 insertions(+), 39 deletions(-)
Reviewed-by: Abhinav Kumar
---
1 file changed, 7 insertions(+), 29 deletions(-)
Reviewed-by: Abhinav Kumar
---
1 file changed, 7 insertions(+), 30 deletions(-)
Reviewed-by: Abhinav Kumar
+++
1 file changed, 5 insertions(+), 27 deletions(-)
Reviewed-by: Abhinav Kumar
changed, 17 insertions(+), 16 deletions(-)
Reviewed-by: Abhinav Kumar
deletions(-)
Reviewed-by: Abhinav Kumar
file changed, 6 insertions(+), 34 deletions(-)
Reviewed-by: Abhinav Kumar
+++-
1 file changed, 4 insertions(+), 25 deletions(-)
Reviewed-by: Abhinav Kumar
changed, 15 insertions(+), 15 deletions(-)
Reviewed-by: Abhinav Kumar
(-)
Reviewed-by: Abhinav Kumar
/mdp5/mdp5_smp.c | 19 ---
drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h | 1 -
3 files changed, 4 insertions(+), 19 deletions(-)
Reviewed-by: Abhinav Kumar
/disp/mdp5/mdp5_pipe.c | 10 +++---
drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.h | 4 ++--
3 files changed, 6 insertions(+), 14 deletions(-)
Reviewed-by: Abhinav Kumar
/msm/disp/mdp5/mdp5_mixer.c | 10 +++---
drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.h | 4 ++--
3 files changed, 6 insertions(+), 13 deletions(-)
Reviewed-by: Abhinav Kumar
-
drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h | 1 -
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 2 --
3 files changed, 4 insertions(+), 20 deletions(-)
Reviewed-by: Abhinav Kumar
On 7/7/2023 6:03 PM, Dmitry Baryshkov wrote:
Use devm_kzalloc to create CTL manager data structure. This allows us
to remove corresponding kfree and drop mdp5_ctlm_destroy() function.
Signed-off-by: Dmitry Baryshkov
---
Reviewed-by: Abhinav Kumar
+---
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h | 1 -
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 2 --
3 files changed, 5 insertions(+), 22 deletions(-)
Reviewed-by: Abhinav Kumar
On 11/30/2023 11:36 PM, Dmitry Baryshkov wrote:
On Fri, 1 Dec 2023 at 03:31, Jessica Zhang wrote:
Set the input_sel bit for encoders as it was missed in the initial
implementation.
Reported-by: Rob Clark
Fixes: 91143873a05d ("drm/msm/dpu: Add MISR register support for interface")
Closes:
On 12/1/2023 8:22 AM, Bjorn Andersson wrote:
On Fri, Dec 01, 2023 at 10:34:50AM +0200, Dmitry Baryshkov wrote:
On Fri, 1 Dec 2023 at 05:47, Bjorn Andersson wrote:
On Thu, Nov 30, 2023 at 05:40:55PM -0800, Paloma Arellano wrote:
[..]
@@ -2386,6 +2390,7 @@ struct drm_encoder
On 11/30/2023 11:45 PM, Dmitry Baryshkov wrote:
On Fri, 1 Dec 2023 at 03:41, Paloma Arellano wrote:
When the irq callback returns a value other than zero,
modify vblank_refcount by performing the inverse
operation of its corresponding if-else condition.
I think it might be better to
On 11/30/2023 11:20 PM, Dmitry Baryshkov wrote:
On Fri, 1 Dec 2023 at 02:41, Abhinav Kumar wrote:
On 8/30/2023 5:11 PM, Dmitry Baryshkov wrote:
On Thu, 31 Aug 2023 at 01:50, Abhinav Kumar wrote:
Add an API dpu_encoder_helper_phys_setup_cdm() which can be used by
the writeback encoder
On 11/30/2023 11:05 PM, Dmitry Baryshkov wrote:
On Fri, 1 Dec 2023 at 01:36, Abhinav Kumar wrote:
On 8/30/2023 5:00 PM, Dmitry Baryshkov wrote:
On Thu, 31 Aug 2023 at 01:50, Abhinav Kumar wrote:
CDM block comes with its own set of registers and operations
which can be done. In-line
On 8/30/2023 5:24 PM, Dmitry Baryshkov wrote:
On Thu, 31 Aug 2023 at 01:50, Abhinav Kumar wrote:
On chipsets where CDM block is not available OR where support has
not been added yet do not allow YUV formats for writeback block.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp
On 8/30/2023 5:23 PM, Dmitry Baryshkov wrote:
On Thu, 31 Aug 2023 at 01:50, Abhinav Kumar wrote:
Reserve CDM blocks for writeback if the format of the output fb
is YUV. At the moment, the reservation is done only for writeback
but can easily be extended by relaxing the checks once other
On 8/30/2023 5:11 PM, Dmitry Baryshkov wrote:
On Thu, 31 Aug 2023 at 01:50, Abhinav Kumar wrote:
Add an API dpu_encoder_helper_phys_setup_cdm() which can be used by
the writeback encoder to setup the CDM block.
Currently, this is defined and used within the writeback's physical
encoder
On 8/30/2023 5:14 PM, Dmitry Baryshkov wrote:
On Thu, 31 Aug 2023 at 01:50, Abhinav Kumar wrote:
In preparation of setting up CDM block, add the logic to disable it
properly during encoder cleanup.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 8
On 8/30/2023 5:12 PM, Dmitry Baryshkov wrote:
On Thu, 31 Aug 2023 at 01:50, Abhinav Kumar wrote:
CDM block will need its own logic to program the flush and active
bits in the dpu_hw_ctl layer.
Make necessary changes in dpu_hw_ctl to support CDM programming.
Signed-off-by: Abhinav Kumar
On 8/30/2023 5:06 PM, Dmitry Baryshkov wrote:
On Thu, 31 Aug 2023 at 01:50, Abhinav Kumar wrote:
Even though there is usually only one CDM block, it can be
used by either HDMI, DisplayPort OR Writeback interfaces.
Hence its allocation needs to be tracked properly by the
resource manager
On 8/30/2023 4:48 PM, Dmitry Baryshkov wrote:
On Thu, 31 Aug 2023 at 01:50, Abhinav Kumar wrote:
Add the RM APIs necessary to initialize and allocate CDM
blocks by the rest of the DPU pipeline.
... to be used by the rest?
Yes, thanks.
Signed-off-by: Abhinav Kumar
---
drivers
On 8/30/2023 5:00 PM, Dmitry Baryshkov wrote:
On Thu, 31 Aug 2023 at 01:50, Abhinav Kumar wrote:
CDM block comes with its own set of registers and operations
which can be done. In-line with other hardware sub-blocks, this
change adds the dpu_hw_cdm abstraction for the CDM block.
Signed
in dpu_encoder_virt
Reported-by: kernel test robot
Closes:
https://lore.kernel.org/oe-kbuild-all/202312010225.2ojwlkma-...@intel.com/
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Paloma Arellano
Reviewed-by: Abhinav Kumar
On 8/30/2023 3:57 PM, Dmitry Baryshkov wrote:
On Thu, 31 Aug 2023 at 01:49, Abhinav Kumar wrote:
Add CDM blocks to the sc7280 dpu_hw_catalog to support
YUV format output from writeback block.
Signed-off-by: Abhinav Kumar
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 9
: Fix reg values for a690")
Signed-off-by: Rob Clark
---
Reviewed-by: Abhinav Kumar
On 11/27/2023 3:17 PM, Dmitry Baryshkov wrote:
On Tue, 28 Nov 2023 at 00:00, Abhinav Kumar wrote:
On 11/27/2023 1:54 PM, Dmitry Baryshkov wrote:
Flush queued events when disabling the crtc. This avoids timeouts when
we come back and wait for dependencies (like the previous frame's
On 11/27/2023 1:54 PM, Dmitry Baryshkov wrote:
Flush queued events when disabling the crtc. This avoids timeouts when
we come back and wait for dependencies (like the previous frame's
flip_done).
Fixes: c8afe684c95c ("drm/msm: basic KMS driver for snapdragon")
Signed-off-by: Dmitry Baryshkov
On 11/21/2023 4:27 PM, Rob Clark wrote:
On Tue, Nov 21, 2023 at 4:41 PM Abhinav Kumar wrote:
On 10/24/2023 12:01 PM, Abhinav Kumar wrote:
On 10/23/2023 4:03 PM, Dmitry Baryshkov wrote:
On Tue, 24 Oct 2023 at 01:36, Rob Clark wrote:
On Mon, Oct 23, 2023 at 3:30 PM Dmitry Baryshkov
On 10/24/2023 12:01 PM, Abhinav Kumar wrote:
On 10/23/2023 4:03 PM, Dmitry Baryshkov wrote:
On Tue, 24 Oct 2023 at 01:36, Rob Clark wrote:
On Mon, Oct 23, 2023 at 3:30 PM Dmitry Baryshkov
wrote:
On Tue, 24 Oct 2023 at 01:12, Rob Clark wrote:
From: Rob Clark
Seems like we need
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