callback to power up the PHY
on init and leave only what is necessary for mode changes in the related
function. This is enough to fix CEC operation when HDMI display is not
enabled.
Fixes: 3f68be7d8e96 ("drm/meson: Add support for HDMI encoder and DW-HDMI
bridge + PHY")
Signed-off-by: Jer
. This is done by restoring init values on PHY init and
disable.
Fixes: 3b7c1237a72a ("drm/meson: Add G12A support for the DW-HDMI Glue")
Signed-off-by: Jerome Brunet
---
drivers/gpu/drm/meson/meson_dw_hdmi.c | 43 ---
1 file changed, 26 insertions(+), 17 deletions(-)
the problem.
Jerome Brunet (2):
drm/meson: dw-hdmi: power up phy on device init
drm/meson: dw-hdmi: add bandgap setting for g12
drivers/gpu/drm/meson/meson_dw_hdmi.c | 70 ---
1 file changed, 31 insertions(+), 39 deletions(-)
--
2.43.0
Applied to clk-meson (v6.10/drivers), thanks!
[2/7] clk: meson: add vclk driver
https://github.com/BayLibre/clk-meson/commit/bb5aa08572b5
[3/7] clk: meson: g12a: make VCLK2 and ENCL clock path configurable by CCF
https://github.com/BayLibre/clk-meson/commit/b70cb1a21a54
Best regards,
On Thu 04 Apr 2024 at 18:59, Neil Armstrong wrote:
> On 04/04/2024 10:13, Jerome Brunet wrote:
>> On Wed 03 Apr 2024 at 09:46, Neil Armstrong
>> wrote:
>>
>>> The VCLK and VCLK_DIV clocks have supplementary bits.
>>>
>>> The VCLK gate has a &qu
On Wed 03 Apr 2024 at 09:46, Neil Armstrong wrote:
> The VCLK and VCLK_DIV clocks have supplementary bits.
>
> The VCLK gate has a "SOFT RESET" bit to toggle after the whole
> VCLK sub-tree rate has been set, this is implemented in
> the gate enable callback.
>
> The VCLK_DIV clocks as enable
On Mon 25 Mar 2024 at 12:09, Neil Armstrong wrote:
> In order to setup the DSI clock, let's make the unused VCLK2 clock path
> configuration via CCF.
>
> The nocache option is removed from following clocks:
> - vclk2_sel
> - vclk2_input
> - vclk2_div
> - vclk2
> - vclk_div1
> - vclk2_div2_en
>
On Mon 25 Mar 2024 at 12:09, Neil Armstrong wrote:
> The VCLK and VCLK_DIV clocks have supplementary bits.
>
> The VCLK gate has a "SOFT RESET" bit to toggle after the whole
> VCLK sub-tree rate has been set, this is implemented in
> the gate enable callback.
>
> The VCLK_DIV clocks as enable
On Wed 13 Dec 2023 at 17:44, Neil Armstrong wrote:
> Hi Maxime,
>
> Le 13/12/2023 à 09:36, Maxime Ripard a écrit :
>> Hi,
>> On Wed, Dec 13, 2023 at 08:43:00AM +0100, Uwe Kleine-König wrote:
>>> On Wed, Dec 13, 2023 at 08:16:04AM +0100, Maxime Ripard wrote:
On Tue, Dec 12, 2023 at
On Wed 13 Dec 2023 at 08:16, Maxime Ripard wrote:
> [[PGP Signed Part:Undecided]]
> Hi,
>
> On Tue, Dec 12, 2023 at 06:26:37PM +0100, Uwe Kleine-König wrote:
>> Hello,
>>
>> clk_rate_exclusive_get() returns zero unconditionally. Most users "know"
>> that and don't check the return value. This
On Mon 27 Nov 2023 at 17:14, Neil Armstrong wrote:
> On 24/11/2023 15:41, Jerome Brunet wrote:
>> On Fri 24 Nov 2023 at 09:41, Neil Armstrong
>> wrote:
>>
>>> The VCLK and VCLK_DIV clocks have supplementary bits.
>>>
>>> The VCLK has a "S
>>
>>>
>>> I suspect mipi_dsi_pxclk_div was added to achieve fractional vclk/bitclk
>>> ratios,
>>> since it doesn't exist on AXG. Not sure we would ever need it... and none
>>> of the other upstream DSI drivers supports such setups.
>>>
>>> The main reasons I set only mipi_dsi_pxclk in DT is
Applied to clk-meson (v6.8/drivers), thanks!
[01/12] dt-bindings: clk: g12a-clkc: add CTS_ENCL clock ids
https://github.com/BayLibre/clk-meson/commit/bd5ef3f21d17
[06/12] clk: meson: g12a: add CTS_ENCL & CTS_ENCL_SEL clocks
https://github.com/BayLibre/clk-meson/commit/5de4e8353e32
On Fri 24 Nov 2023 at 16:15, Neil Armstrong wrote:
> On 24/11/2023 15:12, Jerome Brunet wrote:
>> On Fri 24 Nov 2023 at 09:41, Neil Armstrong
>> wrote:
>>
>>> In order to setup the DSI clock, let's make the unused VCLK2 clock path
>>> configurat
On Fri 24 Nov 2023 at 09:41, Neil Armstrong wrote:
> The VCLK and VCLK_DIV clocks have supplementary bits.
>
> The VCLK has a "SOFT RESET" bit to toggle after the whole
> VCLK sub-tree rate has been set, this is implemented in
> the gate enable callback.
>
> The VCLK_DIV clocks as enable and
On Fri 24 Nov 2023 at 09:41, Neil Armstrong wrote:
> In order to setup the DSI clock, let's make the unused VCLK2 clock path
> configuration via CCF.
>
> The nocache option is removed from following clocks:
> - vclk2_sel
> - vclk2_input
> - vclk2_div
> - vclk2
> - vclk_div1
> - vclk2_div2_en
>
On Thu 03 Aug 2023 at 14:03, Neil Armstrong wrote:
> In order to setup the DSI clock, let's make the unused VCLK2 clock path
> configuration via CCF.
>
> The nocache option is removed from following clocks:
> - vclk2_sel
> - vclk2_input
> - vclk2_div
> - vclk2
> - vclk_div1
> - vclk2_div2_en
>
On Thu 03 Aug 2023 at 14:03, Neil Armstrong wrote:
> Add new CTS_ENCL & CTS_ENCL_SEL clocks for the G12A compatible
> SoCs, they are used to feed the VPU LCD Pixel encoder used for
> DSI display purposes.
>
> Signed-off-by: Neil Armstrong
> ---
> drivers/clk/meson/g12a.c | 40
On Thu 03 Aug 2023 at 14:03, Neil Armstrong wrote:
> The VCLK and VCLK_DIV clocks have supplementary bits.
>
> The VCLK has a "SOFT RESET" bit to toggle after the whole
> VCLK sub-tree rate has been set, this is implemented in
> the gate enable callback.
>
> The VCLK_DIV clocks as enable and
On Tue 30 May 2023 at 17:56, Neil Armstrong wrote:
> On 30/05/2023 10:08, Jerome Brunet wrote:
>> On Tue 30 May 2023 at 09:38, Neil Armstrong
>> wrote:
>>
>>> Exposing should not be done in a single commit anymore due to
>>> dt-bindings enforced rules.
On Tue 30 May 2023 at 09:38, Neil Armstrong wrote:
> In order to setup the DSI clock, let's make the unused VCLK2 clock path
> configuration via CCF.
>
> The nocache option is removed from following clocks:
> - vclk2_sel
> - vclk2_input
> - vclk2_div
> - vclk2
> - vclk_div1
> - vclk2_div2_en
>
On Tue 30 May 2023 at 09:38, Neil Armstrong wrote:
> Exposing should not be done in a single commit anymore due to
> dt-bindings enforced rules.
>
> Prepend PRIV to the private CLK IDs so we can add new clock to
> the bindings header and in a separate commit remove such private
> define and
On Tue 16 May 2023 at 11:00, Neil Armstrong wrote:
> On 16/05/2023 10:44, Arnd Bergmann wrote:
>> On Mon, May 15, 2023, at 18:22, neil.armstr...@linaro.org wrote:
>>> On 15/05/2023 18:15, Krzysztof Kozlowski wrote:
On 15/05/2023 18:13, Krzysztof Kozlowski wrote:
Also one more
On Fri 20 Nov 2020 at 10:42, Marc Zyngier wrote:
> The HDMI driver request clocks early, but never disable them, leaving
> the clocks on even when the driver is removed.
>
> Fix it by slightly refactoring the clock code, and register a devm
> action that will eventually disable/unprepare the
On Thu 19 Nov 2020 at 19:04, Guillaume Tucker
wrote:
> Hi Marc,
>
> On 19/11/2020 11:58, Marc Zyngier wrote:
>> On 2020-11-19 10:26, Neil Armstrong wrote:
>>> On 19/11/2020 11:20, Marc Zyngier wrote:
On 2020-11-19 08:50, Guillaume Tucker wrote:
> Please see the automated bisection
On Wed 18 Sep 2019 at 10:24, Cheng-Yi Chiang wrote:
> The problem of using auto ID is that the device name will be like
> hdmi-audio-codec..auto.
>
> The number might be changed when there are other platform devices being
> created before hdmi-audio-codec device.
> Use a fixed name so machine
setup the channel allocation provided by the generic hdmi-codec driver
Reviewed-by: Jonas Karlman
Signed-off-by: Jerome Brunet
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
b
When changing the audio hw params, reset the audio fifo to make sure
any old remaining data is flushed.
The databook mentions that such reset should be followed by a reset of
the i2s block to make sure the samples stay aligned
Reviewed-by: Jonas Karlman
Signed-off-by: Jerome Brunet
On Mon 12 Aug 2019 at 14:19, Neil Armstrong wrote:
> Hi,
>
> On 12/08/2019 14:07, Jerome Brunet wrote:
>> The purpose of this patchset is to improve the support of the i2s
>> interface of the synopsys hdmi controller.
>>
>> Once applied, the interface sho
://lkml.kernel.org/r/20190805134102.24173-1-jbru...@baylibre.com
Jerome Brunet (8):
drm/bridge: dw-hdmi-i2s: support more i2s format
drm/bridge: dw-hdmi: move audio channel setup out of ahb
drm/bridge: dw-hdmi: set channel count in the infoframes
drm/bridge: dw-hdmi-i2s: enable lpcm multi
Provide the eld to the generic hdmi-codec driver.
This will let the driver enforce the maximum channel number and set the
channel allocation depending on the hdmi sink.
Cc: Jonas Karlman
Signed-off-by: Jerome Brunet
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi-audio.h | 1 +
drivers/gpu
The dw-hdmi-i2s supports more formats than just regular i2s.
Add support for left justified, right justified and dsp modes
A and B.
Reviewed-by: Jonas Karlman
Signed-off-by: Jerome Brunet
---
.../drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 26 ---
drivers/gpu/drm/bridge
Set the number of channel in the infoframes
Reviewed-by: Jonas Karlman
Signed-off-by: Jerome Brunet
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index
Provide the eld to the generic hdmi-codec driver.
This will let the driver enforce the maximum channel number and set the
channel allocation depending on the hdmi sink.
Cc: Jonas Karlman
Signed-off-by: Jerome Brunet
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi-audio.h | 1 +
drivers/gpu
Enable the i2s lanes depending on the number of channel in the stream
Reviewed-by: Jonas Karlman
Signed-off-by: Jerome Brunet
---
.../gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 15 ++-
drivers/gpu/drm/bridge/synopsys/dw-hdmi.h | 6 +-
2 files changed, 19
Part of the channel count setup done in dw-hdmi ahb should
actually be done whatever the interface providing the data.
Reviewed-by: Jonas Karlman
Let's move it to dw-hdmi driver instead.
Signed-off-by: Jerome Brunet
---
.../drm/bridge/synopsys/dw-hdmi-ahb-audio.c | 20 +++-
drivers
Properly setup the channel count and layout in dw-hdmi i2s driver so
we are not limited to 2 channels.
Also correct the maximum channel reported by the DAI from 6 to 8 ch
Reviewed-by: Jonas Karlman
Signed-off-by: Jerome Brunet
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 3 ++-
1
On Wed 07 Aug 2019 at 14:57, Jonas Karlman wrote:
> On 2019-08-05 15:41, Jerome Brunet wrote:
>> Provide the eld to the generic hdmi-codec driver.
>> This will let the driver enforce the maximum channel number and set the
>> channel allocation depending on the hdmi sink.
&g
Properly setup the channel count and layout in dw-hdmi i2s driver so
we are not limited to 2 channels.
Also correct the maximum channel reported by the DAI from 6 to 8 ch
Cc: Jonas Karlman
Signed-off-by: Jerome Brunet
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 3 ++-
1 file
, there is a
runtime dependency for patch 8 on this ASoC series [1].
[0]:
https://github.com/Kwiboo/linux-rockchip/commits/rockchip-5.2-for-libreelec-v5.2.3
[1]: https://lkml.kernel.org/r/20190725165949.29699-1-jbru...@baylibre.com
Jerome Brunet (8):
drm/bridge: dw-hdmi-i2s: support more i2s
When changing the audio hw params, reset the audio fifo to make sure
any old remaining data is flushed.
The databook mentions that such reset should be followed by a reset of
the i2s block to make sure the samples stay aligned
Cc: Jonas Karlman
Signed-off-by: Jerome Brunet
---
drivers/gpu/drm
Part of the channel count setup done in dw-hdmi ahb should
actually be done whatever the interface providing the data.
Let's move it to dw-hdmi driver instead.
Signed-off-by: Jerome Brunet
---
.../drm/bridge/synopsys/dw-hdmi-ahb-audio.c | 20 +++-
drivers/gpu/drm/bridge/synopsys/dw
setup the channel allocation provided by the generic hdmi-codec driver
Cc: Jonas Karlman
Signed-off-by: Jerome Brunet
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
b/drivers/gpu
Set the number of channel in the infoframes
Cc: Jonas Karlman
Signed-off-by: Jerome Brunet
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index
Provide the eld to the generic hdmi-codec driver.
This will let the driver enforce the maximum channel number and set the
channel allocation depending on the hdmi sink.
Cc: Jonas Karlman
Signed-off-by: Jerome Brunet
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi-audio.h | 1 +
drivers/gpu
Enable the i2s lanes depending on the number of channel in the stream
Cc: Jonas Karlman
Signed-off-by: Jerome Brunet
---
.../gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 15 ++-
drivers/gpu/drm/bridge/synopsys/dw-hdmi.h | 6 +-
2 files changed, 19 insertions(+), 2
The dw-hdmi-i2s supports more formats than just regular i2s.
Add support for left justified, right justified and dsp modes
A and B.
Signed-off-by: Jerome Brunet
---
.../drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 26 ---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.h | 6
The dw-hdmi-i2s supports more formats than just regular i2s.
Add support for left justified, right justified and dsp modes
A and B.
Signed-off-by: Jerome Brunet
---
Tested on the Amlogic arm64 meson-g12a-sei510 with i2s, left_j, dsp_a
and dsp_b. right_j is not supported by this platform
Imply the i2s part of the Synopsys HDMI driver for Amlogic SoCs.
This will enable the i2s part by default when meson hdmi driver
is enable but let platforms not supported by the audio subsystem
disable it if necessary.
Signed-off-by: Jerome Brunet
---
drivers/gpu/drm/meson/Kconfig | 1 +
1 file
On Mon, 2019-03-25 at 15:18 +0100, Neil Armstrong wrote:
> This patch adds support for the new OSD+VD Plane blending module
> in the CRTC code by adding the G12A code to manage the blending
> module and setting the right OSD1 & VD1 plane registers.
>
> Signed-off-by: Neil Armstrong
> ---
>
On Mon, 2019-03-25 at 15:18 +0100, Neil Armstrong wrote:
> Amlogic G12A SoC needs a different VIU setup code,
> handle it.
>
> Signed-off-by: Neil Armstrong
> ---
> drivers/gpu/drm/meson/meson_viu.c | 72 ---
> 1 file changed, 67 insertions(+), 5 deletions(-)
>
>
| 11 +-
> drivers/gpu/drm/meson/meson_venc_cvbs.c | 25 ++-
> drivers/gpu/drm/meson/meson_viu.c | 72 ++++++-
> drivers/gpu/drm/meson/meson_vpp.c | 51 +++--
> 13 files changed, 880 insertions(+), 143 deletions(-)
>
on the u200 and sei510
Tested-by: Jerome Brunet
On Mon, 2019-03-25 at 15:18 +0100, Neil Armstrong wrote:
> The Meson G12A SoCs uses the exact same CVBS encoder except a simple
> CVBS DAC register offset and settings delta.
>
> Signed-off-by: Neil Armstrong
> ---
> drivers/gpu/drm/meson/meson_venc.c | 11 +--
>
On Mon, 2019-03-25 at 15:18 +0100, Neil Armstrong wrote:
> Amlogic G12A SoC supports the same set of Video Planes, but now
> are handled by the new OSD plane blender module.
>
> This patch uses the same VD1 plane for G12A, using the exact same scaler
> and VD11 setup registers, except using the
On Tue, 2019-04-09 at 10:43 +0200, Jerome Brunet wrote:
> On Mon, 2019-03-25 at 15:18 +0100, Neil Armstrong wrote:
> > The Meson G12A SoCs uses the exact same CVBS encoder except a simple
> > CVBS DAC register offset and settings delta.
> >
> > Signed-off-by: Neil Armst
On Mon, 2019-03-25 at 15:18 +0100, Neil Armstrong wrote:
> While switching to the Common Clock Framework is still Work In Progress,
> this patch adds the corresponding G12A HDMI PLL setup to be on-par
> with the other SoCs support.
>
> The G12A has only a single tweak about the high frequency
On Wed, 2018-08-01 at 20:51 +0200, Maxime Jourdan wrote:
> This removes the meson_canvas files within the meson/drm layer
> and makes use of the new canvas module that is referenced in the dts.
>
> Canvases can be used by different IPs and modules, and it is as such
> preferable to rely on a
On Thu, 2018-08-02 at 14:34 +0200, Maxime Jourdan wrote:
> Hi Jerome,
>
> 2018-08-02 10:39 GMT+02:00 Jerome Brunet :
> > I looks like the consumer of your 'canvas' devices must know how the canvas
> > device is organized internally. Maybe something better can be done ?
> &
display driver needs a detailed control over the clock setup, maybe we
could solve the problem by exporting the intermediate clock elements in CCF
(such as muxes, ODs, etc...) and let the display driver claim them all ?
Anyway, the situation is improving so:
Acked-by: Jerome Brunet
>
.
>
> Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
Looks good to me
Acked-by: Jerome Brunet <jbru...@baylibre.com>
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/gpu/drm/meson/meson_registers.h | 4
> 5 files changed, 34 insertions(+)
>
No dependencies on the bootloader anymore, this is great ! Thanks
Series tested on libretech-cc s905x
Tested-by: Jerome Brunet <jbru...@baylibre.com>
Reviewed-by: Jerome Brunet <jbru
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