On 4/23/24 09:33, Tomi Valkeinen wrote:
> Hi Sean,
>
> On 22/04/2024 21:45, Sean Anderson wrote:
>> This series cleans up the zyqnmp_dp IRQ and locking situation. Once
>> that's done, it adds debugfs support. The intent is to enable compliance
>> testing or to help debug signal-integrity issues.
On 22-04-2024 12:27, Aravind Iddamsetty wrote:
PCI subsystem provides callbacks to inform the driver about a request to
do function level reset by user, initiated by writing to sysfs entry
/sys/bus/pci/devices/.../reset. This will allow the driver to handle FLR
without the need to do unbind
On 4/23/24 11:30, Tomi Valkeinen wrote:
> On 23/04/2024 17:59, Sean Anderson wrote:
>> On 4/23/24 09:33, Tomi Valkeinen wrote:
>>> Hi Sean,
>>>
>>> On 22/04/2024 21:45, Sean Anderson wrote:
This series cleans up the zyqnmp_dp IRQ and locking situation. Once
that's done, it adds debugfs
Hi, sorry for the long delay
On Mon, Feb 26, 2024 at 10:10 AM Krzysztof Kozlowski
wrote:
>
> On 21/02/2024 17:02, Paweł Anikiel wrote:
> > The Chameleon v3 uses the framebuffer IP core to take the video signal
> > from different sources and directly write frames into memory.
> >
> >
Hi,
On Mon, Apr 22, 2024 at 6:28 PM Xuxin Xiong
wrote:
>
> Yes, I read the edid from the panels, one is CSO and the other is CSW.
> The details are as follows, please help check. Thank you!
>
>
> 1. MNC207QS1-1
> edid-decode (hex):
> 00 ff ff ff ff ff ff 00 0e 6f 00 12 e7 00 00 00
> 1e 21 01 04
On 09/04/2024 17:55, Krzysztof Kozlowski wrote:
+
+additionalProperties: false
+
+examples:
+ - |
+codec {
+mediatek,micbias0-microvolt = <190>;
+mediatek,micbias1-microvolt = <170>;
+mediatek,vaud28-supply = <_vaud28_reg>;
Sorry, this does not work.
Enable this message for verbose debugging only as it is otherwise
printed after every AUX message, quickly filling the log buffer.
Signed-off-by: Sean Anderson
Reviewed-by: Laurent Pinchart
Reviewed-by: Tomi Valkeinen
---
(no changes since v1)
drivers/gpu/drm/xlnx/zynqmp_dp.c | 2 +-
1 file
The blend, avbuf, and audio members of zynqmp_disp are anonymous structs
with only one member each. This is rather pointless, so move the members
up a level.
Signed-off-by: Sean Anderson
Reviewed-by: Tomi Valkeinen
---
(no changes since v3)
Changes in v3:
- New
The feedback we get from the DPRX is per-lane. Make changes using this
information, instead of picking the maximum values from all lanes. This
results in more-consistent training on marginal links.
Signed-off-by: Sean Anderson
Reviewed-by: Tomi Valkeinen
---
(no changes since v1)
We always call scheduled_delayed_work with no delay, so just use a
non-delayed work_struct instead.
Signed-off-by: Sean Anderson
Reviewed-by: Tomi Valkeinen
---
(no changes since v3)
Changes in v3:
- New
drivers/gpu/drm/xlnx/zynqmp_dp.c | 13 ++---
1 file changed, 6 insertions(+), 7
Add some locking to prevent the IRQ/workers/bridge API calls from stepping
on each other's toes. This lock protects:
- Non-atomic registers configuring the link. That is, everything but the
IRQ registers (since these are accessed in an atomic fashion), and the DP
AUX registers (since these
In preparation for supporting compliance testing, split off several
helper functions. No functional change intended.
Signed-off-by: Sean Anderson
Reviewed-by: Laurent Pinchart
Reviewed-by: Tomi Valkeinen
---
(no changes since v1)
drivers/gpu/drm/xlnx/zynqmp_dp.c | 49
Fix a few errors in the kerneldoc. Mostly this addresses missing/renamed
members.
Signed-off-by: Sean Anderson
Reviewed-by: Tomi Valkeinen
---
(no changes since v3)
Changes in v3:
- Split off documentation for base pointers to previous commit
Changes in v2:
- New
Retraining the link can take a while, and might involve waiting for
DPCD reads/writes to complete. In preparation for unthreading the IRQ
handler, move this into its own work function.
Signed-off-by: Sean Anderson
---
(no changes since v2)
Changes in v2:
- Document hpd_irq_work
- Split this
Instead of polling the status register for the AUX status, just enable
the IRQs and signal a completion.
Signed-off-by: Sean Anderson
---
(no changes since v3)
Changes in v3:
- New
drivers/gpu/drm/xlnx/zynqmp_dp.c | 35 +++-
1 file changed, 25 insertions(+), 10
Now that all of the sleeping work is done outside of the IRQ, we can
convert it to a hard IRQ.
Signed-off-by: Sean Anderson
---
(no changes since v3)
Changes in v3:
- New
drivers/gpu/drm/xlnx/zynqmp_dp.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git
This series cleans up the zyqnmp_dp IRQ and locking situation. Once
that's done, it adds debugfs support. The intent is to enable compliance
testing or to help debug signal-integrity issues.
Last time I discussed converting the HPD work(s) to a threaded IRQ. I
did not end up doing that for this
Sort the members of struct zynqmp_dp to reduce padding necessary for
alignment.
Signed-off-by: Sean Anderson
---
(no changes since v2)
Changes in v2:
- New
drivers/gpu/drm/xlnx/zynqmp_dp.c | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git
Add a debugfs interface for exercising the various test modes supported
by the DisplayPort controller. This allows performing compliance
testing, or performing signal integrity measurements on a failing link.
At the moment, we do not support sink-driven link quality testing,
although such support
Add a non-locking version of zynqmp_dp_bridge_detect and use it in
zynqmp_dp_hpd_work_func so we can take the lock explicitly. This will
make it easier to check for hpd_ignore when we add debugfs support.
Signed-off-by: Sean Anderson
---
(no changes since v3)
Changes in v3:
- New
On 4/22/24 8:35 AM, Jose Fernandez wrote:
When slice_height is 0, the division by slice_height in the calculation
of the number of slices will cause a division by zero driver crash. This
leaves the kernel in a state that requires a reboot. This patch adds a
check to avoid the division by
Update header inclusions to follow IWYU (Include What You Use)
principle.
Signed-off-by: Andy Shevchenko
---
drivers/staging/fbtft/fb_seps525.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/staging/fbtft/fb_seps525.c
b/drivers/staging/fbtft/fb_seps525.c
On 23/04/2024 17:59, Sean Anderson wrote:
On 4/23/24 09:33, Tomi Valkeinen wrote:
Hi Sean,
On 22/04/2024 21:45, Sean Anderson wrote:
This series cleans up the zyqnmp_dp IRQ and locking situation. Once
that's done, it adds debugfs support. The intent is to enable compliance
testing or to help
On Sun, 25 Feb 2024 08:19:29 +0200, Tony Lindgren wrote:
> Here are v5 patches to improve tc358775 driver and add support for
> tc358765.
>
> Regards,
>
> Tony
>
> [...]
Thanks for the really nice series, sorry about the delay in applying it.
Applied, thanks!
[01/10] dt-bindings: display:
Hi Liviu,
Thanks for your review. Also want to apologise for replying so late.
Today I'll be sending a v2 of this patch series after having applied
all your suggestions.
On 28.03.2024 15:49, Liviu Dudau wrote:
> Hi Adrián,
>
> Appologies for the delay in reviewing this.
>
> On Tue, Mar 05,
When the host page size was more than 4 times larger than the FW page
size, this macro evaluated to zero resulting in zero-sized arrays.
Use DIV_ROUND_UP() to ensure the correct behavior.
Reported-by: 20240228012313.5934-1-ya...@kylinos.cn
Closes:
Hi,
Thanks a for you reviewing my patch.
On 2024/4/23 21:28, Andy Shevchenko wrote:
On Tue, Apr 23, 2024 at 12:46:58AM +0800, Sui Jingfeng wrote:
Because the software node backend of the fwnode API framework lacks an
implementation for the .device_get_match_data function callback. This
makes
From: Chris Wilson
The breadcrumbs use a GT wakeref for guarding the interrupt, but are
disarmed during release of the engine wakeref. This leaves a hole where
we may attach a breadcrumb just as the engine is parking (after it has
parked its breadcrumbs), execute the irq worker with some
On Tue, 09 Apr 2024 15:25:35 +0200
Louis Chauvet wrote:
> This add the support for:
> - R1/R2/R4/R8
>
> R1 format was tested with [1] and [2].
>
> [1]:
> https://lore.kernel.org/r/20240313-new_rotation-v2-0-6230fd5ca...@bootlin.com
> [2]:
>
Hi Nirmoy,
> > > Currently intel_gt_reset() kills the GuC and then resets requested
> > > engines. This is problematic because there is a dedicated CSB FIFO
> > > which only GuC can access and if that FIFO fills up, the hardware
> > > will block on the next context switch until there is space
Hi,
On Tue, Apr 23, 2024 at 2:37 AM cong yang
wrote:
>
> > > +static int starry_init_cmd(struct hx83102 *ctx)
> > > +{
> > > + struct mipi_dsi_device *dsi = ctx->dsi;
> > > +
> > > + mipi_dsi_dcs_write_seq(dsi, HX83102_SETEXTC, 0x83, 0x10, 0x21,
> > > 0x55, 0x00);
> > > +
> > > +
Hi,
On 2024/4/23 03:51, Dmitry Baryshkov wrote:
On Tue, Apr 23, 2024 at 03:18:55AM +0800, Sui Jingfeng wrote:
Currently, the various display bridge drivers rely on OF infrastructures
to works very well, yet there are platforms and/or devices absence of 'OF'
support. Such as virtual display
Hi,
On Mon, Apr 22, 2024 at 01:08:44PM -0300, Maíra Canal wrote:
> @drm-misc maintainers, is there any chance you could backport commit
> 35f4f8c9fc97 ("drm/v3d: Don't increment `enabled_ns` twice") [1] to drm-
> misc-next?
>
> I would like to apply this series to drm-misc-next because it fixes
On 4/16/2024 4:57 PM, Marijn Suijten wrote:
As we can clearly see in a downstream kernel [1], flushing the slave INTF
is skipped /only if/ the PPSPLIT topology is active.
However, when DPU was originally submitted to mainline PPSPLIT was no
longer part of it (seems to have been ripped out
Hi,
On 3/22/24 02:01, Tomi Valkeinen wrote:
> Hi,
>
> On 08/03/2024 22:47, Sean Anderson wrote:
>> We must always register the DRM bridge, since zynqmp_dp_hpd_work_func
>> calls drm_bridge_hpd_notify, which in turn expects hpd_mutex to be
>> initialized. We do this before zynqmp_dpsub_drm_init
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: a59668a9397e7245b26e9be85d23f242ff757ae8 Add linux-next specific
files for 20240423
Error/Warning reports:
https://lore.kernel.org/oe-kbuild-all/202404231839.ohiy9lw8-...@intel.com
Error
Hi,
On Tue, Apr 23, 2024 at 11:10 AM Hsin-Yi Wang wrote:
>
> > > > > +#define _INIT_DCS_CMD(...) { \
> > > > > + .type = INIT_DCS_CMD, \
> > > > > + .len = sizeof((char[]){__VA_ARGS__}), \
> > > > > + .data = (char[]){__VA_ARGS__} }
> > > > > +
> > > > > +#define _INIT_DELAY_CMD(...)
On Tue, Apr 23, 2024 at 02:25:06PM +0530, Aravind Iddamsetty wrote:
>
> On 23/04/24 02:24, Rodrigo Vivi wrote:
> > On Mon, Apr 22, 2024 at 12:27:53PM +0530, Aravind Iddamsetty wrote:
> >> In scenarios where drm_dev_put is directly called by driver we want to
> >> release devm_drm_dev_init_release
Hi Andreas,
On Sat, Mar 09, 2024 at 07:15:21PM +0100, Sam Ravnborg via B4 Relay wrote:
> This is the second attempt to sunset sun4m and sun4d.
> See [1] for the inital attempt.
>
> The sun4m and sun4d parts of the kernel have seen no real interest
> for several years now. Last time a few people
Syzbot has found the race condition where 'fput()' is in progress
when 'dma_buf_poll()' makes an attempt to hold the 'struct file'
with zero 'f_count'. So use explicit 'atomic_long_inc_not_zero()'
to detect such a case and cancel an undergoing poll activity with
EPOLLERR.
Reported-by:
On 2/22/24 7:19 AM, David Tadokoro wrote:
In the header file dc/dcn301/dcn301_dccg.h, the function dccg301_create
is declared twice, so remove duplication.
Signed-off-by: David Tadokoro
---
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.h | 6 --
1 file changed, 6 deletions(-)
Hi Jason,
Sorry for a late reply. I have been working on a v2 of this series:
https://patchwork.freedesktop.org/series/132229/. This version addressed some
of your concerns, such as removing the global character device, removing svm
process concept (need further clean up per Matt's feedback).
On Thu, Apr 18, 2024 at 7:11 AM Dmitry Baryshkov
wrote:
>
> On Thu, Apr 18, 2024 at 09:11:37PM +0800, Hsin-Yi Wang wrote:
> > On Thu, Apr 18, 2024 at 7:46 PM Dmitry Baryshkov
> > wrote:
> > >
> > > On Thu, Apr 18, 2024 at 04:15:48PM +0800, lvzhaoxiong wrote:
> > > > The kingdisplay panel is
On 2/13/24 3:43 PM, Joao Paulo Pereira da Silva wrote:
From: jppaulo
Clean some wrong indenting that throw errors in checkpatch.
Signed-off-by: Joao Paulo Pereira da Silva
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff
Commit 7af03e688792 ("drm/probe-helper: warn about negative
.get_modes()") clarified, that .get_modes callback must not return
negative values on failure, so fix sub-drivers to return 0 in case of
errors. This fixes strange Exynos DRM initialization failure on boot
(timeout waiting for VSYNC)
On 23.04.2024 22:44, Marek Szyprowski wrote:
> Commit 7af03e688792 ("drm/probe-helper: warn about negative
> .get_modes()") clarified, that .get_modes callback must not return
> negative values on failure, so fix sub-drivers to return 0 in case of
> errors. This fixes strange Exynos DRM
On Tue, Apr 23, 2024 at 01:41:59PM -0700, Doug Anderson wrote:
> Hi,
>
> On Tue, Apr 23, 2024 at 11:10 AM Hsin-Yi Wang wrote:
> >
> > > > > > +#define _INIT_DCS_CMD(...) { \
> > > > > > + .type = INIT_DCS_CMD, \
> > > > > > + .len = sizeof((char[]){__VA_ARGS__}), \
> > > > > > +
6.6-stable review patch. If anyone has any objections, please let me know.
--
From: Zack Rusin
commit d4c972bff3129a9dd4c22a3999fd8eba1a81531a upstream.
The table of primary plane formats wasn't sorted at all, leading to
applications picking our least desirable formats by
6.6-stable review patch. If anyone has any objections, please let me know.
--
From: Zack Rusin
commit a60ccade88f926e871a57176e86a34bbf0db0098 upstream.
The conditional was supposed to prevent enabling of a crtc state
without a set primary plane. Accidently it also prevented
6.1-stable review patch. If anyone has any objections, please let me know.
--
From: Zack Rusin
[ Upstream commit 4c08f01934ab67d1d283d5cbaa52b923abcfe4cd ]
Enable DMA mappings in vmwgfx after TTM has been fixed in commit
3bf3710e3718 ("drm/ttm: Add a generic TTM memcpy move
On 4/16/24 2:02 PM, Randy Dunlap wrote:
>
>
> On 4/16/24 2:00 PM, Marijn Suijten wrote:
>> Hi Randy,
>>
>> [..]
>>
>>> Do you see differences in the generated html for these changes?
>>
>> I have not yet generated the HTML locally to test this patch, but will
>> surely do
>> if that's a
Hello,
An Aspeed VGA monitor, in my case AST 2400, after a suspend/resume
cycle suffers with a "No Signal" state. This is also true of a
IPMI/BMC remote console. To restore the "Signal" state requires
a reboot or the following workaround.
To restore the "Signal" state without rebooting issue
)
drm_panel_init(>panel, dev, _fhd_r63452_panel_funcs,
DRM_MODE_CONNECTOR_DSI);
+ ctx->panel.prepare_prev_first = true;
ret = drm_panel_of_backlight(>panel);
if (ret)
---
base-commit: a59668a9397e7245b26e9be85d23f242ff757ae8
change-id: 20240423-jdi-fix-986
Hello,
I would confirm that this patch works for my machine:
01:00.0 VGA compatible controller: NVIDIA Corporation AD107M [GeForce RTX
4050 Max-Q / Mobile] (rev a1)
01:00.1 Audio device: NVIDIA Corporation Device 22be (rev a1)
System Information
Manufacturer: LENOVO
Product
On Mon, Apr 22, 2024 at 12:27:56PM +0530, Aravind Iddamsetty wrote:
> PCI subsystem provides callbacks to inform the driver about a request to
> do function level reset by user, initiated by writing to sysfs entry
> /sys/bus/pci/devices/.../reset. This will allow the driver to handle FLR
> without
Hi,
Thanks for review.
Rob Herring 于2024年4月22日周一 23:16写道：
>
> On Mon, Apr 22, 2024 at 05:03:07PM +0800, Cong Yang wrote:
> > The BOE nv110wum-l60 is a 11.0" WUXGA TFT LCD panel, which fits in nicely
> > with the existing himax-hx83102 driver.
>
> From a h/w perspective, the reason to share the
Enable calculations of job submission times in clock cycles and wall
time. This is done by expanding the boilerplate command stream when running
a job to include instructions that compute said times right before an after
a user CS.
Those numbers are stored in the queue's group's sync objects BO,
This patch series enables userspace utilities like gputop and nvtop to
query a render context's fdinfo file and figure out rates of engine
and memory utilisation.
Changelog:
v2:
- Split original first patch in two, one for FW CS cycle and timestamp
calculations and job accounting memory
Drawing from the FW-calculated values in the previous commit, we can
increase the numbers for an open file by collecting them from finished jobs
when updating their group synchronisation objects.
Signed-off-by: Adrián Larumbe
---
drivers/gpu/drm/panthor/panthor_devfreq.c | 10 +
When vm-binding an already-created BO, the entirety of its virtual size is
then backed by system memory, so its RSS is always the same as its virtual
size.
Also, we consider a PRIME imported BO to be resident if its matching
dma_buf has an open attachment, which means its backing storage had
Print the accumulated runtime for client when printing fdinfo.
Each time a query is done it first does 2 things:
1) loop through all the exec queues for the current client and
accumulate the runtime, per engine class. CTX_TIMESTAMP is used for
that, being read from the context image.
2)
Add per-client usage statistics to xe. This ports xe to use the common
method in drm to export the usage to userspace per client (where 1
client == 1 drm fd open).
However insted of using the current format measured in nsec, this
creates a new one. The intention here is not to mix the GPU clock
XE_ENGINE_CLASS_OTHER was missing from the str conversion. Add it and
remove the default handling so it's protected by -Wswitch-enum.
Currently the only user is xe_hw_engine_class_sysfs_init(), which
already skips XE_ENGINE_CLASS_OTHER, so there's no change in behavior.
Reviewed-by: Nirmoy Das
Just like CTX_TIMESTAMP is used to calculate runtime, add a helper to
get the timestamp for the engine so it can be used to calculate the
"engine time" with the same unit as the runtime is recorded.
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Lucas De Marchi
---
DRM_PANEL_HIMAX_HX83102 is being split out from DRM_PANEL_BOE_TV101WUM_NL6.
Since the arm64 defconfig had the BOE panel driver enabled, let's also
enable the himax driver.
Signed-off-by: Cong Yang
Reviewed-by: Douglas Anderson
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1
The Starry HX83102 based mipi panel should never have been part of the boe
tv101wum driver. Discussion with Doug and Linus in V1 [1], we need a
separate driver to enable the hx83102 controller.
In hx83102 driver, add DSI commands as macros. So it can add some panels
with same control model in the
On Mon, 22 Apr 2024 16:47:36 +0200
Christian König wrote:
> Am 22.04.24 um 16:40 schrieb Alex Deucher:
> > On Mon, Apr 22, 2024 at 9:00 AM Christian König
> > wrote:
> >> Am 22.04.24 um 14:33 schrieb Qiang Ma:
> >>> On Mon, 22 Apr 2024 11:40:26 +0200
> >>> Christian König wrote:
> >>>
>
The BOE nv110wum-l60 is a 11.0" WUXGA TFT LCD panel with himax-hx83102
controller. Hence, we add a new compatible with panel specific config.
Signed-off-by: Cong Yang
---
Chage since V3:
- Update commit message.
V2:
The BOE nv110wum-l60 is a 11.0" WUXGA TFT LCD panel, use hx83102 controller
which fits in nicely with the existing panel-himax-hx83102 driver. Hence,
we add a new compatible with panel specific config.
Signed-off-by: Cong Yang
---
Chage since V3:
- inital cmds use lowercasehex.
V2:
The IVO t109nw41 is a 11.0" WUXGA TFT LCD panel with himax-hx83102
controller. Hence, we add a new compatible with panel specific config.
Signed-off-by: Cong Yang
---
Chage since V3:
- Update commit message.
V2:
The IVO t109nw41 is a 11.0" WUXGA TFT LCD panel, use hx83102 controller
which fits in nicely with the existing panel-himax-hx83102 driver. Hence,
we add a new compatible with panel specific config.
Signed-off-by: Cong Yang
---
Chage since V3:
- inital cmds use lowercasehex.
V2:
Discussion with Doug and Linus in V1, we need a
separate driver to enable the hx83102 controller.
So this series this series mainly Break out as separate driver
for Starry-himax83102-j02 panels from boe tv101wum driver.
Then add BOE nv110wum-l60 and IVO t109nw41 in himax-hx83102 driver.
Add
In V1, discussed with Doug and Linus [1], we need break out as separate
driver for the himax83102-j02 controller. Beacuse "starry,himax83102-j02"
and in this series "BOE nv110wum-l60" "IVO t109nw41" panels use same
controller, they have some common CMDS. So add new documentation for
this panels.
On Tue, Apr 23, 2024 at 10:30 PM Qiang Ma wrote:
>
> On Mon, 22 Apr 2024 16:47:36 +0200
> Christian König wrote:
>
> > Am 22.04.24 um 16:40 schrieb Alex Deucher:
> > > On Mon, Apr 22, 2024 at 9:00 AM Christian König
> > > wrote:
> > >> Am 22.04.24 um 14:33 schrieb Qiang Ma:
> > >>> On Mon, 22
6.8-stable review patch. If anyone has any objections, please let me know.
--
From: Zack Rusin
commit d4c972bff3129a9dd4c22a3999fd8eba1a81531a upstream.
The table of primary plane formats wasn't sorted at all, leading to
applications picking our least desirable formats by
6.8-stable review patch. If anyone has any objections, please let me know.
--
From: Zack Rusin
commit a60ccade88f926e871a57176e86a34bbf0db0098 upstream.
The conditional was supposed to prevent enabling of a crtc state
without a set primary plane. Accidently it also prevented
From: Umesh Nerlige Ramappa
Add a helper to accumulate per-client runtime of all its
exec queues. Currently that is done in 2 places:
1. when the exec_queue is destroyed
2. when the sched job is completed
Signed-off-by: Umesh Nerlige Ramappa
Signed-off-by: Lucas De Marchi
---
Move it out of the sysfs compilation unit so it can be re-used in other
places.
Reviewed-by: Nirmoy Das
Reviewed-by: Oak Zeng
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/xe/xe_hw_engine.c | 18 ++
drivers/gpu/drm/xe/xe_hw_engine.h | 1 +
From: Umesh Nerlige Ramappa
Add a helper to capture CTX_TIMESTAMP from the context image so it can
be used to calculate the runtime.
v2: Add kernel-doc to clarify expectation from caller
Signed-off-by: Umesh Nerlige Ramappa
Signed-off-by: Lucas De Marchi
---
On Tue, Apr 23, 2024 at 03:17:03PM -0600, Zeng, Oak wrote:
> Hi Jason,
>
> Sorry for a late reply. I have been working on a v2 of this series:
> https://patchwork.freedesktop.org/series/132229/. This version addressed some
> of your concerns, such as removing the global character device,
On Wed, Apr 24, 2024 at 12:49:18AM +0800, Sui Jingfeng wrote:
> Hi,
>
> Thanks a for you reviewing my patch.
>
>
> On 2024/4/23 21:28, Andy Shevchenko wrote:
> > On Tue, Apr 23, 2024 at 12:46:58AM +0800, Sui Jingfeng wrote:
> > > Because the software node backend of the fwnode API framework
6.1-stable review patch. If anyone has any objections, please let me know.
--
From: Zack Rusin
commit d4c972bff3129a9dd4c22a3999fd8eba1a81531a upstream.
The table of primary plane formats wasn't sorted at all, leading to
applications picking our least desirable formats by
6.1-stable review patch. If anyone has any objections, please let me know.
--
From: Zack Rusin
commit a60ccade88f926e871a57176e86a34bbf0db0098 upstream.
The conditional was supposed to prevent enabling of a crtc state
without a set primary plane. Accidently it also prevented
5.15-stable review patch. If anyone has any objections, please let me know.
--
From: Zack Rusin
commit d4c972bff3129a9dd4c22a3999fd8eba1a81531a upstream.
The table of primary plane formats wasn't sorted at all, leading to
applications picking our least desirable formats by
When Panfrost must pin an object that is being prepared a dma-buf
attachment for on behalf of another driver, the core drm gem object pinning
code already takes a lock on the object's dma reservation.
However, Panfrost GEM object's pinning callback would eventually try taking
the lock on the same
On 4/23/24 04:05, Maxime Ripard wrote:
Hi,
On Mon, Apr 22, 2024 at 01:08:44PM -0300, Maíra Canal wrote:
@drm-misc maintainers, is there any chance you could backport commit
35f4f8c9fc97 ("drm/v3d: Don't increment `enabled_ns` twice") [1] to drm-
misc-next?
I would like to apply this series to
Hi Doug, thank you!
We had reported this info to the CSOT to correct the vendor id.
If they confirm to fix this with the same product ID, we will submit a
patch to fix this.
Doug Anderson 于2024年4月24日周三 01:01写道：
>
> Hi,
>
> On Mon, Apr 22, 2024 at 6:28 PM Xuxin Xiong
> wrote:
> >
> > Yes, I
Hi,
Thanks reply.
Doug Anderson 于2024年4月24日周三 00:26写道：
>
> Hi,
>
> On Tue, Apr 23, 2024 at 2:37 AM cong yang
> wrote:
> >
> > > > +static int starry_init_cmd(struct hx83102 *ctx)
> > > > +{
> > > > + struct mipi_dsi_device *dsi = ctx->dsi;
> > > > +
> > > > +
On 23/04/24 20:34, Nilawar, Badal wrote:
>
>
> On 22-04-2024 12:27, Aravind Iddamsetty wrote:
>> PCI subsystem provides callbacks to inform the driver about a request to
>> do function level reset by user, initiated by writing to sysfs entry
>> /sys/bus/pci/devices/.../reset. This will allow the
On Tue, Apr 23, 2024 at 04:56:48PM -0700, Lucas De Marchi wrote:
> From: Umesh Nerlige Ramappa
>
> Add a helper to accumulate per-client runtime of all its
> exec queues. Currently that is done in 2 places:
>
> 1. when the exec_queue is destroyed
> 2. when the sched job is completed
Update the vertical and horizontal scaler registers of XLCDC IP
with Bilinear and Bicubic co-efficients taps for Chroma and
Luma componenets of the Pixel.
Signed-off-by: Manikandan Muralidharan
Acked-by: Sam Ravnborg
---
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h | 4
Add support for the following DPI mode if the encoder type
is DSI as per the XLCDC IP datasheet:
- 16BPPCFG1
- 16BPPCFG2
- 16BPPCFG3
- 18BPPCFG1
- 18BPPCFG2
- 24BPP
Signed-off-by: Manikandan Muralidharan
[durai.manicka...@microchip.com: update output format using is_xlcdc flag]
Signed-off-by:
Add support for Display Pixel Interface (DPI) Compatible Mode
support in atmel-hlcdc driver for XLCDC IP along with legacy
pixel mapping. DPI mode BIT is configured in LCDC_CFG5 register.
Signed-off-by: Manikandan Muralidharan
[durai.manicka...@microchip.com: update DPI mode bit using is_xlcdc
Add the LCD controller layer definition and descriptor structure for
sam9x75 for the following layers:
- Base Layer
- Overlay1 Layer
- Overlay2 Layer
- High End Overlay
Signed-off-by: Manikandan Muralidharan
Acked-by: Sam Ravnborg
---
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c | 100
On 24/04/24 05:19, Michał Winiarski wrote:
> On Mon, Apr 22, 2024 at 12:27:56PM +0530, Aravind Iddamsetty wrote:
>> PCI subsystem provides callbacks to inform the driver about a request to
>> do function level reset by user, initiated by writing to sysfs entry
>> /sys/bus/pci/devices/.../reset.
Hi,
On 2024/4/24 05:37, Dmitry Baryshkov wrote:
On Wed, Apr 24, 2024 at 12:49:18AM +0800, Sui Jingfeng wrote:
Hi,
Thanks a for you reviewing my patch.
On 2024/4/23 21:28, Andy Shevchenko wrote:
On Tue, Apr 23, 2024 at 12:46:58AM +0800, Sui Jingfeng wrote:
Because the software node
This patch series aims to add support for XLCDC IP of sam9x7 SoC family
to the DRM subsystem.XLCDC IP has additional registers and new
configuration bits compared to the existing register set of HLCDC IP.
The new compatible string "microchip,sam9x75-xlcdc" is defined for sam9x75
variant of the
Replace regmap_read with regmap_read_poll_timeout to neatly handle
retries
Signed-off-by: Manikandan Muralidharan
---
.../gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c| 44 +++
1 file changed, 25 insertions(+), 19 deletions(-)
diff --git
From: Durai Manickam KR
The register address of the XLCDC IP used in SAM9X7 SoC family
are different from the previous HLCDC. Defining those address
space with valid macros.
Signed-off-by: Durai Manickam KR
[manikanda...@microchip.com: Remove unused macro definitions]
Signed-off-by: Manikandan
Add XLCDC specific driver ops and is_xlcdc flag to separate the
functionality and to access the controller registers.
HEO scaling, window resampling, Alpha blending, YUV-to-RGB
conversion in XLCDC is derived and handled using additional
configuration bits and registers. Writing one to the Enable
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