[PATCH 9/9] drm/i915: Initialize PCH refclks at modeset init time

2011-09-27 Thread Chris Wilson
On Mon, 26 Sep 2011 23:11:46 -0700, Keith Packard wrote: > The reference clock configuration must be done before any mode setting > can occur as all outputs must be disabled to change > anything. Initialize the clocks after turning everything off during > the initialization process. Ah, now I

[PATCH 8/9] drm/i915: All PCH refclks are 120MHz

2011-09-27 Thread Chris Wilson
On Mon, 26 Sep 2011 23:11:45 -0700, Keith Packard wrote: > I can't find any reference clocks which run at 96MHz as seems to be > indicated from the comments in this code. > > Signed-off-by: Keith Packard I think there exists a 100MHz test mode (certainly there is reference to such in the

[PATCH 7/9] drm/i915: Use CK505 as non-SSC source where available

2011-09-27 Thread Chris Wilson
On Mon, 26 Sep 2011 23:11:44 -0700, Keith Packard wrote: > This eliminates VGA shimmer on some Ironlake machines which have a > CK505 clock source. > > Signed-off-by: Keith Packard References: https://bugzilla.kernel.org/show_bug.cgi?id=21742 References:

[PATCH 6/9] drm/i915: Fix PCH SSC reference clock settings

2011-09-27 Thread Chris Wilson
On Mon, 26 Sep 2011 23:11:43 -0700, Keith Packard wrote: > The PCH refclk settings are global, so we need to look at all of the > encoders, not just the current encoder when deciding how to configure > it. Also, handle systems with more than one panel (any combination of > PCH/non-PCH eDP and

[PATCH 5/9] drm/i915: Allow SSC parameter to override VBT value

2011-09-27 Thread Chris Wilson
On Mon, 26 Sep 2011 23:11:42 -0700, Keith Packard wrote: > Allow SSC to be enabled even when the BIOS disables it for testing SSC paths. > > Signed-off-by: Keith Packard Reviewed-by: Chris Wilson -Chris -- Chris Wilson, Intel Open Source Technology Centre

[PATCH 3/9] drv/i915: Pull display_clock_mode out of VBT table

2011-09-27 Thread Chris Wilson
On Mon, 26 Sep 2011 23:11:40 -0700, Keith Packard wrote: > This tells the driver whether a CK505 clock source is available on > pre-PCH hardware. If so, it should be used as the non-SSC source, > leaving the internal clock for use as the SSC source. > > Signed-off-by: Keith Packard Reviewed-by:

[PATCH 2/9] drm/i915: Use DRM_DEBUG_KMS for all messages in intel_bios.c

2011-09-27 Thread Chris Wilson
On Mon, 26 Sep 2011 23:11:39 -0700, Keith Packard wrote: > These are all KMS related anyways, so don't hide them under other > debug levels. > > Signed-off-by: Keith Packard Reviewed-by: Chris Wilson -Chris -- Chris Wilson, Intel Open Source Technology Centre

[PATCH 9/9] drm/i915: Initialize PCH refclks at modeset init time

2011-09-27 Thread Keith Packard
I didn't get right? -- keith.packard at intel.com -- next part -- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 189 bytes Desc: not available URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20

[PATCH 6/9] drm/i915: Fix PCH SSC reference clock settings

2011-09-27 Thread Keith Packard
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[PATCH] drm/gem: add functions to get/put pages

2011-09-27 Thread Alan Cox
> Well I think for this case the solution is simple: Tiling not allowed > if userspace is too dumb to properly round the buffer up so it > fulfills whatever odd requirement the hw has. I think hiding the fact > that certain buffers need more backing storage than a naive userspace > might assume is

PCH reference clock cleanups

2011-09-27 Thread Chris Wilson
On Mon, 26 Sep 2011 23:11:37 -0700, Keith Packard wrote: > Ok, so I'd love to know where in any PCH reference matter someone has > found a place where the reference clock for any of the PLLs is > anything other than 120MHz. Can someone find a reference for other > frequencies? Oddly in the

PCH reference clock cleanups

2011-09-27 Thread Keith Packard
h.packard at intel.com -- next part -- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 189 bytes Desc: not available URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20110927/26719730/attachment.pgp>

[Bug 41265] KMS does not work on Radeon HD6700M

2011-09-27 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=41265 Varban changed: What|Removed |Added Component|DRM/other |DRM/Radeon --- Comment #1 from Varban

[Bug 41265] New: KMS does not work on Radeon HD6700M

2011-09-27 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=41265 Summary: KMS does not work on Radeon HD6700M Product: DRI Version: unspecified Platform: x86-64 (AMD64) OS/Version: Linux (All) Status: NEW Severity: major

[Bug 41263] [r600g] glCopyTexImage2D selects a texture format that involves fallback to software

2011-09-27 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=41263 --- Comment #1 from Simon Farnsworth 2011-09-27 08:31:26 PDT --- Forgot to mention - I'm looking at Mesa git, as of: commit 4c84fbea9d496567d706468113d63cd8f0faeb7f Author: Brian Paul Date: Mon Sep 26 20:44:09 2011 -0600 mesa: fix

[Bug 41263] New: [r600g] glCopyTexImage2D selects a texture format that involves fallback to software

2011-09-27 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=41263 Summary: [r600g] glCopyTexImage2D selects a texture format that involves fallback to software Product: DRI Version: XOrg CVS Platform: x86 (IA32) OS/Version: Linux (All)

[PATCH] drm/gem: add functions to get/put pages

2011-09-27 Thread Rob Clark
On Tue, Sep 27, 2011 at 4:35 AM, Alan Cox wrote: >> Well I think for this case the solution is simple: Tiling not allowed >> if userspace is too dumb to properly round the buffer up so it >> fulfills whatever odd requirement the hw has. I think hiding the fact >> that certain buffers need more

[Bug 8874] xorg crashes when switching virtual console with mga g550

2011-09-27 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=8874 --- Comment #5 from Michal Suchanek 2011-09-27 07:41:41 PDT --- isn't this bug 8191 ? -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the

[Bug 39320] util/u_upload_mgr.c:192:u_upload_alloc: Assertion `offset < upload->buffer->width0' failed.

2011-09-27 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=39320 Michal Suchanek changed: What|Removed |Added Status|NEW |RESOLVED Resolution|

Curious experiences with a Radeon on the fritz

2011-09-27 Thread Tormod Volden
On Wed, Sep 21, 2011 at 8:52 PM, Michael Witten wrote: > Because my hardware does appear to be malfunctioning due to a corrupt > video BIOS, it seems prudent to salvage as much as possible from > its output, so that it is possible to figure out which other values > need to be hardcoded in case of

Curious experiences with a Radeon on the fritz

2011-09-27 Thread Michael Witten
On Mon, Sep 26, 2011 at 21:51, Tormod Volden wrote: > On Wed, Sep 21, 2011 at 8:52 PM, Michael Witten wrote: >> Because my hardware does appear to be malfunctioning due to a corrupt >> video BIOS, it seems prudent to salvage as much as possible from >> its output, so that it is possible to figure

[PATCH 9/9] drm/i915: Initialize PCH refclks at modeset init time

2011-09-27 Thread Keith Packard
The reference clock configuration must be done before any mode setting can occur as all outputs must be disabled to change anything. Initialize the clocks after turning everything off during the initialization process. Signed-off-by: Keith Packard --- drivers/gpu/drm/i915/intel_display.c | 10

[PATCH 8/9] drm/i915: All PCH refclks are 120MHz

2011-09-27 Thread Keith Packard
I can't find any reference clocks which run at 96MHz as seems to be indicated from the comments in this code. Signed-off-by: Keith Packard --- drivers/gpu/drm/i915/intel_display.c | 14 -- 1 files changed, 4 insertions(+), 10 deletions(-) diff --git

[PATCH 7/9] drm/i915: Use CK505 as non-SSC source where available

2011-09-27 Thread Keith Packard
This eliminates VGA shimmer on some Ironlake machines which have a CK505 clock source. Signed-off-by: Keith Packard --- drivers/gpu/drm/i915/intel_display.c | 12 +--- 1 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c

[PATCH 6/9] drm/i915: Fix PCH SSC reference clock settings

2011-09-27 Thread Keith Packard
The PCH refclk settings are global, so we need to look at all of the encoders, not just the current encoder when deciding how to configure it. Also, handle systems with more than one panel (any combination of PCH/non-PCH eDP and LVDS). Disable SSC clocks when no panels are connected.

[PATCH 5/9] drm/i915: Allow SSC parameter to override VBT value

2011-09-27 Thread Keith Packard
Allow SSC to be enabled even when the BIOS disables it for testing SSC paths. Signed-off-by: Keith Packard --- drivers/gpu/drm/i915/i915_drv.c |4 ++-- drivers/gpu/drm/i915/intel_display.c |4 +++- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git

[PATCH 4/9] drm/i915: Document a few more BDB_GENERAL_FEATURES bits from PCH BIOS

2011-09-27 Thread Keith Packard
This includes whether an eDP panel is present, and whether that should use SSC (and at what frequency) Signed-off-by: Keith Packard --- drivers/gpu/drm/i915/intel_bios.h |5 - 1 files changed, 4 insertions(+), 1 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_bios.h

[PATCH 3/9] drv/i915: Pull display_clock_mode out of VBT table

2011-09-27 Thread Keith Packard
This tells the driver whether a CK505 clock source is available on pre-PCH hardware. If so, it should be used as the non-SSC source, leaving the internal clock for use as the SSC source. Signed-off-by: Keith Packard --- drivers/gpu/drm/i915/i915_drv.h |1 +

[PATCH 2/9] drm/i915: Use DRM_DEBUG_KMS for all messages in intel_bios.c

2011-09-27 Thread Keith Packard
These are all KMS related anyways, so don't hide them under other debug levels. Signed-off-by: Keith Packard --- drivers/gpu/drm/i915/intel_bios.c |9 +++-- 1 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_bios.c

[PATCH 1/9] drm/i915: broken copyright encoding in intel_bios.c

2011-09-27 Thread Keith Packard
Signed-off-by: Keith Packard --- drivers/gpu/drm/i915/intel_bios.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c index 61abef8..4c530fa 100644 --- a/drivers/gpu/drm/i915/intel_bios.c +++

PCH reference clock cleanups

2011-09-27 Thread Keith Packard
Here's a patch sequence which cleans up a bunch of PCH refclk related bits. There are a couple of questionable patches that I'd like to see people look at: [PATCH 6/9] drm/i915: Fix PCH SSC reference clock settings [PATCH 9/9] drm/i915: Initialize PCH refclks at modeset init time Here's the

PCH reference clock cleanups

2011-09-27 Thread Keith Packard
Here's a patch sequence which cleans up a bunch of PCH refclk related bits. There are a couple of questionable patches that I'd like to see people look at: [PATCH 6/9] drm/i915: Fix PCH SSC reference clock settings [PATCH 9/9] drm/i915: Initialize PCH refclks at modeset init time Here's the

[PATCH 1/9] drm/i915: broken copyright encoding in intel_bios.c

2011-09-27 Thread Keith Packard
Signed-off-by: Keith Packard kei...@keithp.com --- drivers/gpu/drm/i915/intel_bios.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c index 61abef8..4c530fa 100644 ---

[PATCH 3/9] drv/i915: Pull display_clock_mode out of VBT table

2011-09-27 Thread Keith Packard
This tells the driver whether a CK505 clock source is available on pre-PCH hardware. If so, it should be used as the non-SSC source, leaving the internal clock for use as the SSC source. Signed-off-by: Keith Packard kei...@keithp.com --- drivers/gpu/drm/i915/i915_drv.h |1 +

[PATCH 5/9] drm/i915: Allow SSC parameter to override VBT value

2011-09-27 Thread Keith Packard
Allow SSC to be enabled even when the BIOS disables it for testing SSC paths. Signed-off-by: Keith Packard kei...@keithp.com --- drivers/gpu/drm/i915/i915_drv.c |4 ++-- drivers/gpu/drm/i915/intel_display.c |4 +++- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git

[PATCH 4/9] drm/i915: Document a few more BDB_GENERAL_FEATURES bits from PCH BIOS

2011-09-27 Thread Keith Packard
This includes whether an eDP panel is present, and whether that should use SSC (and at what frequency) Signed-off-by: Keith Packard kei...@keithp.com --- drivers/gpu/drm/i915/intel_bios.h |5 - 1 files changed, 4 insertions(+), 1 deletions(-) diff --git

[PATCH 2/9] drm/i915: Use DRM_DEBUG_KMS for all messages in intel_bios.c

2011-09-27 Thread Keith Packard
These are all KMS related anyways, so don't hide them under other debug levels. Signed-off-by: Keith Packard kei...@keithp.com --- drivers/gpu/drm/i915/intel_bios.c |9 +++-- 1 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_bios.c

[PATCH 9/9] drm/i915: Initialize PCH refclks at modeset init time

2011-09-27 Thread Keith Packard
The reference clock configuration must be done before any mode setting can occur as all outputs must be disabled to change anything. Initialize the clocks after turning everything off during the initialization process. Signed-off-by: Keith Packard kei...@keithp.com ---

[PATCH 8/9] drm/i915: All PCH refclks are 120MHz

2011-09-27 Thread Keith Packard
I can't find any reference clocks which run at 96MHz as seems to be indicated from the comments in this code. Signed-off-by: Keith Packard kei...@keithp.com --- drivers/gpu/drm/i915/intel_display.c | 14 -- 1 files changed, 4 insertions(+), 10 deletions(-) diff --git

[PATCH 6/9] drm/i915: Fix PCH SSC reference clock settings

2011-09-27 Thread Keith Packard
The PCH refclk settings are global, so we need to look at all of the encoders, not just the current encoder when deciding how to configure it. Also, handle systems with more than one panel (any combination of PCH/non-PCH eDP and LVDS). Disable SSC clocks when no panels are connected.

[PATCH 7/9] drm/i915: Use CK505 as non-SSC source where available

2011-09-27 Thread Keith Packard
This eliminates VGA shimmer on some Ironlake machines which have a CK505 clock source. Signed-off-by: Keith Packard kei...@keithp.com --- drivers/gpu/drm/i915/intel_display.c | 12 +--- 1 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c

Re: PCH reference clock cleanups

2011-09-27 Thread Chris Wilson
On Mon, 26 Sep 2011 23:11:37 -0700, Keith Packard kei...@keithp.com wrote: Ok, so I'd love to know where in any PCH reference matter someone has found a place where the reference clock for any of the PLLs is anything other than 120MHz. Can someone find a reference for other frequencies?

Re: [PATCH] drm/gem: add functions to get/put pages

2011-09-27 Thread Alan Cox
Well I think for this case the solution is simple: Tiling not allowed if userspace is too dumb to properly round the buffer up so it fulfills whatever odd requirement the hw has. I think hiding the fact that certain buffers need more backing storage than a naive userspace might assume is ripe

[Bug 39320] util/u_upload_mgr.c:192:u_upload_alloc: Assertion `offset upload-buffer-width0' failed.

2011-09-27 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=39320 Michal Suchanek hramr...@gmail.com changed: What|Removed |Added Status|NEW |RESOLVED

Re: [PATCH] drm/gem: add functions to get/put pages

2011-09-27 Thread Rob Clark
On Tue, Sep 27, 2011 at 4:35 AM, Alan Cox a...@lxorguk.ukuu.org.uk wrote: Well I think for this case the solution is simple: Tiling not allowed if userspace is too dumb to properly round the buffer up so it fulfills whatever odd requirement the hw has. I think hiding the fact that certain

[Bug 41263] New: [r600g] glCopyTexImage2D selects a texture format that involves fallback to software

2011-09-27 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=41263 Summary: [r600g] glCopyTexImage2D selects a texture format that involves fallback to software Product: DRI Version: XOrg CVS Platform: x86 (IA32) OS/Version: Linux (All)

[Bug 41263] [r600g] glCopyTexImage2D selects a texture format that involves fallback to software

2011-09-27 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=41263 --- Comment #1 from Simon Farnsworth simon.farnswo...@onelan.co.uk 2011-09-27 08:31:26 PDT --- Forgot to mention - I'm looking at Mesa git, as of: commit 4c84fbea9d496567d706468113d63cd8f0faeb7f Author: Brian Paul bri...@vmware.com Date: Mon

[Bug 41265] New: KMS does not work on Radeon HD6700M

2011-09-27 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=41265 Summary: KMS does not work on Radeon HD6700M Product: DRI Version: unspecified Platform: x86-64 (AMD64) OS/Version: Linux (All) Status: NEW Severity: major

[Bug 41265] KMS does not work on Radeon HD6700M

2011-09-27 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=41265 Varban weasalan...@yahoo.com changed: What|Removed |Added Component|DRM/other |DRM/Radeon --- Comment #1

Re: [PATCH 2/9] drm/i915: Use DRM_DEBUG_KMS for all messages in intel_bios.c

2011-09-27 Thread Chris Wilson
On Mon, 26 Sep 2011 23:11:39 -0700, Keith Packard kei...@keithp.com wrote: These are all KMS related anyways, so don't hide them under other debug levels. Signed-off-by: Keith Packard kei...@keithp.com Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk -Chris -- Chris Wilson, Intel Open

Re: [PATCH 3/9] drv/i915: Pull display_clock_mode out of VBT table

2011-09-27 Thread Chris Wilson
On Mon, 26 Sep 2011 23:11:40 -0700, Keith Packard kei...@keithp.com wrote: This tells the driver whether a CK505 clock source is available on pre-PCH hardware. If so, it should be used as the non-SSC source, leaving the internal clock for use as the SSC source. Signed-off-by: Keith Packard

Re: [PATCH 5/9] drm/i915: Allow SSC parameter to override VBT value

2011-09-27 Thread Chris Wilson
On Mon, 26 Sep 2011 23:11:42 -0700, Keith Packard kei...@keithp.com wrote: Allow SSC to be enabled even when the BIOS disables it for testing SSC paths. Signed-off-by: Keith Packard kei...@keithp.com Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk -Chris -- Chris Wilson, Intel Open Source

Re: [PATCH 6/9] drm/i915: Fix PCH SSC reference clock settings

2011-09-27 Thread Chris Wilson
On Mon, 26 Sep 2011 23:11:43 -0700, Keith Packard kei...@keithp.com wrote: The PCH refclk settings are global, so we need to look at all of the encoders, not just the current encoder when deciding how to configure it. Also, handle systems with more than one panel (any combination of

Re: [PATCH 7/9] drm/i915: Use CK505 as non-SSC source where available

2011-09-27 Thread Chris Wilson
On Mon, 26 Sep 2011 23:11:44 -0700, Keith Packard kei...@keithp.com wrote: This eliminates VGA shimmer on some Ironlake machines which have a CK505 clock source. Signed-off-by: Keith Packard kei...@keithp.com References: https://bugzilla.kernel.org/show_bug.cgi?id=21742 References:

Re: [PATCH 8/9] drm/i915: All PCH refclks are 120MHz

2011-09-27 Thread Chris Wilson
On Mon, 26 Sep 2011 23:11:45 -0700, Keith Packard kei...@keithp.com wrote: I can't find any reference clocks which run at 96MHz as seems to be indicated from the comments in this code. Signed-off-by: Keith Packard kei...@keithp.com I think there exists a 100MHz test mode (certainly there is

Re: PCH reference clock cleanups

2011-09-27 Thread Keith Packard
On Tue, 27 Sep 2011 10:01:33 +0100, Chris Wilson ch...@chris-wilson.co.uk wrote: Oddly in the diagram SSC4 is given as a 100MHz clock that can be used for any output other than DP_A. However, the configuration register marks that as being a test-only mode. Ok, it's all irrelevant -- the only

Re: [PATCH 9/9] drm/i915: Initialize PCH refclks at modeset init time

2011-09-27 Thread Chris Wilson
On Mon, 26 Sep 2011 23:11:46 -0700, Keith Packard kei...@keithp.com wrote: The reference clock configuration must be done before any mode setting can occur as all outputs must be disabled to change anything. Initialize the clocks after turning everything off during the initialization process.

Re: [PATCH 6/9] drm/i915: Fix PCH SSC reference clock settings

2011-09-27 Thread Keith Packard
On Tue, 27 Sep 2011 17:47:10 +0100, Chris Wilson ch...@chris-wilson.co.uk wrote: On Mon, 26 Sep 2011 23:11:43 -0700, Keith Packard kei...@keithp.com wrote: The PCH refclk settings are global, so we need to look at all of the encoders, not just the current encoder when deciding how to