RE: [PATCH v2] i2c: tegra: Add ACPI support
> 23.11.2021 10:15, Akhil R пишет:
> > Add support for ACPI based device registration so that the driver can
> > be also enabled through ACPI table.
> >
> > Signed-off-by: Akhil R
> > ---
> > drivers/i2c/busses/i2c-tegra.c | 52
> > --
> > 1 file changed, 40 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/i2c/busses/i2c-tegra.c
> > b/drivers/i2c/busses/i2c-tegra.c index c883044..8e47889 100644
> > --- a/drivers/i2c/busses/i2c-tegra.c
> > +++ b/drivers/i2c/busses/i2c-tegra.c
> > @@ -6,6 +6,7 @@
> > * Author: Colin Cross
> > */
> >
> > +#include
> > #include
> > #include
> > #include
> > @@ -608,6 +609,7 @@ static int tegra_i2c_wait_for_config_load(struct
> > tegra_i2c_dev *i2c_dev) static int tegra_i2c_init(struct
> > tegra_i2c_dev *i2c_dev) {
> > u32 val, clk_divisor, clk_multiplier, tsu_thd, tlow, thigh,
> > non_hs_mode;
> > + acpi_handle handle = ACPI_HANDLE(i2c_dev->dev);
> > int err;
> >
> > /*
> > @@ -618,7 +620,11 @@ static int tegra_i2c_init(struct tegra_i2c_dev
> *i2c_dev)
> >* emit a noisy warning on error, which won't stay unnoticed and
> >* won't hose machine entirely.
> >*/
> > - err = reset_control_reset(i2c_dev->rst);
> > + if (handle && acpi_has_method(handle, "_RST"))
>
> Which SoC version doesn't have "_RST" method? If neither, then please remove
> this check.
>
> > + err = (acpi_evaluate_object(handle, "_RST", NULL,
> > + NULL));
>
> Please remove parens around acpi_evaluate_object(). Why you added them?
>
> > + else
> > + err = reset_control_reset(i2c_dev->rst);
> > +
> > WARN_ON_ONCE(err);
> >
> > if (i2c_dev->is_dvc)
> > @@ -1627,12 +1633,12 @@ static void tegra_i2c_parse_dt(struct
> tegra_i2c_dev *i2c_dev)
> > bool multi_mode;
> > int err;
> >
> > - err = of_property_read_u32(np, "clock-frequency",
> > -_dev->bus_clk_rate);
> > + err = device_property_read_u32(i2c_dev->dev, "clock-frequency",
> > +_dev->bus_clk_rate);
> > if (err)
> > i2c_dev->bus_clk_rate = I2C_MAX_STANDARD_MODE_FREQ;
> >
> > - multi_mode = of_property_read_bool(np, "multi-master");
> > + multi_mode = device_property_read_bool(i2c_dev->dev,
> > + "multi-master");
> > i2c_dev->multimaster_mode = multi_mode;
> >
> > if (of_device_is_compatible(np, "nvidia,tegra20-i2c-dvc")) @@
> > -1642,10 +1648,25 @@ static void tegra_i2c_parse_dt(struct tegra_i2c_dev
> *i2c_dev)
> > i2c_dev->is_vi = true;
> > }
> How are you going to differentiate the VI I2C from a non-VI? This doesn't look
> right.
This patch adds the ACPI support to only non-VI I2C. The device_ids in match
table
are added accordingly. I suppose, of_device_is_compatible always returns false
as
there is no device tree.
Agree with the other comments.
Re: [PATCH 1/2] drm: exynos: dsi: Convert to bridge driver
Hi Marek, On Mon, Nov 22, 2021 at 9:34 PM Marek Szyprowski wrote: > > On 22.11.2021 16:07, Marek Szyprowski wrote: > > On 22.11.2021 15:55, Jagan Teki wrote: > >> On Mon, Nov 22, 2021 at 7:59 PM Jagan Teki > >> wrote: > >>> On Mon, Nov 22, 2021 at 7:51 PM Jagan Teki > >>> wrote: > On Mon, Nov 22, 2021 at 7:45 PM Marek Szyprowski > wrote: > > On 22.11.2021 08:06, Jagan Teki wrote: > >> Some display panels would come up with a non-DSI output, those > >> can have an option to connect the DSI host by means of interface > >> bridge converter. > >> > >> This DSI to non-DSI interface bridge converter would requires > >> DSI Host to handle drm bridge functionalities in order to DSI > >> Host to Interface bridge. > >> > >> This patch convert the existing to a drm bridge driver with a > >> built-in encoder support for compatibility with existing > >> component drivers. > >> > >> Signed-off-by: Jagan Teki > >> --- > >> Note: > >> Hi Marek Szyprowski, > >> > >> Please test this on Panel and Bridge hardware. > > I don't have good news, t crashes: > > > > [drm] Exynos DRM: using 1380.decon device for DMA mapping > > operations > > exynos-drm exynos-drm: bound 1380.decon (ops decon_component_ops) > > exynos-drm exynos-drm: bound 1388.decon (ops decon_component_ops) > > exynos-drm exynos-drm: bound 1393.mic (ops > > exynos_mic_component_ops) > > [drm:drm_bridge_attach] *ERROR* failed to attach bridge > > /soc@0/dsi@1390 to encoder TMDS-67: -22 > > exynos-drm exynos-drm: failed to bind 1390.dsi (ops > > exynos_dsi_component_ops): -22 > > Internal error: synchronous external abort: 96000210 [#1] PREEMPT SMP > > Modules linked in: > > CPU: 2 PID: 74 Comm: kworker/u16:1 Not tainted 5.16.0-rc1+ #4141 > > Hardware name: Samsung TM2E board (DT) > > Workqueue: events_unbound deferred_probe_work_func > > pstate: 8005 (Nzcv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) > > pc : decon_atomic_disable+0x58/0xd4 > > lr : decon_atomic_disable+0x28/0xd4 > > sp : 80001390b940 > > x29: 80001390b940 x28: 80001259a000 x27: 27f39e80 > > input: stmfts as > > /devices/platform/soc@0/14ed.hsi2c/i2c-3/3-0049/input/input0 > > x26: ffea x25: 25a40280 x24: 0001 > > x23: 800011b55f98 x22: 315dc000 x21: 2695d100 > > x20: 27e7a080 x19: 315e6000 x18: > > x17: 645f736f6e797865 x16: 2073706f28206973 x15: 00028ee0 > > x14: 0028 x13: 0001 x12: 0040 > > x11: 23c18920 x10: 23c18922 x9 : 8000126352f0 > > x8 : 23c00270 x7 : x6 : 23c00268 > > x5 : 27e7a3a0 x4 : 0001 x3 : 27e7a080 > > x2 : 0024 x1 : 800013bc8024 x0 : 246117c0 > > Call trace: > >decon_atomic_disable+0x58/0xd4 > >decon_unbind+0x1c/0x3c > >component_unbind+0x38/0x60 > >component_bind_all+0x16c/0x25c > >exynos_drm_bind+0x104/0x1bc > >try_to_bring_up_master+0x164/0x1d0 > >__component_add+0xa8/0x174 > >component_add+0x14/0x20 > >hdmi_probe+0x438/0x710 > >platform_probe+0x68/0xe0 > >really_probe.part.0+0x9c/0x31c > >__driver_probe_device+0x98/0x144 > >driver_probe_device+0xc8/0x160 > >__device_attach_driver+0xb8/0x120 > >bus_for_each_drv+0x78/0xd0 > >__device_attach+0xd8/0x180 > >device_initial_probe+0x14/0x20 > >bus_probe_device+0x9c/0xa4 > >deferred_probe_work_func+0x88/0xc4 > >process_one_work+0x288/0x6f0 > >worker_thread+0x74/0x470 > >kthread+0x188/0x194 > >ret_from_fork+0x10/0x20 > > Code: 11002042 f9481c61 531e7442 8b020021 (88dffc21) > > ---[ end trace d73aff585b108954 ]--- > > Kernel panic - not syncing: synchronous external abort: Fatal > > exception > > SMP: stopping secondary CPUs > > Kernel Offset: disabled > > CPU features: 0x2,300071c2,0846 > > Memory Limit: none > > ---[ end Kernel panic - not syncing: synchronous external abort: > > Fatal > > exception ]--- > Is this with Bridge or normal DSI panel? > >>> Can you apply this patch and check? > >>> https://protect2.fireeye.com/v1/url?k=aad62f08-f54d1627-aad7a447-0cc47a31cdf8-ea5858ddb7f0ecfe=1=2d730862-2c56-4988-a252-8febd02da578=https%3A%2F%2Fgithub.com%2Fopenedev%2Flinux%2Fcommit%2F412f226acd774356e8188c9e62b653672926ee0d > >>> > >> Any news on this? just asking in case if you missed it. > > > > It is somehow better. System doesn't crash, but the DRM is not bound: > > > > # cat /sys/kernel/debug/device_component/exynos-drm > > master namestatus > >
[Bug 211277] sometimes crash at s2ram-wake (Ryzen 3500U): amdgpu, drm, commit_tail, amdgpu_dm_atomic_commit_tail
https://bugzilla.kernel.org/show_bug.cgi?id=211277 --- Comment #77 from James Zhu (jam...@amd.com) --- Created attachment 299697 --> https://bugzilla.kernel.org/attachment.cgi?id=299697=edit backport patch for 5.10 stable. Hi @kolAflash, before I send out them to public for review,. could you help take a test? Thanks so much! James -- You may reply to this email to add a comment. You are receiving this mail because: You are watching the assignee of the bug.
[PATCH] drm/i915/dmabuf: remove duplicate include in i915_gem_dmabuf.c
From: Yao Jing 'asm/smp.h' included in 'drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c' is duplicated. It is clearly included on the 12 line. Reported-by: Zeal Robot Signed-off-by: Yao Jing --- drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c index f291cf4c3886..5712b6b5f285 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c @@ -17,9 +17,7 @@ MODULE_IMPORT_NS(DMA_BUF); -#if defined(CONFIG_X86) -#include -#else +#if !defined(CONFIG_X86) #define wbinvd_on_all_cpus() \ pr_warn(DRIVER_NAME ": Missing cache flush in %s\n", __func__) #endif -- 2.25.1
[PATCH] drm/amd/display: fix application of sizeof to pointer
From: Lv Ruyi
Both of split and merge are pointers, not arrays.
Reported-by: Zeal Robot
Signed-off-by: Lv Ruyi
---
drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c
b/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c
index ece34b0b8a46..91810aaee5a3 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c
@@ -1223,8 +1223,8 @@ static void dml_full_validate_bw_helper(struct dc *dc,
*pipe_cnt = dml_populate_dml_pipes_from_context(dc, context,
pipes, false);
*vlevel = dml_get_voltage_level(>bw_ctx.dml, pipes,
*pipe_cnt);
if (*vlevel < context->bw_ctx.dml.soc.num_states) {
- memset(split, 0, sizeof(split));
- memset(merge, 0, sizeof(merge));
+ memset(split, 0, MAX_PIPES * sizeof(*split));
+ memset(merge, 0, MAX_PIPES * sizeof(*merge));
*vlevel = dml_validate_apply_pipe_split_flags(dc,
context, *vlevel, split, merge);
}
--
2.25.1
Re: [PATCH v5 2/2] drm/bridge: lvds-codec: Add support for pixel data sampling edge select
On 10/24/21 1:04 AM, Marek Vasut wrote:
On 10/17/21 7:40 PM, Sam Ravnborg wrote:
Hi Marek,
Hi,
On Sun, Oct 17, 2021 at 07:29:51PM +0200, Marek Vasut wrote:
On 10/17/21 6:49 PM, Sam Ravnborg wrote:
[...]
+ /*
+ * Encoder might sample data on different clock edge than the
display,
+ * for example OnSemi FIN3385 has a dedicated strapping pin to
select
+ * the sampling edge.
+ */
+ if (lvds_codec->connector_type == DRM_MODE_CONNECTOR_LVDS &&
+ !of_property_read_u32(dev->of_node, "pclk-sample", )) {
+ lvds_codec->timings.input_bus_flags = val ?
+ DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE :
+ DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE;
+ }
+
/*
* The panel_bridge bridge is attached to the panel's of_node,
* but we need a bridge attached to our of_node for our user
* to look up.
*/
lvds_codec->bridge.of_node = dev->of_node;
+ lvds_codec->bridge.timings = _codec->timings;
I do not understand how this will work. The only field that is set
is timings.input_bus_flags
but any user will see bridge.timings is set and will think this is all
timing info.
Maybe I just misses something obvious?
Is there anything else in those timings that should be set ? See
include/drm/drm_bridge.h around line 640
setup_time_ps/hold_time_ps/dual_link isn't supported by this driver,
so it
is 0 or false anyway, i.e. no change.
Just me being confused with display_timings. Patch looks good.
Reviewed-by: Sam Ravnborg
Ping me in a few days to apply it if there is no more feedback.
Ping I guess ... Laurent ?
Ping one more time ?
Re: [PATCH v8 3/8] dt-bindings: display: Add ingenic, jz4780-dw-hdmi DT Schema
On Tue, 23 Nov 2021 19:13:56 +0100, H. Nikolaus Schaller wrote: > From: Sam Ravnborg > > Add DT bindings for the hdmi driver for the Ingenic JZ4780 SoC. > Based on .txt binding from Zubair Lutfullah Kakakhel > > We also add generic ddc-i2c-bus to synopsys,dw-hdmi.yaml > > Signed-off-by: Sam Ravnborg > Signed-off-by: H. Nikolaus Schaller > Cc: Rob Herring > Cc: devicet...@vger.kernel.org > --- > .../display/bridge/ingenic,jz4780-hdmi.yaml | 76 +++ > .../display/bridge/synopsys,dw-hdmi.yaml | 3 + > 2 files changed, 79 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/display/bridge/ingenic,jz4780-hdmi.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: ./Documentation/devicetree/bindings/display/bridge/ingenic,jz4780-hdmi.yaml:36:5: [warning] wrong indentation: expected 2 but found 4 (indentation) dtschema/dtc warnings/errors: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/bridge/ingenic,jz4780-hdmi.yaml: 'unevaluatedPropertes' is not one of ['$id', '$schema', 'title', 'description', 'examples', 'required', 'allOf', 'anyOf', 'oneOf', 'definitions', '$defs', 'additionalProperties', 'dependencies', 'dependentRequired', 'dependentSchemas', 'patternProperties', 'properties', 'if', 'then', 'else', 'unevaluatedProperties', 'deprecated', 'maintainers', 'select'] from schema $id: http://devicetree.org/meta-schemas/base.yaml# /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/bridge/ingenic,jz4780-hdmi.yaml: 'oneOf' conditional failed, one must be fixed: 'unevaluatedProperties' is a required property 'additionalProperties' is a required property hint: A schema with a "$ref" to another schema either can define all properties used and use "additionalProperties" or can use "unevaluatedProperties" from schema $id: http://devicetree.org/meta-schemas/base.yaml# Unknown file referenced: [Errno 2] No such file or directory: '/usr/local/lib/python3.8/dist-packages/dtschema/schemas/bridge/bridge/synopsys,dw-hdmi.yaml' xargs: dt-doc-validate: exited with status 255; aborting /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/bridge/ingenic,jz4780-hdmi.yaml: ignoring, error in schema: warning: no schema found in file: ./Documentation/devicetree/bindings/display/bridge/ingenic,jz4780-hdmi.yaml Documentation/devicetree/bindings/display/bridge/ingenic,jz4780-hdmi.example.dts:19:18: fatal error: dt-bindings/clock/jz4780-cgu.h: No such file or directory 19 | #include | ^~~~ compilation terminated. make[1]: *** [scripts/Makefile.lib:373: Documentation/devicetree/bindings/display/bridge/ingenic,jz4780-hdmi.example.dt.yaml] Error 1 make[1]: *** Waiting for unfinished jobs make: *** [Makefile:1413: dt_binding_check] Error 2 doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/1558736 This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
Re: [PATCH] drm: rcar-du: add modifiers support
Hello Daniel Thanks for the summary of the discussion. On 2021/11/18 22:02, Daniel Stone wrote: Hi all, Thanks for this Laurent. Esaki-san, could you please CC dri-devel@ on discussions like this? I'm sorry. I will check using get_maintainer.pl next time. On Thu, 18 Nov 2021 at 12:32, Laurent Pinchart wrote: On Sat, May 11, 2019 at 09:10:27PM +0300, Laurent Pinchart wrote: On Thu, May 09, 2019 at 06:25:19PM +0900, Esaki Tomohito wrote: Weston compositor (v5.0.0 or later) uses the DRM API to get the supported modifiers and determines if the sprite plane can be used by comparing the modifiers with the client specified modifier. In currently driver, since the weston doesn't know supported modifiers, that cannot determine if the received dmabuf can be passed through to sprite plane. Since there are R-Car GPU which support linear modifier, the sprite plane cannot be used in a compositor similar to the weston if client specify linear modifier. I don't think the right solution is to expose the linear modifier from all drivers that don't otherwise support modifiers. We should instead fix it either in Weston, and treat drivers that don't support the modifiers API as supporting the linear modifier only, or in the DRM/KMS core by reporting the linear modifier for drivers that don't explicitly support modifiers. I've been pointed to https://gitlab.freedesktop.org/wlroots/wlroots/-/merge_requests/3350#note_1161827, and we had a discussion on the #dri-devel IRC channel today on this topic. It turns out I was wrong, not specifying modifiers in userspace is different than specifying a linear modifier. This is true for some legacy drivers only (e.g. radeon) that pre-date the modifiers API, and which select a tiling format internally based on some heuristics. I still don't like this patch though, as it would need to be replicated in most drivers. It would be better if we could handle this in the DRM core. Daniel kindly offered to summarize the IRC discussion in a reply to this e-mail. Just quickly, I believe the check for the linear modifier in fb_create is unnecessary, as this should already be checked in the core through format_mod_supported(). There is indeed a difference between LINEAR and INVALID. Linear is an explicit declaration of the layout; INVALID (i.e. no modifier) means 'I don't know what this is, so you should guess'. Guessing is obviously not reliable, so Weston only passes buffers with no modifier to KMS in two cases. The first case is when we allocate a dumb buffer and the driver does not support modifiers; this is safe since it's the same driver. The second case is when either the GPU driver or KMS driver do not support modifiers and we allocate a buffer via GBM with USE_SCANOUT; in this case, it is GBM's responsibility to select the 'right' layout. We will never create a DRM framebuffer with no modifiers when the original buffer comes from a client. If the client does not support modifiers but the KMS driver does, then we do not know that the client has allocated a suitable layout, so this is not safe. If the client does explicitly declare a modifier but the KMS driver does not support modifiers, then we also do not know that this is safe to use. So unless both sides (client/GPU and KMS) support modifiers, we do not do direct scanout from client buffers. This patch would enable this usecase by declaring support for the linear modifier from KMS; when used with a PVR driver which explicitly declares the linear modifier, we know it is safe to pass that client buffer to KMS. Laurent's concern is that the DRM core should handle this rather than open-coding in every driver, which I agree with. Some drivers (e.g. radeon, maybe legacy NV?) do not support modifiers, and _also_ do magic inference of the actual layout of the underlying buffer. However, these drivers are legacy and we do not accept any new addition of inferring layout without modifiers. I think the best way forward here is: - add a new mode_config.cannot_support_modifiers flag, and enable this in radeon (plus any other drivers in the same boat) - change drm_universal_plane_init() to advertise the LINEAR modifier when NULL is passed as the modifier list (including installing a default .format_mod_supported hook) - remove the mode_config.allow_fb_modifiers hook and always advertise modifier support, unless mode_config.cannot_support_modifiers is set FWIW, the effective modifier API and also valid usage is documented here, which should be finished and merged shortly: https://lore.kernel.org/dri-devel/20210905122742.86029-1-dani...@collabora.com/ Cheers, Daniel -- Best Regards Tomohito Esaki
[Bug 203439] amdgpu: [REG 4.20 -> 5.0] Brightness minimum level is too high
https://bugzilla.kernel.org/show_bug.cgi?id=203439 Anish Sapkota (sapkotaanish...@gmail.com) changed: What|Removed |Added CC||sapkotaanish...@gmail.com --- Comment #6 from Anish Sapkota (sapkotaanish...@gmail.com) --- I am still facing this problem in Acer Aspire 5. Are there any updates to it? -- You may reply to this email to add a comment. You are receiving this mail because: You are watching the assignee of the bug.
linux-next: manual merge of the drm-intel-gt tree with the drm-intel tree
Hi all,
Today's linux-next merge of the drm-intel-gt tree got a conflict in:
drivers/gpu/drm/i915/i915_pci.c
between commit:
3c542cfa8266 ("drm/i915/dg2: Tile 4 plane format support")
from the drm-intel tree and commit:
a5b7ef27da60 ("drm/i915: Add struct to hold IP version")
from the drm-intel-gt tree.
I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging. You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.
--
Cheers,
Stephen Rothwell
diff --cc drivers/gpu/drm/i915/i915_pci.c
index 69b8029da6b6,5e6795853dc3..
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@@ -1042,9 -1030,8 +1042,9 @@@ static const struct intel_device_info d
XE_HPM_FEATURES,
XE_LPD_FEATURES,
DGFX_FEATURES,
- .graphics_rel = 55,
- .media_rel = 55,
+ .graphics.rel = 55,
+ .media.rel = 55,
+ .has_4tile = 1,
PLATFORM(INTEL_DG2),
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) |
pgpLJH1SavfBi.pgp
Description: OpenPGP digital signature
Re: [PATCH v2 12/63] thermal: intel: int340x_thermal: Use struct_group() for memcpy() region
On Tue, 2021-11-23 at 14:19 +0100, Rafael J. Wysocki wrote:
> On Wed, Aug 18, 2021 at 8:08 AM Kees Cook
> wrote:
> >
> > In preparation for FORTIFY_SOURCE performing compile-time and run-
> > time
> > field bounds checking for memcpy(), avoid intentionally writing
> > across
> > neighboring fields.
> >
> > Use struct_group() in struct art around members weight, and ac[0-
> > 9]_max,
> > so they can be referenced together. This will allow memcpy() and
> > sizeof()
> > to more easily reason about sizes, improve readability, and avoid
> > future
> > warnings about writing beyond the end of weight.
> >
> > "pahole" shows no size nor member offset changes to struct art.
> > "objdump -d" shows no meaningful object code changes (i.e. only
> > source
> > line number induced differences).
> >
> > Cc: Zhang Rui
> > Cc: Daniel Lezcano
> > Cc: Amit Kucheria
> > Cc: linux...@vger.kernel.org
> > Signed-off-by: Kees Cook
>
> Rui, Srinivas, any comments here?
Looks good.
Reviewed-by: Srinivas Pandruvada
Thanks,
Srinivas
>
> > ---
> > .../intel/int340x_thermal/acpi_thermal_rel.c | 5 +-
> > .../intel/int340x_thermal/acpi_thermal_rel.h | 48 ++---
> > --
> > 2 files changed, 29 insertions(+), 24 deletions(-)
> >
> > diff --git a/drivers/thermal/intel/int340x_thermal/acpi_thermal_rel.c
> > b/drivers/thermal/intel/int340x_thermal/acpi_thermal_rel.c
> > index a478cff8162a..e90690a234c4 100644
> > --- a/drivers/thermal/intel/int340x_thermal/acpi_thermal_rel.c
> > +++ b/drivers/thermal/intel/int340x_thermal/acpi_thermal_rel.c
> > @@ -250,8 +250,9 @@ static int fill_art(char __user *ubuf)
> > get_single_name(arts[i].source,
> > art_user[i].source_device);
> > get_single_name(arts[i].target,
> > art_user[i].target_device);
> > /* copy the rest int data in addition to source and
> > target */
> > - memcpy(_user[i].weight, [i].weight,
> > - sizeof(u64) * (ACPI_NR_ART_ELEMENTS - 2));
> > + BUILD_BUG_ON(sizeof(art_user[i].data) !=
> > + sizeof(u64) * (ACPI_NR_ART_ELEMENTS -
> > 2));
> > + memcpy(_user[i].data, [i].data,
> > sizeof(art_user[i].data));
> > }
> >
> > if (copy_to_user(ubuf, art_user, art_len))
> > diff --git a/drivers/thermal/intel/int340x_thermal/acpi_thermal_rel.h
> > b/drivers/thermal/intel/int340x_thermal/acpi_thermal_rel.h
> > index 58822575fd54..78d942477035 100644
> > --- a/drivers/thermal/intel/int340x_thermal/acpi_thermal_rel.h
> > +++ b/drivers/thermal/intel/int340x_thermal/acpi_thermal_rel.h
> > @@ -17,17 +17,19 @@
> > struct art {
> > acpi_handle source;
> > acpi_handle target;
> > - u64 weight;
> > - u64 ac0_max;
> > - u64 ac1_max;
> > - u64 ac2_max;
> > - u64 ac3_max;
> > - u64 ac4_max;
> > - u64 ac5_max;
> > - u64 ac6_max;
> > - u64 ac7_max;
> > - u64 ac8_max;
> > - u64 ac9_max;
> > + struct_group(data,
> > + u64 weight;
> > + u64 ac0_max;
> > + u64 ac1_max;
> > + u64 ac2_max;
> > + u64 ac3_max;
> > + u64 ac4_max;
> > + u64 ac5_max;
> > + u64 ac6_max;
> > + u64 ac7_max;
> > + u64 ac8_max;
> > + u64 ac9_max;
> > + );
> > } __packed;
> >
> > struct trt {
> > @@ -47,17 +49,19 @@ union art_object {
> > struct {
> > char source_device[8]; /* ACPI single name */
> > char target_device[8]; /* ACPI single name */
> > - u64 weight;
> > - u64 ac0_max_level;
> > - u64 ac1_max_level;
> > - u64 ac2_max_level;
> > - u64 ac3_max_level;
> > - u64 ac4_max_level;
> > - u64 ac5_max_level;
> > - u64 ac6_max_level;
> > - u64 ac7_max_level;
> > - u64 ac8_max_level;
> > - u64 ac9_max_level;
> > + struct_group(data,
> > + u64 weight;
> > + u64 ac0_max_level;
> > + u64 ac1_max_level;
> > + u64 ac2_max_level;
> > + u64 ac3_max_level;
> > + u64 ac4_max_level;
> > + u64 ac5_max_level;
> > + u64 ac6_max_level;
> > + u64 ac7_max_level;
> > + u64 ac8_max_level;
> > + u64 ac9_max_level;
> > + );
> > };
> > u64 __data[ACPI_NR_ART_ELEMENTS];
> > };
> > --
> > 2.30.2
> >
Re: [PATCH v2 4/6] drm/msm/a6xx: Capture gmu log in devcoredump
On Tue 23 Nov 13:17 PST 2021, Akhil P Oommen wrote:
> Capture gmu log in coredump to enhance debugging.
>
> Signed-off-by: Akhil P Oommen
> ---
>
> Changes in v2:
> - Fix kernel test robot's warning about size_t's format specifier
>
> drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 41
> +
> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +-
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 ++
> 3 files changed, 44 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
> b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
> index e8f65cd..e6f5571 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
> @@ -42,6 +42,8 @@ struct a6xx_gpu_state {
> struct a6xx_gpu_state_obj *cx_debugbus;
> int nr_cx_debugbus;
>
> + struct msm_gpu_state_bo *gmu_log;
> +
> struct list_head objs;
> };
>
> @@ -800,6 +802,30 @@ static void a6xx_get_gmu_registers(struct msm_gpu *gpu,
> _state->gmu_registers[2], false);
> }
>
> +static void a6xx_get_gmu_log(struct msm_gpu *gpu,
> + struct a6xx_gpu_state *a6xx_state)
> +{
> + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
> + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
> + struct a6xx_gmu *gmu = _gpu->gmu;
> + struct msm_gpu_state_bo *gmu_log;
> +
> + gmu_log = state_kcalloc(a6xx_state,
> + 1, sizeof(*a6xx_state->gmu_log));
This line isn't even 80 chars long, so I see no reason to wrap it and if
you ran checkpatch --strict on this patch it would complain about how
you indent that second line as well.
It would also look better with sizeof(*gmu_log), even though they should
have the same size today...
> + if (!gmu_log)
> + return;
> +
> + gmu_log->iova = gmu->log.iova;
> + gmu_log->size = gmu->log.size;
> + gmu_log->data = kvzalloc(gmu_log->size, GFP_KERNEL);
> + if (!gmu_log->data)
> + return;
> +
> + memcpy(gmu_log->data, gmu->log.virt, gmu->log.size);
> +
> + a6xx_state->gmu_log = gmu_log;
> +}
> +
> #define A6XX_GBIF_REGLIST_SIZE 1
> static void a6xx_get_registers(struct msm_gpu *gpu,
> struct a6xx_gpu_state *a6xx_state,
> @@ -937,6 +963,8 @@ struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu
> *gpu)
>
> a6xx_get_gmu_registers(gpu, a6xx_state);
>
> + a6xx_get_gmu_log(gpu, a6xx_state);
> +
> /* If GX isn't on the rest of the data isn't going to be accessible */
> if (!a6xx_gmu_gx_is_on(_gpu->gmu))
> return _state->base;
> @@ -978,6 +1006,9 @@ static void a6xx_gpu_state_destroy(struct kref *kref)
> struct a6xx_gpu_state *a6xx_state = container_of(state,
> struct a6xx_gpu_state, base);
>
> + if (a6xx_state->gmu_log && a6xx_state->gmu_log->data)
> + kvfree(a6xx_state->gmu_log->data);
> +
> list_for_each_entry_safe(obj, tmp, _state->objs, node)
> kfree(obj);
>
> @@ -1191,6 +1222,16 @@ void a6xx_show(struct msm_gpu *gpu, struct
> msm_gpu_state *state,
>
> adreno_show(gpu, state, p);
>
> + drm_puts(p, "gmu-log:\n");
> + if (a6xx_state->gmu_log) {
> + struct msm_gpu_state_bo *gmu_log = a6xx_state->gmu_log;
> +
> + drm_printf(p, "iova: 0x%016llx\n", gmu_log->iova);
> + drm_printf(p, "size: %zu\n", gmu_log->size);
> + adreno_show_object(p, _log->data, gmu_log->size,
> + _log->encoded);
> + }
> +
> drm_puts(p, "registers:\n");
> for (i = 0; i < a6xx_state->nr_registers; i++) {
> struct a6xx_gpu_state_obj *obj = _state->registers[i];
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> index 1539b8e..b43346e 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> @@ -638,7 +638,7 @@ static char *adreno_gpu_ascii85_encode(u32 *src, size_t
> len)
> }
>
> /* len is expected to be in bytes */
> -static void adreno_show_object(struct drm_printer *p, void **ptr, int len,
> +void adreno_show_object(struct drm_printer *p, void **ptr, int len,
> bool *encoded)
Please indent your broken lines by the ( on the line before.
Regards,
Bjorn
> {
> if (!*ptr || !len)
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index 225c277..6762308 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -306,6 +306,8 @@ void adreno_gpu_state_destroy(struct msm_gpu_state
> *state);
>
> int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state);
> int adreno_gpu_state_put(struct msm_gpu_state *state);
> +void adreno_show_object(struct drm_printer *p, void **ptr, int len,
> + bool *encoded);
>
> /*
> * Common helper
Re: [PATCH v3 4/6] drm: implement a method to free unused pages
On 18/11/21 12:32 am, Matthew Auld wrote:
> On 16/11/2021 20:18, Arunpravin wrote:
>> On contiguous allocation, we round up the size
>> to the *next* power of 2, implement a function
>> to free the unused pages after the newly allocate block.
>>
>> v2(Matthew Auld):
>>- replace function name 'drm_buddy_free_unused_pages' with
>> drm_buddy_block_trim
>>- replace input argument name 'actual_size' with 'new_size'
>>- add more validation checks for input arguments
>>- add overlaps check to avoid needless searching and splitting
>>- merged the below patch to see the feature in action
>> - add free unused pages support to i915 driver
>>- lock drm_buddy_block_trim() function as it calls mark_free/mark_split
>> are all globally visible
>>
>> Signed-off-by: Arunpravin
>> ---
>> drivers/gpu/drm/drm_buddy.c | 108 ++
>> drivers/gpu/drm/i915/i915_ttm_buddy_manager.c | 10 ++
>> include/drm/drm_buddy.h | 4 +
>> 3 files changed, 122 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/drm_buddy.c b/drivers/gpu/drm/drm_buddy.c
>> index 0a9db2981188..943fe2ad27bf 100644
>> --- a/drivers/gpu/drm/drm_buddy.c
>> +++ b/drivers/gpu/drm/drm_buddy.c
>> @@ -284,6 +284,114 @@ static inline bool contains(u64 s1, u64 e1, u64 s2,
>> u64 e2)
>> return s1 <= s2 && e1 >= e2;
>> }
>>
>> +/**
>> + * drm_buddy_block_trim - free unused pages
>> + *
>> + * @mm: DRM buddy manager
>> + * @new_size: original size requested
>> + * @blocks: output list head to add allocated blocks
>> + *
>> + * For contiguous allocation, we round up the size to the nearest
>> + * power of two value, drivers consume *actual* size, so remaining
>> + * portions are unused and it can be freed.
>> + *
>> + * Returns:
>> + * 0 on success, error code on failure.
>> + */
>> +int drm_buddy_block_trim(struct drm_buddy_mm *mm,
>> + u64 new_size,
>> + struct list_head *blocks)
>> +{
>> +struct drm_buddy_block *block;
>> +struct drm_buddy_block *buddy;
>> +u64 new_start;
>> +u64 new_end;
>> +LIST_HEAD(dfs);
>> +u64 count = 0;
>> +int err;
>> +
>> +if (!list_is_singular(blocks))
>> +return -EINVAL;
>> +
>> +block = list_first_entry(blocks,
>> + struct drm_buddy_block,
>> + link);
>> +
>> +if (!drm_buddy_block_is_allocated(block))
>> +return -EINVAL;
>> +
>> +if (new_size > drm_buddy_block_size(mm, block))
>> +return -EINVAL;
>> +
>> +if (!new_size && !IS_ALIGNED(new_size, mm->chunk_size))
>> +return -EINVAL;
>> +
>> +if (new_size == drm_buddy_block_size(mm, block))
>> +return 0;
>> +
>> +list_del(>link);
>> +
>> +new_start = drm_buddy_block_offset(block);
>> +new_end = new_start + new_size - 1;
>> +
>> +mark_free(mm, block);
>> +
>> +list_add(>tmp_link, );
>> +
>> +do {
>> +u64 block_start;
>> +u64 block_end;
>> +
>> +block = list_first_entry_or_null(,
>> + struct drm_buddy_block,
>> + tmp_link);
>> +if (!block)
>> +break;
>> +
>> +list_del(>tmp_link);
>> +
>> +if (count == new_size)
>> +return 0;
>> +
>> +block_start = drm_buddy_block_offset(block);
>> +block_end = block_start + drm_buddy_block_size(mm, block) - 1;
>> +
>> +if (!overlaps(new_start, new_end, block_start, block_end))
>> +continue;
>> +
>> +if (contains(new_start, new_end, block_start, block_end)) {
>> +BUG_ON(!drm_buddy_block_is_free(block));
>> +
>> +/* Allocate only required blocks */
>> +mark_allocated(block);
>> +mm->avail -= drm_buddy_block_size(mm, block);
>> +list_add_tail(>link, blocks);
>> +count += drm_buddy_block_size(mm, block);
>> +continue;
>> +}
>> +
>> +if (!drm_buddy_block_is_split(block)) {
>
> Should always be true, right? But I guess depends if we want to re-use
> this for generic range allocation...
yes, since we re-use this for generic range allocation I think we can
keep this check
>
>> +err = split_block(mm, block);
>> +if (unlikely(err))
>> +goto err_undo;
>> +}
>> +
>> +list_add(>right->tmp_link, );
>> +list_add(>left->tmp_link, );
>> +} while (1);
>> +
>> +return -ENOSPC;
>> +
>> +err_undo:
>> +buddy = get_buddy(block);
>> +if (buddy &&
>> +(drm_buddy_block_is_free(block) &&
>> + drm_buddy_block_is_free(buddy)))
>> +__drm_buddy_free(mm, block);
>> +return err;
>
>
Re: [PATCH v3 2/6] drm: improve drm_buddy_alloc function
On 18/11/21 12:09 am, Matthew Auld wrote:
> On 16/11/2021 20:18, Arunpravin wrote:
>> - Make drm_buddy_alloc a single function to handle
>>range allocation and non-range allocation demands
>>
>> - Implemented a new function alloc_range() which allocates
>>the requested power-of-two block comply with range limitations
>>
>> - Moved order computation and memory alignment logic from
>>i915 driver to drm buddy
>>
>> v2:
>>merged below changes to keep the build unbroken
>> - drm_buddy_alloc_range() becomes obsolete and may be removed
>> - enable ttm range allocation (fpfn / lpfn) support in i915 driver
>> - apply enhanced drm_buddy_alloc() function to i915 driver
>>
>> v3(Matthew Auld):
>>- Fix alignment issues and remove unnecessary list_empty check
>>- add more validation checks for input arguments
>>- make alloc_range() block allocations as bottom-up
>>- optimize order computation logic
>>- replace uint64_t with u64, which is preferred in the kernel
>>
>> Signed-off-by: Arunpravin
>> ---
>> drivers/gpu/drm/drm_buddy.c | 259 ++
>> drivers/gpu/drm/i915/i915_ttm_buddy_manager.c | 69 ++---
>> drivers/gpu/drm/i915/i915_ttm_buddy_manager.h | 2 +
>> include/drm/drm_buddy.h | 22 +-
>> 4 files changed, 203 insertions(+), 149 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/drm_buddy.c b/drivers/gpu/drm/drm_buddy.c
>> index 39eb1d224bec..c9b18a29f8d1 100644
>> --- a/drivers/gpu/drm/drm_buddy.c
>> +++ b/drivers/gpu/drm/drm_buddy.c
>> @@ -274,63 +274,6 @@ void drm_buddy_free_list(struct drm_buddy_mm *mm,
>> struct list_head *objects)
>> }
>> EXPORT_SYMBOL(drm_buddy_free_list);
>>
>> -/**
>> - * drm_buddy_alloc - allocate power-of-two blocks
>> - *
>> - * @mm: DRM buddy manager to allocate from
>> - * @order: size of the allocation
>> - *
>> - * The order value here translates to:
>> - *
>> - * 0 = 2^0 * mm->chunk_size
>> - * 1 = 2^1 * mm->chunk_size
>> - * 2 = 2^2 * mm->chunk_size
>> - *
>> - * Returns:
>> - * allocated ptr to the _buddy_block on success
>> - */
>> -struct drm_buddy_block *
>> -drm_buddy_alloc(struct drm_buddy_mm *mm, unsigned int order)
>> -{
>> -struct drm_buddy_block *block = NULL;
>> -unsigned int i;
>> -int err;
>> -
>> -for (i = order; i <= mm->max_order; ++i) {
>> -block = list_first_entry_or_null(>free_list[i],
>> - struct drm_buddy_block,
>> - link);
>> -if (block)
>> -break;
>> -}
>> -
>> -if (!block)
>> -return ERR_PTR(-ENOSPC);
>> -
>> -BUG_ON(!drm_buddy_block_is_free(block));
>> -
>> -while (i != order) {
>> -err = split_block(mm, block);
>> -if (unlikely(err))
>> -goto out_free;
>> -
>> -/* Go low */
>> -block = block->left;
>> -i--;
>> -}
>> -
>> -mark_allocated(block);
>> -mm->avail -= drm_buddy_block_size(mm, block);
>> -kmemleak_update_trace(block);
>> -return block;
>> -
>> -out_free:
>> -if (i != order)
>> -__drm_buddy_free(mm, block);
>> -return ERR_PTR(err);
>> -}
>> -EXPORT_SYMBOL(drm_buddy_alloc);
>> -
>> static inline bool overlaps(u64 s1, u64 e1, u64 s2, u64 e2)
>> {
>> return s1 <= e2 && e1 >= s2;
>> @@ -341,52 +284,22 @@ static inline bool contains(u64 s1, u64 e1, u64 s2,
>> u64 e2)
>> return s1 <= s2 && e1 >= e2;
>> }
>>
>> -/**
>> - * drm_buddy_alloc_range - allocate range
>> - *
>> - * @mm: DRM buddy manager to allocate from
>> - * @blocks: output list head to add allocated blocks
>> - * @start: start of the allowed range for this block
>> - * @size: size of the allocation
>> - *
>> - * Intended for pre-allocating portions of the address space, for example to
>> - * reserve a block for the initial framebuffer or similar, hence the
>> expectation
>> - * here is that drm_buddy_alloc() is still the main vehicle for
>> - * allocations, so if that's not the case then the drm_mm range allocator is
>> - * probably a much better fit, and so you should probably go use that
>> instead.
>> - *
>> - * Note that it's safe to chain together multiple alloc_ranges
>> - * with the same blocks list
>> - *
>> - * Returns:
>> - * 0 on success, error code on failure.
>> - */
>> -int drm_buddy_alloc_range(struct drm_buddy_mm *mm,
>> - struct list_head *blocks,
>> - u64 start, u64 size)
>> +static struct drm_buddy_block *
>> +alloc_range(struct drm_buddy_mm *mm,
>> +u64 start, u64 end,
>> +unsigned int order)
>> {
>> struct drm_buddy_block *block;
>> struct drm_buddy_block *buddy;
>> -LIST_HEAD(allocated);
>> LIST_HEAD(dfs);
>> -u64 end;
>> int err;
>> int i;
>>
>> -if (size < mm->chunk_size)
>> -return -EINVAL;
>> -
>> -if (!IS_ALIGNED(size
Re: [PATCH v2 6/6] drm/msm/a6xx: Add a few gmu buffers to coredump
On 11/24/2021 2:47 AM, Akhil P Oommen wrote:
Add a few more gmu buffers to coredump to help debug gmu
issues.
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 157 +++-
1 file changed, 108 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
index e6f5571..0cb6551 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
@@ -13,12 +13,22 @@ struct a6xx_gpu_state_obj {
u32 *data;
};
+struct a6xx_gmu_state {
+ struct a6xx_gpu_state_obj *registers;
+ int nr_registers;
+
+ struct msm_gpu_state_bo *log_bo;
+
+ struct msm_gpu_state_bo *hfi_bo;
+
+ struct msm_gpu_state_bo *debug_bo;
+
+ struct msm_gpu_state_bo *mem_bin_bo[2];
+};
+
struct a6xx_gpu_state {
struct msm_gpu_state base;
- struct a6xx_gpu_state_obj *gmu_registers;
- int nr_gmu_registers;
-
struct a6xx_gpu_state_obj *registers;
int nr_registers;
@@ -42,7 +52,7 @@ struct a6xx_gpu_state {
struct a6xx_gpu_state_obj *cx_debugbus;
int nr_cx_debugbus;
- struct msm_gpu_state_bo *gmu_log;
+ struct a6xx_gmu_state gmu_state;
struct list_head objs;
};
@@ -777,20 +787,21 @@ static void a6xx_get_gmu_registers(struct msm_gpu *gpu,
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
+ struct a6xx_gmu_state *gmu_state = _state->gmu_state;
- a6xx_state->gmu_registers = state_kcalloc(a6xx_state,
- 2, sizeof(*a6xx_state->gmu_registers));
+ gmu_state->registers = state_kcalloc(a6xx_state,
+ 2, sizeof(*gmu_state->registers));
- if (!a6xx_state->gmu_registers)
+ if (!gmu_state->registers)
return;
- a6xx_state->nr_gmu_registers = 2;
+ gmu_state->nr_registers = 2;
/* Get the CX GMU registers from AHB */
_a6xx_get_gmu_registers(gpu, a6xx_state, _gmu_reglist[0],
- _state->gmu_registers[0], false);
+ _state->registers[0], false);
_a6xx_get_gmu_registers(gpu, a6xx_state, _gmu_reglist[1],
- _state->gmu_registers[1], true);
+ _state->registers[1], true);
if (!a6xx_gmu_gx_is_on(_gpu->gmu))
return;
@@ -799,31 +810,46 @@ static void a6xx_get_gmu_registers(struct msm_gpu *gpu,
gpu_write(gpu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);
_a6xx_get_gmu_registers(gpu, a6xx_state, _gmu_reglist[2],
- _state->gmu_registers[2], false);
+ _state->registers[2], false);
+
+ gmu_state->nr_registers = 3;
This is not required after rebasing on top of:
https://lore.kernel.org/all/20211103153049.1.Idfa574ccb529d17b69db3a1852e49b580132035c@changeid/
-Akhil.
}
-static void a6xx_get_gmu_log(struct msm_gpu *gpu,
+static void a6xx_get_gmu_bo(struct a6xx_gpu_state *a6xx_state,
+ struct a6xx_gmu_bo *gmu_bo, struct msm_gpu_state_bo **dest_bo)
+{
+ struct msm_gpu_state_bo *bo;
+
+ bo = state_kcalloc(a6xx_state, 1, sizeof(**dest_bo));
+ if (!bo)
+ return;
+
+ bo->iova = gmu_bo->iova;
+ bo->size = gmu_bo->size;
+ bo->data = kvzalloc(bo->size, GFP_KERNEL);
+ if (!bo->data)
+ return;
+
+ memcpy(bo->data, gmu_bo->virt, gmu_bo->size);
+
+ *dest_bo = bo;
+}
+
+static void a6xx_get_gmu_state(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state)
{
+ struct a6xx_gmu_state *gmu_state = _state->gmu_state;
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
struct a6xx_gmu *gmu = _gpu->gmu;
- struct msm_gpu_state_bo *gmu_log;
- gmu_log = state_kcalloc(a6xx_state,
- 1, sizeof(*a6xx_state->gmu_log));
- if (!gmu_log)
- return;
+ a6xx_get_gmu_registers(gpu, a6xx_state);
- gmu_log->iova = gmu->log.iova;
- gmu_log->size = gmu->log.size;
- gmu_log->data = kvzalloc(gmu_log->size, GFP_KERNEL);
- if (!gmu_log->data)
- return;
+ a6xx_get_gmu_bo(a6xx_state, >log, _state->log_bo);
- memcpy(gmu_log->data, gmu->log.virt, gmu->log.size);
+ a6xx_get_gmu_bo(a6xx_state, >hfi, _state->hfi_bo);
- a6xx_state->gmu_log = gmu_log;
+ a6xx_get_gmu_bo(a6xx_state, >debug, _state->debug_bo);
}
#define A6XX_GBIF_REGLIST_SIZE 1
@@ -961,9 +987,7 @@ struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu
*gpu)
/* Get the generic state from the adreno core */
adreno_gpu_state_get(gpu, _state->base);
- a6xx_get_gmu_registers(gpu, a6xx_state);
-
- a6xx_get_gmu_log(gpu, a6xx_state);
+ a6xx_get_gmu_state(gpu, a6xx_state);
/* If GX isn't on the rest of the data isn't going
[PATCH v2 6/6] drm/msm/a6xx: Add a few gmu buffers to coredump
Add a few more gmu buffers to coredump to help debug gmu
issues.
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 157 +++-
1 file changed, 108 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
index e6f5571..0cb6551 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
@@ -13,12 +13,22 @@ struct a6xx_gpu_state_obj {
u32 *data;
};
+struct a6xx_gmu_state {
+ struct a6xx_gpu_state_obj *registers;
+ int nr_registers;
+
+ struct msm_gpu_state_bo *log_bo;
+
+ struct msm_gpu_state_bo *hfi_bo;
+
+ struct msm_gpu_state_bo *debug_bo;
+
+ struct msm_gpu_state_bo *mem_bin_bo[2];
+};
+
struct a6xx_gpu_state {
struct msm_gpu_state base;
- struct a6xx_gpu_state_obj *gmu_registers;
- int nr_gmu_registers;
-
struct a6xx_gpu_state_obj *registers;
int nr_registers;
@@ -42,7 +52,7 @@ struct a6xx_gpu_state {
struct a6xx_gpu_state_obj *cx_debugbus;
int nr_cx_debugbus;
- struct msm_gpu_state_bo *gmu_log;
+ struct a6xx_gmu_state gmu_state;
struct list_head objs;
};
@@ -777,20 +787,21 @@ static void a6xx_get_gmu_registers(struct msm_gpu *gpu,
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
+ struct a6xx_gmu_state *gmu_state = _state->gmu_state;
- a6xx_state->gmu_registers = state_kcalloc(a6xx_state,
- 2, sizeof(*a6xx_state->gmu_registers));
+ gmu_state->registers = state_kcalloc(a6xx_state,
+ 2, sizeof(*gmu_state->registers));
- if (!a6xx_state->gmu_registers)
+ if (!gmu_state->registers)
return;
- a6xx_state->nr_gmu_registers = 2;
+ gmu_state->nr_registers = 2;
/* Get the CX GMU registers from AHB */
_a6xx_get_gmu_registers(gpu, a6xx_state, _gmu_reglist[0],
- _state->gmu_registers[0], false);
+ _state->registers[0], false);
_a6xx_get_gmu_registers(gpu, a6xx_state, _gmu_reglist[1],
- _state->gmu_registers[1], true);
+ _state->registers[1], true);
if (!a6xx_gmu_gx_is_on(_gpu->gmu))
return;
@@ -799,31 +810,46 @@ static void a6xx_get_gmu_registers(struct msm_gpu *gpu,
gpu_write(gpu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);
_a6xx_get_gmu_registers(gpu, a6xx_state, _gmu_reglist[2],
- _state->gmu_registers[2], false);
+ _state->registers[2], false);
+
+ gmu_state->nr_registers = 3;
}
-static void a6xx_get_gmu_log(struct msm_gpu *gpu,
+static void a6xx_get_gmu_bo(struct a6xx_gpu_state *a6xx_state,
+ struct a6xx_gmu_bo *gmu_bo, struct msm_gpu_state_bo **dest_bo)
+{
+ struct msm_gpu_state_bo *bo;
+
+ bo = state_kcalloc(a6xx_state, 1, sizeof(**dest_bo));
+ if (!bo)
+ return;
+
+ bo->iova = gmu_bo->iova;
+ bo->size = gmu_bo->size;
+ bo->data = kvzalloc(bo->size, GFP_KERNEL);
+ if (!bo->data)
+ return;
+
+ memcpy(bo->data, gmu_bo->virt, gmu_bo->size);
+
+ *dest_bo = bo;
+}
+
+static void a6xx_get_gmu_state(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state)
{
+ struct a6xx_gmu_state *gmu_state = _state->gmu_state;
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
struct a6xx_gmu *gmu = _gpu->gmu;
- struct msm_gpu_state_bo *gmu_log;
- gmu_log = state_kcalloc(a6xx_state,
- 1, sizeof(*a6xx_state->gmu_log));
- if (!gmu_log)
- return;
+ a6xx_get_gmu_registers(gpu, a6xx_state);
- gmu_log->iova = gmu->log.iova;
- gmu_log->size = gmu->log.size;
- gmu_log->data = kvzalloc(gmu_log->size, GFP_KERNEL);
- if (!gmu_log->data)
- return;
+ a6xx_get_gmu_bo(a6xx_state, >log, _state->log_bo);
- memcpy(gmu_log->data, gmu->log.virt, gmu->log.size);
+ a6xx_get_gmu_bo(a6xx_state, >hfi, _state->hfi_bo);
- a6xx_state->gmu_log = gmu_log;
+ a6xx_get_gmu_bo(a6xx_state, >debug, _state->debug_bo);
}
#define A6XX_GBIF_REGLIST_SIZE 1
@@ -961,9 +987,7 @@ struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu
*gpu)
/* Get the generic state from the adreno core */
adreno_gpu_state_get(gpu, _state->base);
- a6xx_get_gmu_registers(gpu, a6xx_state);
-
- a6xx_get_gmu_log(gpu, a6xx_state);
+ a6xx_get_gmu_state(gpu, a6xx_state);
/* If GX isn't on the rest of the data isn't going to be accessible */
if (!a6xx_gmu_gx_is_on(_gpu->gmu))
@@ -1005,9 +1029,16 @@ static void a6xx_gpu_state_destroy(struct kref *kref)
[PATCH v2 5/6] drm/msm: Add a module param to force coredump
Add a module param "force_gpu_coredump" to force coredump on relatively
harmless gpu hw errors.
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 33 ++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 38 +-
drivers/gpu/drm/msm/adreno/adreno_device.c | 4
3 files changed, 54 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index 5e2750e..1861e9a 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -14,6 +14,7 @@
#include "a5xx_gpu.h"
extern bool hang_debug;
+extern bool force_gpu_coredump;
static void a5xx_dump(struct msm_gpu *gpu);
#define GPU_PAS_ID 13
@@ -1237,11 +1238,6 @@ static void a5xx_fault_detect_irq(struct msm_gpu *gpu)
gpu_read(gpu, REG_A5XX_CP_IB1_BUFSZ),
gpu_read64(gpu, REG_A5XX_CP_IB2_BASE, REG_A5XX_CP_IB2_BASE_HI),
gpu_read(gpu, REG_A5XX_CP_IB2_BUFSZ));
-
- /* Turn off the hangcheck timer to keep it from bothering us */
- del_timer(>hangcheck_timer);
-
- kthread_queue_work(gpu->worker, >recover_work);
}
#define RBBM_ERROR_MASK \
@@ -1255,6 +1251,7 @@ static void a5xx_fault_detect_irq(struct msm_gpu *gpu)
static irqreturn_t a5xx_irq(struct msm_gpu *gpu)
{
u32 status = gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS);
+ bool coredump = false;
/*
* Clear all the interrupts except RBBM_AHB_ERROR - if we clear it
@@ -1264,20 +1261,30 @@ static irqreturn_t a5xx_irq(struct msm_gpu *gpu)
status & ~A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR);
/* Pass status to a5xx_rbbm_err_irq because we've already cleared it */
- if (status & RBBM_ERROR_MASK)
+ if (status & RBBM_ERROR_MASK) {
a5xx_rbbm_err_irq(gpu, status);
+ coredump |= force_gpu_coredump;
+ }
- if (status & A5XX_RBBM_INT_0_MASK_CP_HW_ERROR)
+ if (status & A5XX_RBBM_INT_0_MASK_CP_HW_ERROR) {
a5xx_cp_err_irq(gpu);
+ coredump |= force_gpu_coredump;
+ }
- if (status & A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT)
+ if (status & A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT) {
a5xx_fault_detect_irq(gpu);
+ coredump = true;
+ }
- if (status & A5XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS)
+ if (status & A5XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS) {
a5xx_uche_err_irq(gpu);
+ coredump |= force_gpu_coredump;
+ }
- if (status & A5XX_RBBM_INT_0_MASK_GPMU_VOLTAGE_DROOP)
+ if (status & A5XX_RBBM_INT_0_MASK_GPMU_VOLTAGE_DROOP) {
a5xx_gpmu_err_irq(gpu);
+ coredump |= force_gpu_coredump;
+ }
if (status & A5XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS) {
a5xx_preempt_trigger(gpu);
@@ -1287,6 +1294,12 @@ static irqreturn_t a5xx_irq(struct msm_gpu *gpu)
if (status & A5XX_RBBM_INT_0_MASK_CP_SW)
a5xx_preempt_irq(gpu);
+ if (coredump) {
+ /* Turn off the hangcheck timer to keep it from bothering us */
+ del_timer(>hangcheck_timer);
+ kthread_queue_work(gpu->worker, >recover_work);
+ }
+
return IRQ_HANDLED;
}
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 6c2edce..f96587f 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -15,6 +15,8 @@
#define GPU_PAS_ID 13
+extern bool force_gpu_coredump;
+
static inline bool _a6xx_check_idle(struct msm_gpu *gpu)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
@@ -1354,40 +1356,54 @@ static void a6xx_fault_detect_irq(struct msm_gpu *gpu)
gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE),
gpu_read64(gpu, REG_A6XX_CP_IB2_BASE, REG_A6XX_CP_IB2_BASE_HI),
gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE));
-
- /* Turn off the hangcheck timer to keep it from bothering us */
- del_timer(>hangcheck_timer);
-
- kthread_queue_work(gpu->worker, >recover_work);
}
static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
{
u32 status = gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS);
+ bool coredump = false;
gpu_write(gpu, REG_A6XX_RBBM_INT_CLEAR_CMD, status);
- if (status & A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT)
+ if (status & A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT) {
a6xx_fault_detect_irq(gpu);
+ coredump = true;
+ }
- if (status & A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR)
+ if (status & A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR) {
dev_err_ratelimited(>pdev->dev, "CP | AHB bus error\n");
+ coredump |= force_gpu_coredump;
+ }
- if (status & A6XX_RBBM_INT_0_MASK_CP_HW_ERROR)
+ if (status &
[PATCH v2 4/6] drm/msm/a6xx: Capture gmu log in devcoredump
Capture gmu log in coredump to enhance debugging.
Signed-off-by: Akhil P Oommen
---
Changes in v2:
- Fix kernel test robot's warning about size_t's format specifier
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 41 +
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +-
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 ++
3 files changed, 44 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
index e8f65cd..e6f5571 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
@@ -42,6 +42,8 @@ struct a6xx_gpu_state {
struct a6xx_gpu_state_obj *cx_debugbus;
int nr_cx_debugbus;
+ struct msm_gpu_state_bo *gmu_log;
+
struct list_head objs;
};
@@ -800,6 +802,30 @@ static void a6xx_get_gmu_registers(struct msm_gpu *gpu,
_state->gmu_registers[2], false);
}
+static void a6xx_get_gmu_log(struct msm_gpu *gpu,
+ struct a6xx_gpu_state *a6xx_state)
+{
+ struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
+ struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
+ struct a6xx_gmu *gmu = _gpu->gmu;
+ struct msm_gpu_state_bo *gmu_log;
+
+ gmu_log = state_kcalloc(a6xx_state,
+ 1, sizeof(*a6xx_state->gmu_log));
+ if (!gmu_log)
+ return;
+
+ gmu_log->iova = gmu->log.iova;
+ gmu_log->size = gmu->log.size;
+ gmu_log->data = kvzalloc(gmu_log->size, GFP_KERNEL);
+ if (!gmu_log->data)
+ return;
+
+ memcpy(gmu_log->data, gmu->log.virt, gmu->log.size);
+
+ a6xx_state->gmu_log = gmu_log;
+}
+
#define A6XX_GBIF_REGLIST_SIZE 1
static void a6xx_get_registers(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state,
@@ -937,6 +963,8 @@ struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu
*gpu)
a6xx_get_gmu_registers(gpu, a6xx_state);
+ a6xx_get_gmu_log(gpu, a6xx_state);
+
/* If GX isn't on the rest of the data isn't going to be accessible */
if (!a6xx_gmu_gx_is_on(_gpu->gmu))
return _state->base;
@@ -978,6 +1006,9 @@ static void a6xx_gpu_state_destroy(struct kref *kref)
struct a6xx_gpu_state *a6xx_state = container_of(state,
struct a6xx_gpu_state, base);
+ if (a6xx_state->gmu_log && a6xx_state->gmu_log->data)
+ kvfree(a6xx_state->gmu_log->data);
+
list_for_each_entry_safe(obj, tmp, _state->objs, node)
kfree(obj);
@@ -1191,6 +1222,16 @@ void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state
*state,
adreno_show(gpu, state, p);
+ drm_puts(p, "gmu-log:\n");
+ if (a6xx_state->gmu_log) {
+ struct msm_gpu_state_bo *gmu_log = a6xx_state->gmu_log;
+
+ drm_printf(p, "iova: 0x%016llx\n", gmu_log->iova);
+ drm_printf(p, "size: %zu\n", gmu_log->size);
+ adreno_show_object(p, _log->data, gmu_log->size,
+ _log->encoded);
+ }
+
drm_puts(p, "registers:\n");
for (i = 0; i < a6xx_state->nr_registers; i++) {
struct a6xx_gpu_state_obj *obj = _state->registers[i];
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 1539b8e..b43346e 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -638,7 +638,7 @@ static char *adreno_gpu_ascii85_encode(u32 *src, size_t len)
}
/* len is expected to be in bytes */
-static void adreno_show_object(struct drm_printer *p, void **ptr, int len,
+void adreno_show_object(struct drm_printer *p, void **ptr, int len,
bool *encoded)
{
if (!*ptr || !len)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 225c277..6762308 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -306,6 +306,8 @@ void adreno_gpu_state_destroy(struct msm_gpu_state *state);
int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state);
int adreno_gpu_state_put(struct msm_gpu_state *state);
+void adreno_show_object(struct drm_printer *p, void **ptr, int len,
+ bool *encoded);
/*
* Common helper function to initialize the default address space for arm-smmu
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation.
[PATCH v2 1/6] drm/msm: Increase gpu boost interval
Currently, we boost gpu freq after 25ms of inactivity. This regresses
some of the 30 fps usecases where the workload on gpu (at 33ms internval)
is very small which it can finish at the lowest OPP before the deadline.
Lets increase this inactivity threshold to 50ms (same as the current
devfreq interval) to fix this.
Signed-off-by: Akhil P Oommen
---
Changes in v2:
- Added patch (5) & (6) to this stack
drivers/gpu/drm/msm/msm_gpu_devfreq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_gpu_devfreq.c
b/drivers/gpu/drm/msm/msm_gpu_devfreq.c
index 84e98c0..5028f92 100644
--- a/drivers/gpu/drm/msm/msm_gpu_devfreq.c
+++ b/drivers/gpu/drm/msm/msm_gpu_devfreq.c
@@ -167,7 +167,7 @@ void msm_devfreq_active(struct msm_gpu *gpu)
* interval, then we won't meet the threshold of busyness for
* the governor to ramp up the freq.. so give some boost
*/
- if (idle_time > msm_devfreq_profile.polling_ms/2) {
+ if (idle_time > msm_devfreq_profile.polling_ms) {
target_freq *= 2;
}
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation.
[PATCH v2 3/6] drm/msm/a6xx: Fix smatch warning for gpu_scid
Fix the below smatch warning:
drivers/gpu/drm/msm/adreno/a6xx_gpu.c:1480 a6xx_llc_activate()
error: uninitialized symbol 'gpu_scid'.
Reported-by: Dan Carpenter
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index b7f11cd..6c2edce 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1411,17 +1411,24 @@ static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu)
{
struct adreno_gpu *adreno_gpu = _gpu->base;
struct msm_gpu *gpu = _gpu->base;
- u32 gpu_scid, cntl1_regval = 0;
+ u32 cntl1_regval = 0;
if (IS_ERR(a6xx_gpu->llc_mmio))
return;
if (!llcc_slice_activate(a6xx_gpu->llc_slice)) {
- gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice);
+ u32 gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice);
gpu_scid &= 0x1f;
cntl1_regval = (gpu_scid << 0) | (gpu_scid << 5) | (gpu_scid <<
10) |
(gpu_scid << 15) | (gpu_scid << 20);
+
+ /* On A660, the SCID programming for UCHE traffic is done in
+* A6XX_GBIF_SCACHE_CNTL0[14:10]
+*/
+ if (adreno_is_a660_family(adreno_gpu))
+ gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL0, (0x1f << 10) |
+ (1 << 8), (gpu_scid << 10) | (1 << 8));
}
/*
@@ -1458,13 +1465,6 @@ static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu)
}
gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL1, GENMASK(24, 0), cntl1_regval);
-
- /* On A660, the SCID programming for UCHE traffic is done in
-* A6XX_GBIF_SCACHE_CNTL0[14:10]
-*/
- if (adreno_is_a660_family(adreno_gpu))
- gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL0, (0x1f << 10) |
- (1 << 8), (gpu_scid << 10) | (1 << 8));
}
static void a6xx_llc_slices_destroy(struct a6xx_gpu *a6xx_gpu)
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation.
[PATCH v2 2/6] drm/msm: Fix null ptr dereference in msm_ioctl_gem_submit()
Fix the below null pointer dereference in msm_ioctl_gem_submit():
26545.260705: Call trace:
26545.263223:kref_put+0x1c/0x60
26545.266452:msm_ioctl_gem_submit+0x254/0x744
26545.270937:drm_ioctl_kernel+0xa8/0x124
26545.274976:drm_ioctl+0x21c/0x33c
26545.278478:drm_compat_ioctl+0xdc/0xf0
26545.282428:__arm64_compat_sys_ioctl+0xc8/0x100
26545.287169:el0_svc_common+0xf8/0x250
26545.291025:do_el0_svc_compat+0x28/0x54
26545.295066:el0_svc_compat+0x10/0x1c
26545.298838:el0_sync_compat_handler+0xa8/0xcc
26545.303403:el0_sync_compat+0x188/0x1c0
26545.307445: Code: d503201f d503201f 52800028 4b0803e8 (b8680008)
26545.313703: ---[ end trace 5c93eb55e485b259 ]---
26545.318799: Kernel panic - not syncing: Oops: Fatal exception
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
drivers/gpu/drm/msm/msm_gem_submit.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c
b/drivers/gpu/drm/msm/msm_gem_submit.c
index ac23bbd..88a6cd5 100644
--- a/drivers/gpu/drm/msm/msm_gem_submit.c
+++ b/drivers/gpu/drm/msm/msm_gem_submit.c
@@ -780,6 +780,7 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
args->nr_cmds);
if (IS_ERR(submit)) {
ret = PTR_ERR(submit);
+ submit = NULL;
goto out_unlock;
}
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation.
Re: [Freedreno] [PATCH] drm/msm/dpu: Add more of the INTF interrupt regions
On Tue 23 Nov 12:54 PST 2021, Abhinav Kumar wrote:
> Hi Bjorn
>
> On 11/23/2021 7:40 AM, Bjorn Andersson wrote:
> > In addition to the other 7xxx INTF interrupt regions, SM8350 has
> > additional INTF regions at 0x0ae37000, 0x0ae38000 and 0x0ae39000, define
> > these. The 7xxx naming scheme of the bits are kept for consistency.
> >
> More than consistency, this is because both sc7280 and SM8350 use MDP's
> 7x hw version.
>
Aha, didn't connect the dots.
Thank you for the clarification.
> Otherwise,
>
> Reviewed-by: Abhinav Kumar
Thanks,
Bjorn
> > Signed-off-by: Bjorn Andersson
> > ---
> > .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 18 ++
> > .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 3 +++
> > 2 files changed, 21 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> > index d2b6dca487e3..a77a5eaa78ad 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> > @@ -30,6 +30,9 @@
> > #define MDP_AD4_INTR_STATUS_OFF 0x420
> > #define MDP_INTF_0_OFF_REV_7xxx 0x34000
> > #define MDP_INTF_1_OFF_REV_7xxx 0x35000
> > +#define MDP_INTF_2_OFF_REV_7xxx 0x36000
> > +#define MDP_INTF_3_OFF_REV_7xxx 0x37000
> > +#define MDP_INTF_4_OFF_REV_7xxx 0x38000
> > #define MDP_INTF_5_OFF_REV_7xxx 0x39000
> > /**
> > @@ -110,6 +113,21 @@ static const struct dpu_intr_reg dpu_intr_set[] = {
> > MDP_INTF_1_OFF_REV_7xxx+INTF_INTR_EN,
> > MDP_INTF_1_OFF_REV_7xxx+INTF_INTR_STATUS
> > },
> > + {
> > + MDP_INTF_2_OFF_REV_7xxx+INTF_INTR_CLEAR,
> > + MDP_INTF_2_OFF_REV_7xxx+INTF_INTR_EN,
> > + MDP_INTF_2_OFF_REV_7xxx+INTF_INTR_STATUS
> > + },
> > + {
> > + MDP_INTF_3_OFF_REV_7xxx+INTF_INTR_CLEAR,
> > + MDP_INTF_3_OFF_REV_7xxx+INTF_INTR_EN,
> > + MDP_INTF_3_OFF_REV_7xxx+INTF_INTR_STATUS
> > + },
> > + {
> > + MDP_INTF_4_OFF_REV_7xxx+INTF_INTR_CLEAR,
> > + MDP_INTF_4_OFF_REV_7xxx+INTF_INTR_EN,
> > + MDP_INTF_4_OFF_REV_7xxx+INTF_INTR_STATUS
> > + },
> > {
> > MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_CLEAR,
> > MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_EN,
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> > index d50e78c9f148..1ab75cccd145 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> > @@ -26,6 +26,9 @@ enum dpu_hw_intr_reg {
> > MDP_AD4_1_INTR,
> > MDP_INTF0_7xxx_INTR,
> > MDP_INTF1_7xxx_INTR,
> > + MDP_INTF2_7xxx_INTR,
> > + MDP_INTF3_7xxx_INTR,
> > + MDP_INTF4_7xxx_INTR,
> > MDP_INTF5_7xxx_INTR,
> > MDP_INTR_MAX,
> > };
> >
Re: [Freedreno] [PATCH] drm/msm/dpu: Add more of the INTF interrupt regions
Hi Bjorn
On 11/23/2021 7:40 AM, Bjorn Andersson wrote:
In addition to the other 7xxx INTF interrupt regions, SM8350 has
additional INTF regions at 0x0ae37000, 0x0ae38000 and 0x0ae39000, define
these. The 7xxx naming scheme of the bits are kept for consistency.
More than consistency, this is because both sc7280 and SM8350 use MDP's
7x hw version.
Otherwise,
Reviewed-by: Abhinav Kumar
Signed-off-by: Bjorn Andersson
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 18 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 3 +++
2 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
index d2b6dca487e3..a77a5eaa78ad 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
@@ -30,6 +30,9 @@
#define MDP_AD4_INTR_STATUS_OFF 0x420
#define MDP_INTF_0_OFF_REV_7xxx 0x34000
#define MDP_INTF_1_OFF_REV_7xxx 0x35000
+#define MDP_INTF_2_OFF_REV_7xxx 0x36000
+#define MDP_INTF_3_OFF_REV_7xxx 0x37000
+#define MDP_INTF_4_OFF_REV_7xxx 0x38000
#define MDP_INTF_5_OFF_REV_7xxx 0x39000
/**
@@ -110,6 +113,21 @@ static const struct dpu_intr_reg dpu_intr_set[] = {
MDP_INTF_1_OFF_REV_7xxx+INTF_INTR_EN,
MDP_INTF_1_OFF_REV_7xxx+INTF_INTR_STATUS
},
+ {
+ MDP_INTF_2_OFF_REV_7xxx+INTF_INTR_CLEAR,
+ MDP_INTF_2_OFF_REV_7xxx+INTF_INTR_EN,
+ MDP_INTF_2_OFF_REV_7xxx+INTF_INTR_STATUS
+ },
+ {
+ MDP_INTF_3_OFF_REV_7xxx+INTF_INTR_CLEAR,
+ MDP_INTF_3_OFF_REV_7xxx+INTF_INTR_EN,
+ MDP_INTF_3_OFF_REV_7xxx+INTF_INTR_STATUS
+ },
+ {
+ MDP_INTF_4_OFF_REV_7xxx+INTF_INTR_CLEAR,
+ MDP_INTF_4_OFF_REV_7xxx+INTF_INTR_EN,
+ MDP_INTF_4_OFF_REV_7xxx+INTF_INTR_STATUS
+ },
{
MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_CLEAR,
MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_EN,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
index d50e78c9f148..1ab75cccd145 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
@@ -26,6 +26,9 @@ enum dpu_hw_intr_reg {
MDP_AD4_1_INTR,
MDP_INTF0_7xxx_INTR,
MDP_INTF1_7xxx_INTR,
+ MDP_INTF2_7xxx_INTR,
+ MDP_INTF3_7xxx_INTR,
+ MDP_INTF4_7xxx_INTR,
MDP_INTF5_7xxx_INTR,
MDP_INTR_MAX,
};
Re: [WARN][AMDGPU] Linux 5.15.4 with AMD Bonaire GPU
Alas no, other than to observe that the issue is not present in 5.13.15, but is present in 5.14.3; i.e. the last 5.13.x and first 5.14.x kernels that I compiled myself. Cheers, Chris On Tue, 23 Nov 2021 at 20:14, Alex Deucher wrote: > On Sun, Nov 21, 2021 at 9:47 AM Chris Rankin wrote: > > > > Hi, > > > > i have found this warning in my vanilla 5.15.4 kernel's dmesg log: > > > > [ 87.687139] [ cut here ] > > [ 87.710799] WARNING: CPU: 1 PID: 1 at > > drivers/gpu/drm/ttm/ttm_bo.c:409 ttm_bo_release+0x1c/0x266 [ttm] > > [ 87.718965] Modules linked in: nf_nat_ftp nf_conntrack_ftp cfg80211 > > af_packet nft_fib_inet nft_fib_ipv4 nft_fib_ipv6 nft_fib > > nft_reject_inet nf_reject_ipv4 nf_reject_ipv6 nft_reject nft_ct > > nft_chain_nat nf_tables ebtable_nat ebtable_broute ip6table_nat > > ip6table_mangle ip6table_raw ip6table_security iptable_nat nf_nat > > nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4 libcrc32c iptable_mangle > > iptable_raw iptable_security nfnetlink ebtable_filter ebtables > > ip6table_filter ip6_tables iptable_filter bnep it87 hwmon_vid dm_mod > > dax snd_hda_codec_realtek snd_hda_codec_generic ledtrig_audio > > snd_hda_codec_hdmi snd_hda_intel uvcvideo videobuf2_vmalloc > > videobuf2_memops snd_intel_dspcfg snd_hda_codec snd_usb_audio > > snd_usbmidi_lib snd_hwdep videobuf2_v4l2 snd_virtuoso snd_oxygen_lib > > videobuf2_common btusb snd_mpu401_uart input_leds snd_hda_core > > videodev btbcm snd_rawmidi btintel joydev snd_seq mc led_class > > bluetooth ecdh_generic rfkill snd_seq_device ecc snd_pcm r8169 > > coretemp snd_hrtimer i2c_i801 psmouse > > [ 87.719024] i2c_smbus pcspkr kvm_intel realtek kvm snd_timer > > gpio_ich mdio_devres iTCO_wdt snd libphy mxm_wmi irqbypass soundcore > > tiny_power_button lpc_ich i7core_edac acpi_cpufreq button wmi nfsd > > auth_rpcgss nfs_acl lockd grace sunrpc binfmt_misc fuse configfs zram > > zsmalloc ip_tables x_tables ext4 crc32c_generic crc16 mbcache jbd2 > > hid_microsoft usbhid sr_mod cdrom sd_mod amdgpu uhci_hcd > > drm_ttm_helper ehci_pci ttm mfd_core ehci_hcd gpu_sched xhci_pci > > xhci_hcd i2c_algo_bit crc32c_intel serio_raw drm_kms_helper > > firewire_ohci ahci libahci pata_jmicron firewire_core libata crc_itu_t > > cfbfillrect syscopyarea cfbimgblt sysfillrect sysimgblt fb_sys_fops > > cfbcopyarea cec rc_core scsi_mod usbcore drm bsg scsi_common > > usb_common drm_panel_orientation_quirks ipmi_devintf ipmi_msghandler > > msr sha256_ssse3 sha256_generic ipv6 crc_ccitt > > [ 87.876267] CPU: 1 PID: 1 Comm: systemd Tainted: G I > 5.15.4 #1 > > [ 87.882109] Hardware name: Gigabyte Technology Co., Ltd. > > EX58-UD3R/EX58-UD3R, BIOS FB 05/04/2009 > > [ 87.889800] RIP: 0010:ttm_bo_release+0x1c/0x266 [ttm] > > [ 87.893615] Code: 44 89 e0 5b 5d 41 5c 41 5d 41 5e 41 5f c3 41 56 > > 41 55 41 54 4c 8d a7 90 fe ff ff 55 53 83 7f 4c 00 48 89 fb 48 8b 6f > > e8 74 02 <0f> 0b 80 7b 18 00 48 8b 43 88 0f 85 ac 00 00 00 4c 8d 6b 90 > > 49 39 > > [ 87.911829] RSP: 0018:c9023e00 EFLAGS: 00010202 > > [ 87.915886] RAX: 0001 RBX: 888123a449c8 RCX: > 004c > > [ 87.921825] RDX: 01f3 RSI: a02ee0e5 RDI: > 888123a449c8 > > [ 87.927750] RBP: 88810d6652f0 R08: 0001 R09: > 0003 > > [ 87.933869] R10: 4000 R11: 888109970600 R12: > 888123a44858 > > [ 87.939767] R13: 888146e35ad0 R14: 888146dad6c0 R15: > > > [ 87.945604] FS: 7f901262ab40() GS:888343c4() > > knlGS: > > [ 87.952390] CS: 0010 DS: ES: CR0: 80050033 > > [ 87.956837] CR2: 55d9edfa8fa0 CR3: 00010218 CR4: > 06e0 > > [ 87.962704] Call Trace: > > [ 87.963876] > > [ 87.964742] amdgpu_bo_unref+0x15/0x1e [amdgpu] > > [ 87.968219] amdgpu_gem_object_free+0x2b/0x45 [amdgpu] > > [ 87.972135] drm_gem_dmabuf_release+0x11/0x1a [drm] > > [ 87.975792] dma_buf_release+0x36/0x7d > > [ 87.978363] __dentry_kill+0xf5/0x12f > > [ 87.980749] dput+0xfc/0x136 > > [ 87.982386] __fput+0x17a/0x1cc > > [ 87.984234] task_work_run+0x64/0x75 > > [ 87.986615] exit_to_user_mode_prepare+0x88/0x112 > > [ 87.990111] syscall_exit_to_user_mode+0x14/0x1f > > [ 87.993513] do_syscall_64+0x7a/0x80 > > [ 87.995873] entry_SYSCALL_64_after_hwframe+0x44/0xae > > [ 87.999798] RIP: 0033:0x7f9013160fdb > > [ 88.002129] Code: 03 00 00 00 0f 05 48 3d 00 f0 ff ff 77 41 c3 48 > > 83 ec 18 89 7c 24 0c e8 33 81 f8 ff 8b 7c 24 0c 41 89 c0 b8 03 00 00 > > 00 0f 05 <48> 3d 00 f0 ff ff 77 35 44 89 c7 89 44 24 0c e8 81 81 f8 ff > > 8b 44 > > [ 88.020215] RSP: 002b:7ffda9891d20 EFLAGS: 0293 ORIG_RAX: > > 0003 > > [ 88.026698] RAX: RBX: 7f901262a8f0 RCX: > 7f9013160fdb > > [ 88.032789] RDX: RSI: 00055d9edfc6 RDI: > 0069 > > [ 88.038864] RBP: 0069 R08:
[PATCH v2 2/2] drm/amdkfd: Slighly optimize 'init_doorbell_bitmap()'
The 'doorbell_bitmap' bitmap has just been allocated. So we can use the
non-atomic '__set_bit()' function to save a few cycles as no concurrent
access can happen.
Reviewed-by: Felix Kuehling
Signed-off-by: Christophe JAILLET
---
bitmap_set() could certainly also be use, but range checking would be
tricky.
v1 --> v2: No change
---
drivers/gpu/drm/amd/amdkfd/kfd_process.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index 67bb1654becc..9158f9754a24 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -1446,9 +1446,9 @@ static int init_doorbell_bitmap(struct qcm_process_device
*qpd,
for (i = 0; i < KFD_MAX_NUM_OF_QUEUES_PER_PROCESS / 2; i++) {
if (i >= range_start && i <= range_end) {
- set_bit(i, qpd->doorbell_bitmap);
- set_bit(i + KFD_QUEUE_DOORBELL_MIRROR_OFFSET,
- qpd->doorbell_bitmap);
+ __set_bit(i, qpd->doorbell_bitmap);
+ __set_bit(i + KFD_QUEUE_DOORBELL_MIRROR_OFFSET,
+ qpd->doorbell_bitmap);
}
}
--
2.30.2
[PATCH v2 1/2] drm/amdkfd: Use bitmap_zalloc() when applicable
'doorbell_bitmap' and 'queue_slot_bitmap' are bitmaps. So use
'bitmap_zalloc()' to simplify code, improve the semantic and avoid some
open-coded arithmetic in allocator arguments.
Also change the corresponding 'kfree()' into 'bitmap_free()' to keep
consistency.
Reviewed-by: Felix Kuehling
Signed-off-by: Christophe JAILLET
---
v1 --> v2: Compile tested :)
Add a missing ',' (kernel test robot)
Add kfd_process_queue_manager.c (Felix Kuehling)
---
drivers/gpu/drm/amd/amdkfd/kfd_process.c | 7 +++
drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 7 +++
2 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index d4c8a6948a9f..67bb1654becc 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -1011,7 +1011,7 @@ static void kfd_process_destroy_pdds(struct kfd_process
*p)
free_pages((unsigned long)pdd->qpd.cwsr_kaddr,
get_order(KFD_CWSR_TBA_TMA_SIZE));
- kfree(pdd->qpd.doorbell_bitmap);
+ bitmap_free(pdd->qpd.doorbell_bitmap);
idr_destroy(>alloc_idr);
kfd_free_process_doorbells(pdd->dev, pdd->doorbell_index);
@@ -1433,9 +1433,8 @@ static int init_doorbell_bitmap(struct qcm_process_device
*qpd,
if (!KFD_IS_SOC15(dev))
return 0;
- qpd->doorbell_bitmap =
- kzalloc(DIV_ROUND_UP(KFD_MAX_NUM_OF_QUEUES_PER_PROCESS,
-BITS_PER_BYTE), GFP_KERNEL);
+ qpd->doorbell_bitmap = bitmap_zalloc(KFD_MAX_NUM_OF_QUEUES_PER_PROCESS,
+GFP_KERNEL);
if (!qpd->doorbell_bitmap)
return -ENOMEM;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
index 4f8464658daf..c5f5a25c6dcc 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
@@ -135,9 +135,8 @@ void kfd_process_dequeue_from_all_devices(struct
kfd_process *p)
int pqm_init(struct process_queue_manager *pqm, struct kfd_process *p)
{
INIT_LIST_HEAD(>queues);
- pqm->queue_slot_bitmap =
- kzalloc(DIV_ROUND_UP(KFD_MAX_NUM_OF_QUEUES_PER_PROCESS,
- BITS_PER_BYTE), GFP_KERNEL);
+ pqm->queue_slot_bitmap =
bitmap_zalloc(KFD_MAX_NUM_OF_QUEUES_PER_PROCESS,
+ GFP_KERNEL);
if (!pqm->queue_slot_bitmap)
return -ENOMEM;
pqm->process = p;
@@ -159,7 +158,7 @@ void pqm_uninit(struct process_queue_manager *pqm)
kfree(pqn);
}
- kfree(pqm->queue_slot_bitmap);
+ bitmap_free(pqm->queue_slot_bitmap);
pqm->queue_slot_bitmap = NULL;
}
--
2.30.2
Re: [PATCH v8 0/8] MIPS: JZ4780 and CI20 HDMI
Hi Paul, > Am 23.11.2021 um 21:12 schrieb Paul Cercueil : > > Hi Nikolaus, > > I think if you can fix the last few things I commented on, and I get an ACK > from Rob for the Device Tree related patches, then it will be ready to merge. Fine! Especially for finding the NULL regulator risk. Will do in the next days. For the unwedge pinmux I have to check if we need it at all. BR and thanks, Nikolaus > > Cheers, > -Paul > > > Le mar., nov. 23 2021 at 19:13:53 +0100, H. Nikolaus Schaller > a écrit : >> PATCH V8 2021-11-23 19:14:00: >> - fix a bad editing result from patch 2/8 (found by p...@crapouillou.net) >> PATCH V7 2021-11-23 18:46:23: >> - changed gpio polarity of hdmi_power to 0 (suggested by >> p...@crapouillou.net) >> - fixed LCD1 irq number (bug found by p...@crapouillou.net) >> - removed "- 4" for calculating max_register (suggested by >> p...@crapouillou.net) >> - use unevaluatedPropertes instead of additionalProperties (suggested by >> r...@kernel.org) >> - moved and renamed ingenic,jz4780-hdmi.yaml (suggested by r...@kernel.org) >> - adjusted assigned-clocks changes to upstream which added some for SSI (by >> h...@goldelico.com) >> - rebased and tested with v5.16-rc2 + patch set drm/ingenic by >> p...@crapouillou.net (by h...@goldelico.com) >> PATCH V6 2021-11-10 20:43:33: >> - changed CONFIG_DRM_INGENIC_DW_HDMI to "m" (by h...@goldelico.com) >> - made ingenic-dw-hdmi an independent platform driver which can be compiled >> as module >> and removed error patch fixes for IPU (suggested by p...@crapouillou.net) >> - moved assigned-clocks from jz4780.dtsi to ci20.dts (suggested by >> p...@crapouillou.net) >> - fixed reg property in jz4780.dtsi to cover all registers incl. gamma and >> vee (by h...@goldelico.com) >> - added a base patch to calculate regmap size from DTS reg property >> (requested by p...@crapouillou.net) >> - restored resetting all bits except one in LCDOSDC (requested by >> p...@crapouillou.net) >> - clarified setting of cpos (suggested by p...@crapouillou.net) >> - moved bindings definition for ddc-i2c-bus (suggested by >> p...@crapouillou.net) >> - simplified mask definitions for JZ_LCD_DESSIZE (requested by >> p...@crapouillou.net) >> - removed setting alpha premultiplication (suggested by p...@crapouillou.net) >> - removed some comments (suggested by p...@crapouillou.net) >> PATCH V5 2021-10-05 14:28:44: >> - dropped mode_fixup and timings support in dw-hdmi as it is no longer >> needed in this V5 (by h...@goldelico.com) >> - dropped "drm/ingenic: add some jz4780 specific features" (stimulated by >> p...@crapouillou.net) >> - fixed typo in commit subject: "synopsis" -> "synopsys" (by >> h...@goldelico.com) >> - swapped clocks in jz4780.dtsi to match synopsys,dw-hdmi.yaml (by >> h...@goldelico.com) >> - improved, simplified, fixed, dtbschecked ingenic-jz4780-hdmi.yaml and made >> dependent of bridge/synopsys,dw-hdmi.yaml (based on suggestions by >> max...@cerno.tech) >> - fixed binding vs. driver use of hdmi-5v regulator (suggested by >> max...@cerno.tech) >> - dropped "drm/bridge: synopsis: Fix to properly handle HPD" - was a no >> longer needed workaround for a previous version >> (suggested by max...@cerno.tech) >> PATCH V4 2021-09-27 18:44:38: >> - fix setting output_port = 1 (issue found by p...@crapouillou.net) >> - ci20.dts: convert to use hdmi-connector (by h...@goldelico.com) >> - add a hdmi-regulator to control +5V power (by h...@goldelico.com) >> - added a fix to dw-hdmi to call drm_kms_helper_hotplug_event on plugin >> event detection (by h...@goldelico.com) >> - always allocate extended descriptor but initialize only for jz4780 (by >> h...@goldelico.com) >> - updated to work on top of "[PATCH v3 0/6] drm/ingenic: Various >> improvements v3" (by p...@crapouillou.net) >> - rebased to v5.13-rc3 >> PATCH V3 2021-08-08 07:10:50: >> This series adds HDMI support for JZ4780 and CI20 board (and fixes one IPU >> related issue in registration error path) >> - [patch 1/8] switched from mode_fixup to atomic_check (suggested by >> robert.f...@linaro.org) >> - the call to the dw-hdmi specialization is still called mode_fixup >> - [patch 3/8] diverse fixes for ingenic-drm-drv (suggested by >> p...@crapouillou.net) >> - factor out some non-HDMI features of the jz4780 into a separate patch >> - multiple fixes around max height >> - do not change regmap config but a copy on stack >> - define some constants >> - factor out fixing of drm_init error path for IPU into separate patch >> - use FIELD_PREP() >> - [patch 8/8] conversion to component framework dropped (suggested by >> laurent.pinch...@ideasonboard.com and p...@crapouillou.net) >> PATCH V2 2021-08-05 16:08:05: >> - code and commit messages revisited for checkpatch warnings >> - rebased on v5.14-rc4 >> - include (failed, hence RFC 8/8) attempt to convert to component framework >> (was suggested by Paul Cercueil a while ago) >> This series adds HDMI support for JZ4780 and CI20 board
[Bug 211277] sometimes crash at s2ram-wake (Ryzen 3500U): amdgpu, drm, commit_tail, amdgpu_dm_atomic_commit_tail
https://bugzilla.kernel.org/show_bug.cgi?id=211277 --- Comment #76 from Alex Deucher (alexdeuc...@gmail.com) --- (In reply to James Zhu from comment #75) > (In reply to kolAflash from comment #74) > > @James Zhu > > > > Tested 5.15.2 for over a week and more than 50 standby-wakeups. > > No problems! > > Thanks :-) > > > > I would be happy about a patch for the 5.10 longterm kernel. > > The bug became a problem with v5.10-rc3 (see comment 14), just before > Debian > > made 5.10-longterm the Debian-11 kernel. So it would be great if I and > > probably other Debian-11 users could finally use that AMD GPU without > > workarounds. > > Hi @Alex Deucher, Can you help on this request? thanks! James I cc'ed stable with the patches so they should show up in 5.10 assuming they apply cleanly. If not, can you look at what it would take to backport them? -- You may reply to this email to add a comment. You are receiving this mail because: You are watching the assignee of the bug.
Re: [PATCH 0/5] xen: cleanup detection of non-essential pv devices
On 11/22/21 3:20 AM, Juergen Gross wrote: On 22.10.21 08:47, Juergen Gross wrote: Today the non-essential pv devices are hard coded in the xenbus driver and this list is lacking multiple entries. This series reworks the detection logic of non-essential devices by adding a flag for that purpose to struct xenbus_driver. Juergen Gross (5): xen: add "not_essential" flag to struct xenbus_driver xen: flag xen_drm_front to be not essential for system boot xen: flag hvc_xen to be not essential for system boot xen: flag pvcalls-front to be not essential for system boot xen: flag xen_snd_front to be not essential for system boot drivers/gpu/drm/xen/xen_drm_front.c | 1 + drivers/input/misc/xen-kbdfront.c | 1 + drivers/tty/hvc/hvc_xen.c | 1 + drivers/video/fbdev/xen-fbfront.c | 1 + drivers/xen/pvcalls-front.c | 1 + drivers/xen/xenbus/xenbus_probe_frontend.c | 14 +++--- include/xen/xenbus.h | 1 + sound/xen/xen_snd_front.c | 1 + 8 files changed, 10 insertions(+), 11 deletions(-) Any further comments? Reviewed-by: Boris Ostrovsky (I'll fix the semicolon typo in the last patch, no need to resend)
[PATCH v2 3/8] macintosh/mac_hid.c: simplify subdirectory registration with register_sysctl()
There is no need to user boiler plate code to specify a set of base
directories we're going to stuff sysctls under. Simplify this by using
register_sysctl() and specifying the directory path directly.
// pycocci sysctl-subdir-register-sysctl-simplify.cocci PATH
@c1@
expression E1;
identifier subdir, sysctls;
@@
static struct ctl_table subdir[] = {
{
.procname = E1,
.maxlen = 0,
.mode = 0555,
.child = sysctls,
},
{ }
};
@c2@
identifier c1.subdir;
expression E2;
identifier base;
@@
static struct ctl_table base[] = {
{
.procname = E2,
.maxlen = 0,
.mode = 0555,
.child = subdir,
},
{ }
};
@c3@
identifier c2.base;
identifier header;
@@
header = register_sysctl_table(base);
@r1 depends on c1 && c2 && c3@
expression c1.E1;
identifier c1.subdir, c1.sysctls;
@@
-static struct ctl_table subdir[] = {
- {
- .procname = E1,
- .maxlen = 0,
- .mode = 0555,
- .child = sysctls,
- },
- { }
-};
@r2 depends on c1 && c2 && c3@
identifier c1.subdir;
expression c2.E2;
identifier c2.base;
@@
-static struct ctl_table base[] = {
- {
- .procname = E2,
- .maxlen = 0,
- .mode = 0555,
- .child = subdir,
- },
- { }
-};
@initialize:python@
@@
def make_my_fresh_expression(s1, s2):
return '"' + s1.strip('"') + "/" + s2.strip('"') + '"'
@r3 depends on c1 && c2 && c3@
expression c1.E1;
identifier c1.sysctls;
expression c2.E2;
identifier c2.base;
identifier c3.header;
fresh identifier E3 = script:python(E2, E1) { make_my_fresh_expression(E2, E1)
};
@@
header =
-register_sysctl_table(base);
+register_sysctl(E3, sysctls);
Generated-by: Coccinelle SmPL
Signed-off-by: Luis Chamberlain
---
drivers/macintosh/mac_hid.c | 24 +---
1 file changed, 1 insertion(+), 23 deletions(-)
diff --git a/drivers/macintosh/mac_hid.c b/drivers/macintosh/mac_hid.c
index 28b8581b44dd..d8c4d5664145 100644
--- a/drivers/macintosh/mac_hid.c
+++ b/drivers/macintosh/mac_hid.c
@@ -239,33 +239,11 @@ static struct ctl_table mac_hid_files[] = {
{ }
};
-/* dir in /proc/sys/dev */
-static struct ctl_table mac_hid_dir[] = {
- {
- .procname = "mac_hid",
- .maxlen = 0,
- .mode = 0555,
- .child = mac_hid_files,
- },
- { }
-};
-
-/* /proc/sys/dev itself, in case that is not there yet */
-static struct ctl_table mac_hid_root_dir[] = {
- {
- .procname = "dev",
- .maxlen = 0,
- .mode = 0555,
- .child = mac_hid_dir,
- },
- { }
-};
-
static struct ctl_table_header *mac_hid_sysctl_header;
static int __init mac_hid_init(void)
{
- mac_hid_sysctl_header = register_sysctl_table(mac_hid_root_dir);
+ mac_hid_sysctl_header = register_sysctl("dev/mac_hid", mac_hid_files);
if (!mac_hid_sysctl_header)
return -ENOMEM;
--
2.33.0
[PATCH v2 6/8] inotify: simplify subdirectory registration with register_sysctl()
From: Xiaoming Ni
There is no need to user boiler plate code to specify a set of base
directories we're going to stuff sysctls under. Simplify this by using
register_sysctl() and specifying the directory path directly.
Move inotify_user sysctl to inotify_user.c while at it to remove clutter
from kernel/sysctl.c.
Signed-off-by: Xiaoming Ni
[mcgrof: update commit log to reflect new path we decided to take]
Signed-off-by: Luis Chamberlain
---
fs/notify/inotify/inotify_user.c | 11 ++-
include/linux/inotify.h | 3 ---
kernel/sysctl.c | 21 -
3 files changed, 10 insertions(+), 25 deletions(-)
diff --git a/fs/notify/inotify/inotify_user.c b/fs/notify/inotify/inotify_user.c
index 29fca3284bb5..54583f62dc44 100644
--- a/fs/notify/inotify/inotify_user.c
+++ b/fs/notify/inotify/inotify_user.c
@@ -58,7 +58,7 @@ struct kmem_cache *inotify_inode_mark_cachep __read_mostly;
static long it_zero = 0;
static long it_int_max = INT_MAX;
-struct ctl_table inotify_table[] = {
+static struct ctl_table inotify_table[] = {
{
.procname = "max_user_instances",
.data =
_user_ns.ucount_max[UCOUNT_INOTIFY_INSTANCES],
@@ -87,6 +87,14 @@ struct ctl_table inotify_table[] = {
},
{ }
};
+
+static void __init inotify_sysctls_init(void)
+{
+ register_sysctl("fs/inotify", inotify_table);
+}
+
+#else
+#define inotify_sysctls_init() do { } while (0)
#endif /* CONFIG_SYSCTL */
static inline __u32 inotify_arg_to_mask(struct inode *inode, u32 arg)
@@ -849,6 +857,7 @@ static int __init inotify_user_setup(void)
inotify_max_queued_events = 16384;
init_user_ns.ucount_max[UCOUNT_INOTIFY_INSTANCES] = 128;
init_user_ns.ucount_max[UCOUNT_INOTIFY_WATCHES] = watches_max;
+ inotify_sysctls_init();
return 0;
}
diff --git a/include/linux/inotify.h b/include/linux/inotify.h
index 6a24905f6e1e..8d20caa1b268 100644
--- a/include/linux/inotify.h
+++ b/include/linux/inotify.h
@@ -7,11 +7,8 @@
#ifndef _LINUX_INOTIFY_H
#define _LINUX_INOTIFY_H
-#include
#include
-extern struct ctl_table inotify_table[]; /* for sysctl */
-
#define ALL_INOTIFY_BITS (IN_ACCESS | IN_MODIFY | IN_ATTRIB | IN_CLOSE_WRITE |
\
IN_CLOSE_NOWRITE | IN_OPEN | IN_MOVED_FROM | \
IN_MOVED_TO | IN_CREATE | IN_DELETE | \
diff --git a/kernel/sysctl.c b/kernel/sysctl.c
index 7a90a12b9ea4..6aa67c737e4e 100644
--- a/kernel/sysctl.c
+++ b/kernel/sysctl.c
@@ -125,13 +125,6 @@ static const int maxolduid = 65535;
static const int ngroups_max = NGROUPS_MAX;
static const int cap_last_cap = CAP_LAST_CAP;
-#ifdef CONFIG_INOTIFY_USER
-#include
-#endif
-#ifdef CONFIG_FANOTIFY
-#include
-#endif
-
#ifdef CONFIG_PROC_SYSCTL
/**
@@ -3099,20 +3092,6 @@ static struct ctl_table fs_table[] = {
.proc_handler = proc_dointvec,
},
#endif
-#ifdef CONFIG_INOTIFY_USER
- {
- .procname = "inotify",
- .mode = 0555,
- .child = inotify_table,
- },
-#endif
-#ifdef CONFIG_FANOTIFY
- {
- .procname = "fanotify",
- .mode = 0555,
- .child = fanotify_table,
- },
-#endif
#ifdef CONFIG_EPOLL
{
.procname = "epoll",
--
2.33.0
[PATCH v2 1/8] hpet: simplify subdirectory registration with register_sysctl()
There is no need to user boiler plate code to specify a set of base
directories we're going to stuff sysctls under. Simplify this by using
register_sysctl() and specifying the directory path directly.
// pycocci sysctl-subdir-register-sysctl-simplify.cocci drivers/char/hpet.c
@c1@
expression E1;
identifier subdir, sysctls;
@@
static struct ctl_table subdir[] = {
{
.procname = E1,
.maxlen = 0,
.mode = 0555,
.child = sysctls,
},
{ }
};
@c2@
identifier c1.subdir;
expression E2;
identifier base;
@@
static struct ctl_table base[] = {
{
.procname = E2,
.maxlen = 0,
.mode = 0555,
.child = subdir,
},
{ }
};
@c3@
identifier c2.base;
identifier header;
@@
header = register_sysctl_table(base);
@r1 depends on c1 && c2 && c3@
expression c1.E1;
identifier c1.subdir, c1.sysctls;
@@
-static struct ctl_table subdir[] = {
- {
- .procname = E1,
- .maxlen = 0,
- .mode = 0555,
- .child = sysctls,
- },
- { }
-};
@r2 depends on c1 && c2 && c3@
identifier c1.subdir;
expression c2.E2;
identifier c2.base;
@@
-static struct ctl_table base[] = {
- {
- .procname = E2,
- .maxlen = 0,
- .mode = 0555,
- .child = subdir,
- },
- { }
-};
@initialize:python@
@@
def make_my_fresh_expression(s1, s2):
return '"' + s1.strip('"') + "/" + s2.strip('"') + '"'
@r3 depends on c1 && c2 && c3@
expression c1.E1;
identifier c1.sysctls;
expression c2.E2;
identifier c2.base;
identifier c3.header;
fresh identifier E3 = script:python(E2, E1) { make_my_fresh_expression(E2, E1)
};
@@
header =
-register_sysctl_table(base);
+register_sysctl(E3, sysctls);
Generated-by: Coccinelle SmPL
Signed-off-by: Luis Chamberlain
---
drivers/char/hpet.c | 22 +-
1 file changed, 1 insertion(+), 21 deletions(-)
diff --git a/drivers/char/hpet.c b/drivers/char/hpet.c
index 4e5431f01450..563dfae3b8da 100644
--- a/drivers/char/hpet.c
+++ b/drivers/char/hpet.c
@@ -746,26 +746,6 @@ static struct ctl_table hpet_table[] = {
{}
};
-static struct ctl_table hpet_root[] = {
- {
-.procname = "hpet",
-.maxlen = 0,
-.mode = 0555,
-.child = hpet_table,
-},
- {}
-};
-
-static struct ctl_table dev_root[] = {
- {
-.procname = "dev",
-.maxlen = 0,
-.mode = 0555,
-.child = hpet_root,
-},
- {}
-};
-
static struct ctl_table_header *sysctl_header;
/*
@@ -1061,7 +1041,7 @@ static int __init hpet_init(void)
if (result < 0)
return -ENODEV;
- sysctl_header = register_sysctl_table(dev_root);
+ sysctl_header = register_sysctl("dev/hpet", hpet_table);
result = acpi_bus_register_driver(_acpi_driver);
if (result < 0) {
--
2.33.0
[PATCH v2 7/8] cdrom: simplify subdirectory registration with register_sysctl()
There is no need to user boiler plate code to specify a set of base
directories we're going to stuff sysctls under. Simplify this by using
register_sysctl() and specifying the directory path directly.
// pycocci sysctl-subdir-register-sysctl-simplify.cocci PATH
@c1@
expression E1;
identifier subdir, sysctls;
@@
static struct ctl_table subdir[] = {
{
.procname = E1,
.maxlen = 0,
.mode = 0555,
.child = sysctls,
},
{ }
};
@c2@
identifier c1.subdir;
expression E2;
identifier base;
@@
static struct ctl_table base[] = {
{
.procname = E2,
.maxlen = 0,
.mode = 0555,
.child = subdir,
},
{ }
};
@c3@
identifier c2.base;
identifier header;
@@
header = register_sysctl_table(base);
@r1 depends on c1 && c2 && c3@
expression c1.E1;
identifier c1.subdir, c1.sysctls;
@@
-static struct ctl_table subdir[] = {
- {
- .procname = E1,
- .maxlen = 0,
- .mode = 0555,
- .child = sysctls,
- },
- { }
-};
@r2 depends on c1 && c2 && c3@
identifier c1.subdir;
expression c2.E2;
identifier c2.base;
@@
-static struct ctl_table base[] = {
- {
- .procname = E2,
- .maxlen = 0,
- .mode = 0555,
- .child = subdir,
- },
- { }
-};
@initialize:python@
@@
def make_my_fresh_expression(s1, s2):
return '"' + s1.strip('"') + "/" + s2.strip('"') + '"'
@r3 depends on c1 && c2 && c3@
expression c1.E1;
identifier c1.sysctls;
expression c2.E2;
identifier c2.base;
identifier c3.header;
fresh identifier E3 = script:python(E2, E1) { make_my_fresh_expression(E2, E1)
};
@@
header =
-register_sysctl_table(base);
+register_sysctl(E3, sysctls);
Generated-by: Coccinelle SmPL
Signed-off-by: Luis Chamberlain
---
drivers/cdrom/cdrom.c | 23 +--
1 file changed, 1 insertion(+), 22 deletions(-)
diff --git a/drivers/cdrom/cdrom.c b/drivers/cdrom/cdrom.c
index 9877e413fce3..1b57d4666e43 100644
--- a/drivers/cdrom/cdrom.c
+++ b/drivers/cdrom/cdrom.c
@@ -3691,27 +3691,6 @@ static struct ctl_table cdrom_table[] = {
},
{ }
};
-
-static struct ctl_table cdrom_cdrom_table[] = {
- {
- .procname = "cdrom",
- .maxlen = 0,
- .mode = 0555,
- .child = cdrom_table,
- },
- { }
-};
-
-/* Make sure that /proc/sys/dev is there */
-static struct ctl_table cdrom_root_table[] = {
- {
- .procname = "dev",
- .maxlen = 0,
- .mode = 0555,
- .child = cdrom_cdrom_table,
- },
- { }
-};
static struct ctl_table_header *cdrom_sysctl_header;
static void cdrom_sysctl_register(void)
@@ -3721,7 +3700,7 @@ static void cdrom_sysctl_register(void)
if (!atomic_add_unless(, 1, 1))
return;
- cdrom_sysctl_header = register_sysctl_table(cdrom_root_table);
+ cdrom_sysctl_header = register_sysctl("dev/cdrom", cdrom_table);
/* set the defaults */
cdrom_sysctl_settings.autoclose = autoclose;
--
2.33.0
[PATCH v2 8/8] eventpoll: simplify sysctl declaration with register_sysctl()
From: Xiaoming Ni
The kernel/sysctl.c is a kitchen sink where everyone leaves
their dirty dishes, this makes it very difficult to maintain.
To help with this maintenance let's start by moving sysctls to
places where they actually belong. The proc sysctl maintainers
do not want to know what sysctl knobs you wish to add for your own
piece of code, we just care about the core logic.
So move the epoll_table sysctl to fs/eventpoll.c and use
use register_sysctl().
Signed-off-by: Xiaoming Ni
Signed-off-by: Luis Chamberlain
---
fs/eventpoll.c | 10 +-
include/linux/poll.h | 2 --
include/linux/sysctl.h | 1 -
kernel/sysctl.c| 7 ---
4 files changed, 9 insertions(+), 11 deletions(-)
diff --git a/fs/eventpoll.c b/fs/eventpoll.c
index 06f4c5ae1451..e2daa940ebce 100644
--- a/fs/eventpoll.c
+++ b/fs/eventpoll.c
@@ -307,7 +307,7 @@ static void unlist_file(struct epitems_head *head)
static long long_zero;
static long long_max = LONG_MAX;
-struct ctl_table epoll_table[] = {
+static struct ctl_table epoll_table[] = {
{
.procname = "max_user_watches",
.data = _user_watches,
@@ -319,6 +319,13 @@ struct ctl_table epoll_table[] = {
},
{ }
};
+
+static void __init epoll_sysctls_init(void)
+{
+ register_sysctl("fs/epoll", epoll_table);
+}
+#else
+#define epoll_sysctls_init() do { } while (0)
#endif /* CONFIG_SYSCTL */
static const struct file_operations eventpoll_fops;
@@ -2378,6 +2385,7 @@ static int __init eventpoll_init(void)
/* Allocates slab cache used to allocate "struct eppoll_entry" */
pwq_cache = kmem_cache_create("eventpoll_pwq",
sizeof(struct eppoll_entry), 0, SLAB_PANIC|SLAB_ACCOUNT, NULL);
+ epoll_sysctls_init();
ephead_cache = kmem_cache_create("ep_head",
sizeof(struct epitems_head), 0, SLAB_PANIC|SLAB_ACCOUNT, NULL);
diff --git a/include/linux/poll.h b/include/linux/poll.h
index 1cdc32b1f1b0..a9e0e1c2d1f2 100644
--- a/include/linux/poll.h
+++ b/include/linux/poll.h
@@ -8,12 +8,10 @@
#include
#include
#include
-#include
#include
#include
#include
-extern struct ctl_table epoll_table[]; /* for sysctl */
/* ~832 bytes of stack space used max in sys_select/sys_poll before allocating
additional memory. */
#ifdef __clang__
diff --git a/include/linux/sysctl.h b/include/linux/sysctl.h
index 718492057c70..5e0428a71899 100644
--- a/include/linux/sysctl.h
+++ b/include/linux/sysctl.h
@@ -218,7 +218,6 @@ extern int no_unaligned_warning;
extern struct ctl_table sysctl_mount_point[];
extern struct ctl_table random_table[];
extern struct ctl_table firmware_config_table[];
-extern struct ctl_table epoll_table[];
#else /* CONFIG_SYSCTL */
static inline struct ctl_table_header *register_sysctl_table(struct ctl_table
* table)
diff --git a/kernel/sysctl.c b/kernel/sysctl.c
index 6aa67c737e4e..b09ff41720e3 100644
--- a/kernel/sysctl.c
+++ b/kernel/sysctl.c
@@ -3092,13 +3092,6 @@ static struct ctl_table fs_table[] = {
.proc_handler = proc_dointvec,
},
#endif
-#ifdef CONFIG_EPOLL
- {
- .procname = "epoll",
- .mode = 0555,
- .child = epoll_table,
- },
-#endif
#endif
{
.procname = "protected_symlinks",
--
2.33.0
[PATCH v2 4/8] ocfs2: simplify subdirectory registration with register_sysctl()
There is no need to user boiler plate code to specify a set of base
directories we're going to stuff sysctls under. Simplify this by using
register_sysctl() and specifying the directory path directly.
// pycocci sysctl-subdir-register-sysctl-simplify.cocci PATH
@c1@
expression E1;
identifier subdir, sysctls;
@@
static struct ctl_table subdir[] = {
{
.procname = E1,
.maxlen = 0,
.mode = 0555,
.child = sysctls,
},
{ }
};
@c2@
identifier c1.subdir;
expression E2;
identifier base;
@@
static struct ctl_table base[] = {
{
.procname = E2,
.maxlen = 0,
.mode = 0555,
.child = subdir,
},
{ }
};
@c3@
identifier c2.base;
identifier header;
@@
header = register_sysctl_table(base);
@r1 depends on c1 && c2 && c3@
expression c1.E1;
identifier c1.subdir, c1.sysctls;
@@
-static struct ctl_table subdir[] = {
- {
- .procname = E1,
- .maxlen = 0,
- .mode = 0555,
- .child = sysctls,
- },
- { }
-};
@r2 depends on c1 && c2 && c3@
identifier c1.subdir;
expression c2.E2;
identifier c2.base;
@@
-static struct ctl_table base[] = {
- {
- .procname = E2,
- .maxlen = 0,
- .mode = 0555,
- .child = subdir,
- },
- { }
-};
@initialize:python@
@@
def make_my_fresh_expression(s1, s2):
return '"' + s1.strip('"') + "/" + s2.strip('"') + '"'
@r3 depends on c1 && c2 && c3@
expression c1.E1;
identifier c1.sysctls;
expression c2.E2;
identifier c2.base;
identifier c3.header;
fresh identifier E3 = script:python(E2, E1) { make_my_fresh_expression(E2, E1)
};
@@
header =
-register_sysctl_table(base);
+register_sysctl(E3, sysctls);
Generated-by: Coccinelle SmPL
Signed-off-by: Luis Chamberlain
---
fs/ocfs2/stackglue.c | 25 +
1 file changed, 1 insertion(+), 24 deletions(-)
diff --git a/fs/ocfs2/stackglue.c b/fs/ocfs2/stackglue.c
index 16f1bfc407f2..731558a6f27d 100644
--- a/fs/ocfs2/stackglue.c
+++ b/fs/ocfs2/stackglue.c
@@ -672,31 +672,8 @@ static struct ctl_table ocfs2_mod_table[] = {
{ }
};
-static struct ctl_table ocfs2_kern_table[] = {
- {
- .procname = "ocfs2",
- .data = NULL,
- .maxlen = 0,
- .mode = 0555,
- .child = ocfs2_mod_table
- },
- { }
-};
-
-static struct ctl_table ocfs2_root_table[] = {
- {
- .procname = "fs",
- .data = NULL,
- .maxlen = 0,
- .mode = 0555,
- .child = ocfs2_kern_table
- },
- { }
-};
-
static struct ctl_table_header *ocfs2_table_header;
-
/*
* Initialization
*/
@@ -705,7 +682,7 @@ static int __init ocfs2_stack_glue_init(void)
{
strcpy(cluster_stack_name, OCFS2_STACK_PLUGIN_O2CB);
- ocfs2_table_header = register_sysctl_table(ocfs2_root_table);
+ ocfs2_table_header = register_sysctl("fs/ocfs2", ocfs2_mod_table);
if (!ocfs2_table_header) {
printk(KERN_ERR
"ocfs2 stack glue: unable to register sysctl\n");
--
2.33.0
[PATCH v2 2/8] i915: simplify subdirectory registration with register_sysctl()
There is no need to user boiler plate code to specify a set of base
directories we're going to stuff sysctls under. Simplify this by using
register_sysctl() and specifying the directory path directly.
// pycocci sysctl-subdir-register-sysctl-simplify.cocci PATH
@c1@
expression E1;
identifier subdir, sysctls;
@@
static struct ctl_table subdir[] = {
{
.procname = E1,
.maxlen = 0,
.mode = 0555,
.child = sysctls,
},
{ }
};
@c2@
identifier c1.subdir;
expression E2;
identifier base;
@@
static struct ctl_table base[] = {
{
.procname = E2,
.maxlen = 0,
.mode = 0555,
.child = subdir,
},
{ }
};
@c3@
identifier c2.base;
identifier header;
@@
header = register_sysctl_table(base);
@r1 depends on c1 && c2 && c3@
expression c1.E1;
identifier c1.subdir, c1.sysctls;
@@
-static struct ctl_table subdir[] = {
- {
- .procname = E1,
- .maxlen = 0,
- .mode = 0555,
- .child = sysctls,
- },
- { }
-};
@r2 depends on c1 && c2 && c3@
identifier c1.subdir;
expression c2.E2;
identifier c2.base;
@@
-static struct ctl_table base[] = {
- {
- .procname = E2,
- .maxlen = 0,
- .mode = 0555,
- .child = subdir,
- },
- { }
-};
@initialize:python@
@@
def make_my_fresh_expression(s1, s2):
return '"' + s1.strip('"') + "/" + s2.strip('"') + '"'
@r3 depends on c1 && c2 && c3@
expression c1.E1;
identifier c1.sysctls;
expression c2.E2;
identifier c2.base;
identifier c3.header;
fresh identifier E3 = script:python(E2, E1) { make_my_fresh_expression(E2, E1)
};
@@
header =
-register_sysctl_table(base);
+register_sysctl(E3, sysctls);
Generated-by: Coccinelle SmPL
Signed-off-by: Luis Chamberlain
---
drivers/gpu/drm/i915/i915_perf.c | 22 +-
1 file changed, 1 insertion(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 2f01b8c0284c..5979e3258647 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -4273,26 +4273,6 @@ static struct ctl_table oa_table[] = {
{}
};
-static struct ctl_table i915_root[] = {
- {
-.procname = "i915",
-.maxlen = 0,
-.mode = 0555,
-.child = oa_table,
-},
- {}
-};
-
-static struct ctl_table dev_root[] = {
- {
-.procname = "dev",
-.maxlen = 0,
-.mode = 0555,
-.child = i915_root,
-},
- {}
-};
-
static void oa_init_supported_formats(struct i915_perf *perf)
{
struct drm_i915_private *i915 = perf->i915;
@@ -4488,7 +4468,7 @@ static int destroy_config(int id, void *p, void *data)
int i915_perf_sysctl_register(void)
{
- sysctl_header = register_sysctl_table(dev_root);
+ sysctl_header = register_sysctl("dev/i915", oa_table);
return 0;
}
--
2.33.0
[PATCH v2 5/8] test_sysctl: simplify subdirectory registration with register_sysctl()
There is no need to user boiler plate code to specify a set of base
directories we're going to stuff sysctls under. Simplify this by using
register_sysctl() and specifying the directory path directly.
// pycocci sysctl-subdir-register-sysctl-simplify.cocci lib/test_sysctl.c
@c1@
expression E1;
identifier subdir, sysctls;
@@
static struct ctl_table subdir[] = {
{
.procname = E1,
.maxlen = 0,
.mode = 0555,
.child = sysctls,
},
{ }
};
@c2@
identifier c1.subdir;
expression E2;
identifier base;
@@
static struct ctl_table base[] = {
{
.procname = E2,
.maxlen = 0,
.mode = 0555,
.child = subdir,
},
{ }
};
@c3@
identifier c2.base;
identifier header;
@@
header = register_sysctl_table(base);
@r1 depends on c1 && c2 && c3@
expression c1.E1;
identifier c1.subdir, c1.sysctls;
@@
-static struct ctl_table subdir[] = {
- {
- .procname = E1,
- .maxlen = 0,
- .mode = 0555,
- .child = sysctls,
- },
- { }
-};
@r2 depends on c1 && c2 && c3@
identifier c1.subdir;
expression c2.E2;
identifier c2.base;
@@
-static struct ctl_table base[] = {
- {
- .procname = E2,
- .maxlen = 0,
- .mode = 0555,
- .child = subdir,
- },
- { }
-};
@initialize:python@
@@
def make_my_fresh_expression(s1, s2):
return '"' + s1.strip('"') + "/" + s2.strip('"') + '"'
@r3 depends on c1 && c2 && c3@
expression c1.E1;
identifier c1.sysctls;
expression c2.E2;
identifier c2.base;
identifier c3.header;
fresh identifier E3 = script:python(E2, E1) { make_my_fresh_expression(E2, E1)
};
@@
header =
-register_sysctl_table(base);
+register_sysctl(E3, sysctls);
Generated-by: Coccinelle SmPL
Signed-off-by: Luis Chamberlain
---
lib/test_sysctl.c | 22 +-
1 file changed, 1 insertion(+), 21 deletions(-)
diff --git a/lib/test_sysctl.c b/lib/test_sysctl.c
index 3750323973f4..a5a3d6c27e1f 100644
--- a/lib/test_sysctl.c
+++ b/lib/test_sysctl.c
@@ -128,26 +128,6 @@ static struct ctl_table test_table[] = {
{ }
};
-static struct ctl_table test_sysctl_table[] = {
- {
- .procname = "test_sysctl",
- .maxlen = 0,
- .mode = 0555,
- .child = test_table,
- },
- { }
-};
-
-static struct ctl_table test_sysctl_root_table[] = {
- {
- .procname = "debug",
- .maxlen = 0,
- .mode = 0555,
- .child = test_sysctl_table,
- },
- { }
-};
-
static struct ctl_table_header *test_sysctl_header;
static int __init test_sysctl_init(void)
@@ -155,7 +135,7 @@ static int __init test_sysctl_init(void)
test_data.bitmap_0001 = kzalloc(SYSCTL_TEST_BITMAP_SIZE/8, GFP_KERNEL);
if (!test_data.bitmap_0001)
return -ENOMEM;
- test_sysctl_header = register_sysctl_table(test_sysctl_root_table);
+ test_sysctl_header = register_sysctl("debug/test_sysctl", test_table);
if (!test_sysctl_header) {
kfree(test_data.bitmap_0001);
return -ENOMEM;
--
2.33.0
[PATCH v2 0/8] sysctl: second set of kernel/sysctl cleanups
This is the 2nd set of kernel/sysctl.c cleanups. The diff stat should reflect how this is a much better way to deal with theses. Fortunately coccinelle can be used to ensure correctness for most of these and/or future merge conflicts. Note that since this is part of a larger effort to cleanup kernel/sysctl.c I think we have no other option but to go with merging these patches in either Andrew's tree or keep them staged in a separate tree and send a merge request later. Otherwise kernel/sysctl.c will end up becoming a sore spot for the next merge window. Changes in this v2: * As suggested by Eric W. Biederman I dropped the subdir new call and just used the register_sysctl() by specifying the parent directory. * 0-day cleanups, commit log enhancements * Updated the coccinelle patch with register_sysctl() Luis Chamberlain (6): hpet: simplify subdirectory registration with register_sysctl() i915: simplify subdirectory registration with register_sysctl() macintosh/mac_hid.c: simplify subdirectory registration with register_sysctl() ocfs2: simplify subdirectory registration with register_sysctl() test_sysctl: simplify subdirectory registration with register_sysctl() cdrom: simplify subdirectory registration with register_sysctl() Xiaoming Ni (2): inotify: simplify subdirectory registration with register_sysctl() eventpoll: simplify sysctl declaration with register_sysctl() drivers/cdrom/cdrom.c| 23 +-- drivers/char/hpet.c | 22 +- drivers/gpu/drm/i915/i915_perf.c | 22 +- drivers/macintosh/mac_hid.c | 24 +--- fs/eventpoll.c | 10 +- fs/notify/inotify/inotify_user.c | 11 ++- fs/ocfs2/stackglue.c | 25 + include/linux/inotify.h | 3 --- include/linux/poll.h | 2 -- include/linux/sysctl.h | 1 - kernel/sysctl.c | 28 lib/test_sysctl.c| 22 +- 12 files changed, 25 insertions(+), 168 deletions(-) -- 2.33.0
Re: [WARN][AMDGPU] Linux 5.15.4 with AMD Bonaire GPU
On Sun, Nov 21, 2021 at 9:47 AM Chris Rankin wrote: > > Hi, > > i have found this warning in my vanilla 5.15.4 kernel's dmesg log: > > [ 87.687139] [ cut here ] > [ 87.710799] WARNING: CPU: 1 PID: 1 at > drivers/gpu/drm/ttm/ttm_bo.c:409 ttm_bo_release+0x1c/0x266 [ttm] > [ 87.718965] Modules linked in: nf_nat_ftp nf_conntrack_ftp cfg80211 > af_packet nft_fib_inet nft_fib_ipv4 nft_fib_ipv6 nft_fib > nft_reject_inet nf_reject_ipv4 nf_reject_ipv6 nft_reject nft_ct > nft_chain_nat nf_tables ebtable_nat ebtable_broute ip6table_nat > ip6table_mangle ip6table_raw ip6table_security iptable_nat nf_nat > nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4 libcrc32c iptable_mangle > iptable_raw iptable_security nfnetlink ebtable_filter ebtables > ip6table_filter ip6_tables iptable_filter bnep it87 hwmon_vid dm_mod > dax snd_hda_codec_realtek snd_hda_codec_generic ledtrig_audio > snd_hda_codec_hdmi snd_hda_intel uvcvideo videobuf2_vmalloc > videobuf2_memops snd_intel_dspcfg snd_hda_codec snd_usb_audio > snd_usbmidi_lib snd_hwdep videobuf2_v4l2 snd_virtuoso snd_oxygen_lib > videobuf2_common btusb snd_mpu401_uart input_leds snd_hda_core > videodev btbcm snd_rawmidi btintel joydev snd_seq mc led_class > bluetooth ecdh_generic rfkill snd_seq_device ecc snd_pcm r8169 > coretemp snd_hrtimer i2c_i801 psmouse > [ 87.719024] i2c_smbus pcspkr kvm_intel realtek kvm snd_timer > gpio_ich mdio_devres iTCO_wdt snd libphy mxm_wmi irqbypass soundcore > tiny_power_button lpc_ich i7core_edac acpi_cpufreq button wmi nfsd > auth_rpcgss nfs_acl lockd grace sunrpc binfmt_misc fuse configfs zram > zsmalloc ip_tables x_tables ext4 crc32c_generic crc16 mbcache jbd2 > hid_microsoft usbhid sr_mod cdrom sd_mod amdgpu uhci_hcd > drm_ttm_helper ehci_pci ttm mfd_core ehci_hcd gpu_sched xhci_pci > xhci_hcd i2c_algo_bit crc32c_intel serio_raw drm_kms_helper > firewire_ohci ahci libahci pata_jmicron firewire_core libata crc_itu_t > cfbfillrect syscopyarea cfbimgblt sysfillrect sysimgblt fb_sys_fops > cfbcopyarea cec rc_core scsi_mod usbcore drm bsg scsi_common > usb_common drm_panel_orientation_quirks ipmi_devintf ipmi_msghandler > msr sha256_ssse3 sha256_generic ipv6 crc_ccitt > [ 87.876267] CPU: 1 PID: 1 Comm: systemd Tainted: G I 5.15.4 > #1 > [ 87.882109] Hardware name: Gigabyte Technology Co., Ltd. > EX58-UD3R/EX58-UD3R, BIOS FB 05/04/2009 > [ 87.889800] RIP: 0010:ttm_bo_release+0x1c/0x266 [ttm] > [ 87.893615] Code: 44 89 e0 5b 5d 41 5c 41 5d 41 5e 41 5f c3 41 56 > 41 55 41 54 4c 8d a7 90 fe ff ff 55 53 83 7f 4c 00 48 89 fb 48 8b 6f > e8 74 02 <0f> 0b 80 7b 18 00 48 8b 43 88 0f 85 ac 00 00 00 4c 8d 6b 90 > 49 39 > [ 87.911829] RSP: 0018:c9023e00 EFLAGS: 00010202 > [ 87.915886] RAX: 0001 RBX: 888123a449c8 RCX: > 004c > [ 87.921825] RDX: 01f3 RSI: a02ee0e5 RDI: > 888123a449c8 > [ 87.927750] RBP: 88810d6652f0 R08: 0001 R09: > 0003 > [ 87.933869] R10: 4000 R11: 888109970600 R12: > 888123a44858 > [ 87.939767] R13: 888146e35ad0 R14: 888146dad6c0 R15: > > [ 87.945604] FS: 7f901262ab40() GS:888343c4() > knlGS: > [ 87.952390] CS: 0010 DS: ES: CR0: 80050033 > [ 87.956837] CR2: 55d9edfa8fa0 CR3: 00010218 CR4: > 06e0 > [ 87.962704] Call Trace: > [ 87.963876] > [ 87.964742] amdgpu_bo_unref+0x15/0x1e [amdgpu] > [ 87.968219] amdgpu_gem_object_free+0x2b/0x45 [amdgpu] > [ 87.972135] drm_gem_dmabuf_release+0x11/0x1a [drm] > [ 87.975792] dma_buf_release+0x36/0x7d > [ 87.978363] __dentry_kill+0xf5/0x12f > [ 87.980749] dput+0xfc/0x136 > [ 87.982386] __fput+0x17a/0x1cc > [ 87.984234] task_work_run+0x64/0x75 > [ 87.986615] exit_to_user_mode_prepare+0x88/0x112 > [ 87.990111] syscall_exit_to_user_mode+0x14/0x1f > [ 87.993513] do_syscall_64+0x7a/0x80 > [ 87.995873] entry_SYSCALL_64_after_hwframe+0x44/0xae > [ 87.999798] RIP: 0033:0x7f9013160fdb > [ 88.002129] Code: 03 00 00 00 0f 05 48 3d 00 f0 ff ff 77 41 c3 48 > 83 ec 18 89 7c 24 0c e8 33 81 f8 ff 8b 7c 24 0c 41 89 c0 b8 03 00 00 > 00 0f 05 <48> 3d 00 f0 ff ff 77 35 44 89 c7 89 44 24 0c e8 81 81 f8 ff > 8b 44 > [ 88.020215] RSP: 002b:7ffda9891d20 EFLAGS: 0293 ORIG_RAX: > 0003 > [ 88.026698] RAX: RBX: 7f901262a8f0 RCX: > 7f9013160fdb > [ 88.032789] RDX: RSI: 00055d9edfc6 RDI: > 0069 > [ 88.038864] RBP: 0069 R08: R09: > 007f > [ 88.045044] R10: R11: 0293 R12: > > [ 88.051033] R13: 55d9ecadd680 R14: 55d9eca96719 R15: > 55d9edf412f0 > [ 88.056868] > [ 88.057758] ---[ end trace bf3184763fd2083a ]--- > > I have seen a warning like this one in every dmesg log from 5.14.x > onwards, and it is clearly still
Re: [PATCH v8 0/8] MIPS: JZ4780 and CI20 HDMI
Hi Nikolaus, I think if you can fix the last few things I commented on, and I get an ACK from Rob for the Device Tree related patches, then it will be ready to merge. Cheers, -Paul Le mar., nov. 23 2021 at 19:13:53 +0100, H. Nikolaus Schaller a écrit : PATCH V8 2021-11-23 19:14:00: - fix a bad editing result from patch 2/8 (found by p...@crapouillou.net) PATCH V7 2021-11-23 18:46:23: - changed gpio polarity of hdmi_power to 0 (suggested by p...@crapouillou.net) - fixed LCD1 irq number (bug found by p...@crapouillou.net) - removed "- 4" for calculating max_register (suggested by p...@crapouillou.net) - use unevaluatedPropertes instead of additionalProperties (suggested by r...@kernel.org) - moved and renamed ingenic,jz4780-hdmi.yaml (suggested by r...@kernel.org) - adjusted assigned-clocks changes to upstream which added some for SSI (by h...@goldelico.com) - rebased and tested with v5.16-rc2 + patch set drm/ingenic by p...@crapouillou.net (by h...@goldelico.com) PATCH V6 2021-11-10 20:43:33: - changed CONFIG_DRM_INGENIC_DW_HDMI to "m" (by h...@goldelico.com) - made ingenic-dw-hdmi an independent platform driver which can be compiled as module and removed error patch fixes for IPU (suggested by p...@crapouillou.net) - moved assigned-clocks from jz4780.dtsi to ci20.dts (suggested by p...@crapouillou.net) - fixed reg property in jz4780.dtsi to cover all registers incl. gamma and vee (by h...@goldelico.com) - added a base patch to calculate regmap size from DTS reg property (requested by p...@crapouillou.net) - restored resetting all bits except one in LCDOSDC (requested by p...@crapouillou.net) - clarified setting of cpos (suggested by p...@crapouillou.net) - moved bindings definition for ddc-i2c-bus (suggested by p...@crapouillou.net) - simplified mask definitions for JZ_LCD_DESSIZE (requested by p...@crapouillou.net) - removed setting alpha premultiplication (suggested by p...@crapouillou.net) - removed some comments (suggested by p...@crapouillou.net) PATCH V5 2021-10-05 14:28:44: - dropped mode_fixup and timings support in dw-hdmi as it is no longer needed in this V5 (by h...@goldelico.com) - dropped "drm/ingenic: add some jz4780 specific features" (stimulated by p...@crapouillou.net) - fixed typo in commit subject: "synopsis" -> "synopsys" (by h...@goldelico.com) - swapped clocks in jz4780.dtsi to match synopsys,dw-hdmi.yaml (by h...@goldelico.com) - improved, simplified, fixed, dtbschecked ingenic-jz4780-hdmi.yaml and made dependent of bridge/synopsys,dw-hdmi.yaml (based on suggestions by max...@cerno.tech) - fixed binding vs. driver use of hdmi-5v regulator (suggested by max...@cerno.tech) - dropped "drm/bridge: synopsis: Fix to properly handle HPD" - was a no longer needed workaround for a previous version (suggested by max...@cerno.tech) PATCH V4 2021-09-27 18:44:38: - fix setting output_port = 1 (issue found by p...@crapouillou.net) - ci20.dts: convert to use hdmi-connector (by h...@goldelico.com) - add a hdmi-regulator to control +5V power (by h...@goldelico.com) - added a fix to dw-hdmi to call drm_kms_helper_hotplug_event on plugin event detection (by h...@goldelico.com) - always allocate extended descriptor but initialize only for jz4780 (by h...@goldelico.com) - updated to work on top of "[PATCH v3 0/6] drm/ingenic: Various improvements v3" (by p...@crapouillou.net) - rebased to v5.13-rc3 PATCH V3 2021-08-08 07:10:50: This series adds HDMI support for JZ4780 and CI20 board (and fixes one IPU related issue in registration error path) - [patch 1/8] switched from mode_fixup to atomic_check (suggested by robert.f...@linaro.org) - the call to the dw-hdmi specialization is still called mode_fixup - [patch 3/8] diverse fixes for ingenic-drm-drv (suggested by p...@crapouillou.net) - factor out some non-HDMI features of the jz4780 into a separate patch - multiple fixes around max height - do not change regmap config but a copy on stack - define some constants - factor out fixing of drm_init error path for IPU into separate patch - use FIELD_PREP() - [patch 8/8] conversion to component framework dropped (suggested by laurent.pinch...@ideasonboard.com and p...@crapouillou.net) PATCH V2 2021-08-05 16:08:05: - code and commit messages revisited for checkpatch warnings - rebased on v5.14-rc4 - include (failed, hence RFC 8/8) attempt to convert to component framework (was suggested by Paul Cercueil a while ago) This series adds HDMI support for JZ4780 and CI20 board H. Nikolaus Schaller (3): drm/ingenic: prepare ingenic drm for later addition of JZ4780 MIPS: defconfig: CI20: configure for DRM_DW_HDMI_JZ4780 [RFC] MIPS: DTS: Ingenic: adjust register size to available registers Paul Boddie (4): drm/ingenic: Add support for JZ4780 and HDMI output drm/ingenic: Add dw-hdmi driver for jz4780 MIPS: DTS: jz4780: Account for Synopsys HDMI driver and LCD controllers MIPS: DTS: CI20: Add DT nodes for HDMI setup
Re: [PATCH v8 6/8] MIPS: DTS: CI20: Add DT nodes for HDMI setup
Hi Nikolaus,
Le mar., nov. 23 2021 at 19:13:59 +0100, H. Nikolaus Schaller
a écrit :
From: Paul Boddie
We need to hook up
* HDMI connector
* HDMI power regulator
* JZ4780_CLK_HDMI @ 27 MHz
* DDC pinmux
* HDMI and LCDC endpoint connections
Signed-off-by: Paul Boddie
Signed-off-by: H. Nikolaus Schaller
---
arch/mips/boot/dts/ingenic/ci20.dts | 83
+++--
1 file changed, 80 insertions(+), 3 deletions(-)
diff --git a/arch/mips/boot/dts/ingenic/ci20.dts
b/arch/mips/boot/dts/ingenic/ci20.dts
index b249a4f0f6b62..15cf03670693f 100644
--- a/arch/mips/boot/dts/ingenic/ci20.dts
+++ b/arch/mips/boot/dts/ingenic/ci20.dts
@@ -78,6 +78,18 @@ eth0_power: fixedregulator@0 {
enable-active-high;
};
+ hdmi_out: connector {
+ compatible = "hdmi-connector";
+ label = "HDMI OUT";
+ type = "a";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <_hdmi_out>;
+ };
+ };
+ };
+
ir: ir {
compatible = "gpio-ir-receiver";
gpios = < 3 GPIO_ACTIVE_LOW>;
@@ -102,6 +114,17 @@ otg_power: fixedregulator@2 {
gpio = < 14 GPIO_ACTIVE_LOW>;
enable-active-high;
};
+
+ hdmi_power: fixedregulator@3 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "hdmi_power";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+
+ gpio = < 25 0>;
+ enable-active-high;
+ };
};
{
@@ -114,11 +137,13 @@ {
* precision.
*/
assigned-clocks = < JZ4780_CLK_OTGPHY>, < JZ4780_CLK_RTC>,
- < JZ4780_CLK_SSIPLL>, < JZ4780_CLK_SSI>;
+ < JZ4780_CLK_SSIPLL>, < JZ4780_CLK_SSI>,
+ < JZ4780_CLK_HDMI>;
assigned-clock-parents = <0>, < JZ4780_CLK_RTCLK>,
< JZ4780_CLK_MPLL>,
-< JZ4780_CLK_SSIPLL>;
- assigned-clock-rates = <4800>, <0>, <5400>;
+< JZ4780_CLK_SSIPLL>,
+<0>;
Nit - you can remove the last <0>, it will be the default.
+ assigned-clock-rates = <4800>, <0>, <5400>, <0>, <2700>;
};
{
@@ -509,6 +534,19 @@ pins_i2c4: i2c4 {
bias-disable;
};
+ pins_hdmi_ddc: hdmi_ddc {
+ function = "hdmi-ddc";
+ groups = "hdmi-ddc";
+ bias-disable;
+ };
+
+ /* switch to PF25 as gpio driving DDC_SDA low */
+ pins_hdmi_ddc_unwedge: hdmi_ddc {
+ function = "hdmi-ddc";
+ groups = "hdmi-ddc";
+ bias-disable;
+ };
Your pins_hdmi_ddc and pins_hdmi_ddc_unwedge are the exact same? You
could just use the former and pass it to both pinctrl-0 and pinctrl-1.
Cheers,
-Paul
+
pins_nemc: nemc {
function = "nemc";
groups = "nemc-data", "nemc-cle-ale", "nemc-rd-we",
"nemc-frd-fwe";
@@ -539,3 +577,42 @@ pins_mmc1: mmc1 {
bias-disable;
};
};
+
+ {
+ status = "okay";
+
+ pinctrl-names = "default", "unwedge";
+ pinctrl-0 = <_hdmi_ddc>;
+ pinctrl-1 = <_hdmi_ddc_unwedge>;
+
+ hdmi-5v-supply = <_power>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dw_hdmi_in: endpoint {
+ remote-endpoint = <_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dw_hdmi_out: endpoint {
+ remote-endpoint = <_con>;
+ };
+ };
+ };
+};
+
+ {
+ status = "okay";
+
+ port {
+ lcd_out: endpoint {
+ remote-endpoint = <_hdmi_in>;
+ };
+ };
+};
--
2.33.0
Re: [PATCH v8 4/8] drm/ingenic: Add dw-hdmi driver for jz4780
Hi Nikolaus,
I keep seeing a few things, sorry.
Le mar., nov. 23 2021 at 19:13:57 +0100, H. Nikolaus Schaller
a écrit :
From: Paul Boddie
A specialisation of the generic Synopsys HDMI driver is employed for
JZ4780 HDMI support. This requires a new driver, plus device tree and
configuration modifications.
Here we add Kconfig DRM_INGENIC_DW_HDMI, Makefile and driver code.
Signed-off-by: Paul Boddie
Signed-off-by: Ezequiel Garcia
Signed-off-by: H. Nikolaus Schaller
---
drivers/gpu/drm/ingenic/Kconfig | 9 ++
drivers/gpu/drm/ingenic/Makefile | 1 +
drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c | 129
++
3 files changed, 139 insertions(+)
create mode 100644 drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c
diff --git a/drivers/gpu/drm/ingenic/Kconfig
b/drivers/gpu/drm/ingenic/Kconfig
index 3b57f8be007c4..4efc709d77b0a 100644
--- a/drivers/gpu/drm/ingenic/Kconfig
+++ b/drivers/gpu/drm/ingenic/Kconfig
@@ -25,4 +25,13 @@ config DRM_INGENIC_IPU
The Image Processing Unit (IPU) will appear as a second primary
plane.
+config DRM_INGENIC_DW_HDMI
+ tristate "Ingenic specific support for Synopsys DW HDMI"
+ depends on MACH_JZ4780
+ select DRM_DW_HDMI
+ help
+ Choose this option to enable Synopsys DesignWare HDMI based
driver.
+ If you want to enable HDMI on Ingenic JZ4780 based SoC, you should
+ select this option..
+
endif
diff --git a/drivers/gpu/drm/ingenic/Makefile
b/drivers/gpu/drm/ingenic/Makefile
index d313326bdddbb..f10cc1c5a5f22 100644
--- a/drivers/gpu/drm/ingenic/Makefile
+++ b/drivers/gpu/drm/ingenic/Makefile
@@ -1,3 +1,4 @@
obj-$(CONFIG_DRM_INGENIC) += ingenic-drm.o
ingenic-drm-y = ingenic-drm-drv.o
ingenic-drm-$(CONFIG_DRM_INGENIC_IPU) += ingenic-ipu.o
+obj-$(CONFIG_DRM_INGENIC_DW_HDMI) += ingenic-dw-hdmi.o
diff --git a/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c
b/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c
new file mode 100644
index 0..c14890d6b9826
--- /dev/null
+++ b/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2019, 2020 Paul Boddie
+ *
+ * Derived from dw_hdmi-imx.c with i.MX portions removed.
+ * Probe and remove operations derived from rcar_dw_hdmi.c.
+ */
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+static const struct dw_hdmi_mpll_config ingenic_mpll_cfg[] = {
+ { 4525, { { 0x01e0, 0x }, { 0x21e1, 0x }, { 0x41e2,
0x } } },
+ { 9250, { { 0x0140, 0x0005 }, { 0x2141, 0x0005 }, { 0x4142,
0x0005 } } },
+ { 14850, { { 0x00a0, 0x000a }, { 0x20a1, 0x000a }, { 0x40a2,
0x000a } } },
+ { 21600, { { 0x00a0, 0x000a }, { 0x2001, 0x000f }, { 0x4002,
0x000f } } },
+ { ~0UL, { { 0x, 0x }, { 0x, 0x }, { 0x,
0x } } }
+};
+
+static const struct dw_hdmi_curr_ctrl ingenic_cur_ctr[] = {
+ /*pixelclk bpp8bpp10 bpp12 */
+ { 5400, { 0x091c, 0x091c, 0x06dc } },
+ { 5840, { 0x091c, 0x06dc, 0x06dc } },
+ { 7200, { 0x06dc, 0x06dc, 0x091c } },
+ { 7425, { 0x06dc, 0x0b5c, 0x091c } },
+ { 11880, { 0x091c, 0x091c, 0x06dc } },
+ { 21600, { 0x06dc, 0x0b5c, 0x091c } },
+ { ~0UL, { 0x, 0x, 0x } },
+};
+
+/*
+ * Resistance term 133Ohm Cfg
+ * PREEMP config 0.00
+ * TX/CK level 10
+ */
+static const struct dw_hdmi_phy_config ingenic_phy_config[] = {
+ /*pixelclk symbol term vlev */
+ { 21600, 0x800d, 0x0005, 0x01ad},
+ { ~0UL, 0x, 0x, 0x}
+};
+
+static enum drm_mode_status
+ingenic_dw_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data,
+ const struct drm_display_info *info,
+ const struct drm_display_mode *mode)
+{
+ if (mode->clock < 13500)
+ return MODE_CLOCK_LOW;
+ /* FIXME: Hardware is capable of 270MHz, but setup data is missing.
*/
+ if (mode->clock > 216000)
+ return MODE_CLOCK_HIGH;
+
+ return MODE_OK;
+}
+
+static struct dw_hdmi_plat_data ingenic_dw_hdmi_plat_data = {
+ .mpll_cfg = ingenic_mpll_cfg,
+ .cur_ctr= ingenic_cur_ctr,
+ .phy_config = ingenic_phy_config,
+ .mode_valid = ingenic_dw_hdmi_mode_valid,
+ .output_port= 1,
+};
+
+static const struct of_device_id ingenic_dw_hdmi_dt_ids[] = {
+ { .compatible = "ingenic,jz4780-dw-hdmi" },
+ { /* Sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, ingenic_dw_hdmi_dt_ids);
+
+static int ingenic_dw_hdmi_probe(struct platform_device *pdev)
+{
+ struct dw_hdmi *hdmi;
+ struct regulator *regulator;
+ int ret;
+
+ hdmi = dw_hdmi_probe(pdev, _dw_hdmi_plat_data);
+ if (IS_ERR(hdmi))
+ return PTR_ERR(hdmi);
+
+ platform_set_drvdata(pdev, hdmi);
+
+ regulator = devm_regulator_get_optional(>dev, "hdmi-5v");
+
Nit -
Re: [Intel-gfx] [PATCH 1/3] drm/i915/gt: Spread virtual engines over idle engines
On Tue, Nov 23, 2021 at 09:39:25AM +, Tvrtko Ursulin wrote:
>
> On 17/11/2021 22:49, Vinay Belgaumkar wrote:
> > From: Chris Wilson
> >
> > Everytime we come to the end of a virtual engine's context, re-randomise
> > it's siblings[]. As we schedule the siblings' tasklets in the order they
> > are in the array, earlier entries are executed first (when idle) and so
> > will be preferred when scheduling the next virtual request. Currently,
> > we only update the array when switching onto a new idle engine, so we
> > prefer to stick on the last execute engine, keeping the work compact.
> > However, it can be beneficial to spread the work out across idle
> > engines, so choose another sibling as our preferred target at the end of
> > the context's execution.
>
> This partially brings back, from a different angle, the more dynamic
> scheduling behavior which has been lost since bugfix 90a987205c6c
> ("drm/i915/gt: Only swap to a random sibling once upon creation").
Shouldn't we use the Fixes tag here since this is targeting to fix one
of the performance regressions of this patch?
>
> One day we could experiment with using engine busyness as criteria (instead
> of random). Back in the day busyness was kind of the best strategy, although
> sampled at submit, not at the trailing edge like here, but it still may be
> able to settle down to engine configuration better in some scenarios. Only
> testing could say.
>
> Still, from memory random also wasn't that bad so this should be okay for
> now.
>
> Reviewed-by: Tvrtko Ursulin
Since you reviewed and it looks to be a middle ground point in terms
of when to balancing (always like in the initial implementation vs
only once like the in 90a987205c6c).
If this one is really fixing the regression by itself:
Acked-by: Rodrigo Vivi
on this patch here.
But I still don't want to take the risk with touching the freq with
race to idle, until not convinced that it is absolutely needed and
that we are not breaking the world out there.
>
> Regards,
>
> Tvrtko
>
> > Signed-off-by: Chris Wilson
> > Cc: Vinay Belgaumkar
> > Cc: Tvrtko Ursulin
> > ---
> > .../drm/i915/gt/intel_execlists_submission.c | 80 ---
> > 1 file changed, 52 insertions(+), 28 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > index ca03880fa7e4..b95bbc8fb91a 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > @@ -539,6 +539,41 @@ static void execlists_schedule_in(struct i915_request
> > *rq, int idx)
> > GEM_BUG_ON(intel_context_inflight(ce) != rq->engine);
> > }
> > +static void virtual_xfer_context(struct virtual_engine *ve,
> > +struct intel_engine_cs *engine)
> > +{
> > + unsigned int n;
> > +
> > + if (likely(engine == ve->siblings[0]))
> > + return;
> > +
> > + if (!intel_engine_has_relative_mmio(engine))
> > + lrc_update_offsets(>context, engine);
> > +
> > + /*
> > +* Move the bound engine to the top of the list for
> > +* future execution. We then kick this tasklet first
> > +* before checking others, so that we preferentially
> > +* reuse this set of bound registers.
> > +*/
> > + for (n = 1; n < ve->num_siblings; n++) {
> > + if (ve->siblings[n] == engine) {
> > + swap(ve->siblings[n], ve->siblings[0]);
> > + break;
> > + }
> > + }
> > +}
> > +
> > +static int ve_random_sibling(struct virtual_engine *ve)
> > +{
> > + return prandom_u32_max(ve->num_siblings);
> > +}
> > +
> > +static int ve_random_other_sibling(struct virtual_engine *ve)
> > +{
> > + return 1 + prandom_u32_max(ve->num_siblings - 1);
> > +}
> > +
> > static void
> > resubmit_virtual_request(struct i915_request *rq, struct virtual_engine
> > *ve)
> > {
> > @@ -578,8 +613,23 @@ static void kick_siblings(struct i915_request *rq,
> > struct intel_context *ce)
> > rq->execution_mask != engine->mask)
> > resubmit_virtual_request(rq, ve);
> > - if (READ_ONCE(ve->request))
> > + /*
> > +* Reschedule with a new "preferred" sibling.
> > +*
> > +* The tasklets are executed in the order of ve->siblings[], so
> > +* siblings[0] receives preferrential treatment of greedily checking
> > +* for execution of the virtual engine. At this point, the virtual
> > +* engine is no longer in the current GPU cache due to idleness or
> > +* contention, so it can be executed on any without penalty. We
> > +* re-randomise at this point in order to spread light loads across
> > +* the system, heavy overlapping loads will continue to be greedily
> > +* executed by the first available engine.
> > +*/
> > + if (READ_ONCE(ve->request)) {
> > + virtual_xfer_context(ve,
> > +
Re: [PATCH v3 3/5] drm/i915/panelreplay: Initializaton and compute config for panel replay
On Sun, 2021-10-10 at 17:40 +0530, Animesh Manna wrote:
> As panel replay feature similar to PSR feature of EDP panel, so currently
> utilized existing psr framework for panel replay.
>
> v1: RFC version.
> v2: optimized code, pr_enabled and pr_dpcd variable removed. [Jose]
> v3:
> - code comments improved. [Jani]
> - dpcd_readb used instead of dpcd_read. [Jani]
> - panel-repaplay init/compute functions moved inside respective psr
> function. [Jani]
>
> Signed-off-by: Animesh Manna
> ---
> .../drm/i915/display/intel_display_types.h| 2 +
> drivers/gpu/drm/i915/display/intel_dp.c | 43 +
> drivers/gpu/drm/i915/display/intel_psr.c | 48 +++
> drivers/gpu/drm/i915/display/intel_psr.h | 3 ++
> 4 files changed, 87 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 39e11eaec1a3..48f7d676ed2c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1070,6 +1070,7 @@ struct intel_crtc_state {
> bool req_psr2_sdp_prior_scanline;
> u32 dc3co_exitline;
> u16 su_y_granularity;
> + bool has_panel_replay;
We can drop this and reuse current ones ones, see bellow.
> struct drm_dp_vsc_sdp psr_vsc;
>
> /*
> @@ -1531,6 +1532,7 @@ struct intel_psr {
> bool irq_aux_error;
> u16 su_w_granularity;
> u16 su_y_granularity;
> + bool sink_panel_replay_support;
move this closer to has_psr and set both when it is panel replay.
otherwise psr functions will not be executed for panel replay, see CAN_PSR().
> u32 dc3co_exitline;
> u32 dc3co_exit_delay;
> struct delayed_work dc3co_work;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 10fda20a5bd8..f58a7b72be14 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1587,12 +1587,22 @@ static void intel_dp_compute_vsc_colorimetry(const
> struct intel_crtc_state *crtc
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> - /*
> - * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> - * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> - * Colorimetry Format indication.
> - */
> - vsc->revision = 0x5;
> + if (crtc_state->has_panel_replay) {
> + /*
> + * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
> + * VSC SDP supporting 3D stereo, Panel Replay, and Pixel
> + * Encoding/Colorimetry Format indication.
> + */
> + vsc->revision = 0x7;
> + } else {
> + /*
> + * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> + * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> + * Colorimetry Format indication.
> + */
> + vsc->revision = 0x5;
> + }
> +
> vsc->length = 0x13;
>
> /* DP 1.4a spec, Table 2-120 */
> @@ -1701,6 +1711,21 @@ void intel_dp_compute_psr_vsc_sdp(struct intel_dp
> *intel_dp,
> vsc->revision = 0x4;
> vsc->length = 0xe;
> }
> + } else if (intel_dp->psr.enabled && !intel_dp_is_edp(intel_dp)) {
> + if (intel_dp->psr.colorimetry_support &&
> + intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> + /* [Panel Replay with colorimetry info] */
> + intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
> + vsc);
> + } else {
> + /*
> + * [Panel Replay without colorimetry info]
> + * Prepare VSC Header for SU as per DP 2.0 spec, Table
> 2-223
> + * VSC SDP supporting 3D stereo + Panel Replay.
> + */
> + vsc->revision = 0x6;
> + vsc->length = 0x10;
> + }
> } else {
> /*
>* [PSR1]
> @@ -2749,10 +2774,10 @@ static ssize_t intel_dp_vsc_sdp_pack(const struct
> drm_dp_vsc_sdp *vsc,
> sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
>
> /*
> - * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
> - * per DP 1.4a spec.
> + * Revision 0x5 and 0x7 supports Pixel Encoding/Colorimetry Format as
> + * per DP 1.4a spec and DP 2.0 spec respectively.
>*/
> - if (vsc->revision != 0x5)
> + if (vsc->revision != 0x5 || vsc->revision != 0x7)
> goto out;
>
> /* VSC SDP Payload for DB16 through DB18 */
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
>
Re: [PATCH v3 1/5] drm/i915/panelreplay: dpcd register definition for panelreplay
On Sun, 2021-10-10 at 17:40 +0530, Animesh Manna wrote: > DPCD register definition added to check and enable panel replay > capability of the sink. > > Signed-off-by: Animesh Manna > --- > include/drm/drm_dp_helper.h | 6 ++ > 1 file changed, 6 insertions(+) > > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > index b52df4db3e8f..8a2b929c3f88 100644 > --- a/include/drm/drm_dp_helper.h > +++ b/include/drm/drm_dp_helper.h > @@ -541,6 +541,9 @@ struct drm_panel; > /* DFP Capability Extension */ > #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ > > +#define DP_PANEL_REPLAY_CAP 0x0b0 > +# define PANEL_REPLAY_SUPPORT (1 << 0) Missing bit 1, that is very important when panel do not support selective update panel replay needs to act like PSR1 when it is sets it needs to act like PSR2. > + > /* Link Configuration */ > #define DP_LINK_BW_SET 0x100 > # define DP_LINK_RATE_TABLE 0x00/* eDP 1.4 */ > @@ -709,6 +712,9 @@ struct drm_panel; > #define DP_BRANCH_DEVICE_CTRL0x1a1 > # define DP_BRANCH_DEVICE_IRQ_HPD(1 << 0) > > +#define PANEL_REPLAY_CONFIG 0x1b0 > +# define PANEL_REPLAY_ENABLE(1 << 0) All other bits are also important, for the errors ones we have PSR counter parts and your are missing the error status register. > + > #define DP_PAYLOAD_ALLOCATE_SET 0x1c0 > #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1 > #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
Re: [PATCH] drm/nouveau/acr: fix a couple NULL vs IS_ERR() checks
Reviewed-by: Lyude Paul
Will push this to drm-misc in a bit
On Thu, 2021-11-18 at 14:13 +0300, Dan Carpenter wrote:
> The nvkm_acr_lsfw_add() function never returns NULL. It returns error
> pointers on error.
>
> Fixes: 22dcda45a3d1 ("drm/nouveau/acr: implement new subdev to replace
> "secure boot"")
> Signed-off-by: Dan Carpenter
> ---
> drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm200.c | 6 --
> drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp102.c | 6 --
> 2 files changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm200.c
> b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm200.c
> index cdb1ead26d84..82b4c8e1457c 100644
> --- a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm200.c
> +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm200.c
> @@ -207,11 +207,13 @@ int
> gm200_acr_wpr_parse(struct nvkm_acr *acr)
> {
> const struct wpr_header *hdr = (void *)acr->wpr_fw->data;
> + struct nvkm_acr_lsfw *lsfw;
>
> while (hdr->falcon_id != WPR_HEADER_V0_FALCON_ID_INVALID) {
> wpr_header_dump(>subdev, hdr);
> - if (!nvkm_acr_lsfw_add(NULL, acr, NULL, (hdr++)->falcon_id))
> - return -ENOMEM;
> + lsfw = nvkm_acr_lsfw_add(NULL, acr, NULL, (hdr++)-
> >falcon_id);
> + if (IS_ERR(lsfw))
> + return PTR_ERR(lsfw);
> }
>
> return 0;
> diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp102.c
> b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp102.c
> index fb9132a39bb1..fd97a935a380 100644
> --- a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp102.c
> +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp102.c
> @@ -161,11 +161,13 @@ int
> gp102_acr_wpr_parse(struct nvkm_acr *acr)
> {
> const struct wpr_header_v1 *hdr = (void *)acr->wpr_fw->data;
> + struct nvkm_acr_lsfw *lsfw;
>
> while (hdr->falcon_id != WPR_HEADER_V1_FALCON_ID_INVALID) {
> wpr_header_v1_dump(>subdev, hdr);
> - if (!nvkm_acr_lsfw_add(NULL, acr, NULL, (hdr++)->falcon_id))
> - return -ENOMEM;
> + lsfw = nvkm_acr_lsfw_add(NULL, acr, NULL, (hdr++)-
> >falcon_id);
> + if (IS_ERR(lsfw))
> + return PTR_ERR(lsfw);
> }
>
> return 0;
--
Cheers,
Lyude Paul (she/her)
Software Engineer at Red Hat
Re: [PATCH v2] drm/virtio: Fix an NULL vs IS_ERR() bug in virtio_gpu_object_shmem_init()
On Thu, Nov 18, 2021 at 3:16 AM Dan Carpenter wrote:
>
> The drm_gem_shmem_get_sg_table() function never returns NULL. It returns
> error pointers on error.
>
> Fixes: c66df701e783 ("drm/virtio: switch from ttm to gem shmem helpers")
> Signed-off-by: Dan Carpenter
> ---
> v2: I originally sent this patch on 19 Jun 2020 but it was somehow
> not applied. As I review it now, I see that the bug is actually
> older than I originally thought and so I have updated the Fixes
> tag.
Reviewed-by: Chia-I Wu
[PATCH v2] drm: change logs to print connectors in the form [CONNECTOR:id:name]
The preferred way to log connectors is [CONNECTOR:id:name]. Change it in
drm core programs. Also replace obsolete log calls (like DRM_DEBUG_*)
to the new ones (like drm_dbg_*)
Suggested-by: Ville Syrjälä
Signed-off-by: Claudio Suarez
---
drivers/gpu/drm/drm_client_modeset.c | 66 +---
drivers/gpu/drm/drm_connector.c | 24 +-
drivers/gpu/drm/drm_edid.c | 45 +++
drivers/gpu/drm/drm_edid_load.c | 21 +
drivers/gpu/drm/drm_mode_config.c| 3 +-
5 files changed, 95 insertions(+), 64 deletions(-)
diff --git a/drivers/gpu/drm/drm_client_modeset.c
b/drivers/gpu/drm/drm_client_modeset.c
index ced09c7c06f9..8df53b6e7687 100644
--- a/drivers/gpu/drm/drm_client_modeset.c
+++ b/drivers/gpu/drm/drm_client_modeset.c
@@ -240,8 +240,9 @@ static void drm_client_connectors_enabled(struct
drm_connector **connectors,
for (i = 0; i < connector_count; i++) {
connector = connectors[i];
enabled[i] = drm_connector_enabled(connector, true);
- DRM_DEBUG_KMS("connector %d enabled? %s\n", connector->base.id,
- connector->display_info.non_desktop ? "non
desktop" : enabled[i] ? "yes" : "no");
+ drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] enabled? %s\n",
+ connector->base.id, connector->name,
+ connector->display_info.non_desktop ? "non desktop"
: enabled[i] ? "yes" : "no");
any_enabled |= enabled[i];
}
@@ -350,8 +351,9 @@ static int drm_client_get_tile_offsets(struct drm_connector
**connectors,
continue;
if (!modes[i] && (h_idx || v_idx)) {
- DRM_DEBUG_KMS("no modes for connector tiled %d %d\n", i,
- connector->base.id);
+ drm_dbg_kms(connector->dev,
+ "[CONNECTOR:%d:%s]: no modes tiled %d\n",
+ connector->base.id, connector->name, i);
continue;
}
if (connector->tile_h_loc < h_idx)
@@ -419,14 +421,17 @@ static bool drm_client_target_preferred(struct
drm_connector **connectors,
drm_client_get_tile_offsets(connectors,
connector_count, modes, offsets, i,
connector->tile_h_loc,
connector->tile_v_loc);
}
- DRM_DEBUG_KMS("looking for cmdline mode on connector %d\n",
- connector->base.id);
+ drm_dbg_kms(connector->dev,
+ "[CONNECTOR:%d:%s]: looking for cmdline mode\n",
+ connector->base.id, connector->name);
/* got for command line mode first */
modes[i] = drm_connector_pick_cmdline_mode(connector);
if (!modes[i]) {
- DRM_DEBUG_KMS("looking for preferred mode on connector
%d %d\n",
- connector->base.id, connector->tile_group
? connector->tile_group->id : 0);
+ drm_dbg_kms(connector->dev,
+ "[CONNECTOR:%d:%s]: looking for preferred
mode %d\n",
+ connector->base.id, connector->name,
+ connector->tile_group ?
connector->tile_group->id : 0);
modes[i] = drm_connector_has_preferred_mode(connector,
width, height);
}
/* No preferred modes, pick one off the list */
@@ -448,8 +453,8 @@ static bool drm_client_target_preferred(struct
drm_connector **connectors,
(connector->tile_h_loc == 0 &&
connector->tile_v_loc == 0 &&
!drm_connector_get_tiled_mode(connector))) {
- DRM_DEBUG_KMS("Falling back to non tiled mode
on Connector %d\n",
- connector->base.id);
+ DRM_DEBUG_KMS("[CONNECTOR:%d:%s]: falling back
to non tiled mode\n",
+ connector->base.id,
connector->name);
modes[i] =
drm_connector_fallback_non_tiled_mode(connector);
} else {
modes[i] =
drm_connector_get_tiled_mode(connector);
@@ -617,15 +622,17 @@ static bool drm_client_firmware_config(struct
drm_client_dev *client,
num_connectors_detected++;
if (!enabled[i]) {
- DRM_DEBUG_KMS("connector %s not enabled, skipping\n",
- connector->name);
+ drm_dbg_kms(connector->dev,
+ "[CONNECTOR:%d:%s] not enabled, skipping\n",
+
Re: [PATCH v5 3/7] drm: sun4i: dsi: Convert to bridge driver
Hi Maxime,
On Mon, Nov 22, 2021 at 7:49 PM Jagan Teki wrote:
>
> Hi Maxime,
>
> On Mon, Nov 22, 2021 at 7:35 PM Maxime Ripard wrote:
> >
> > On Mon, Nov 22, 2021 at 07:18:13PM +0530, Jagan Teki wrote:
> > > Hi Maxime,
> > >
> > > On Mon, Nov 22, 2021 at 3:37 PM Maxime Ripard wrote:
> > > >
> > > > On Mon, Nov 22, 2021 at 12:22:19PM +0530, Jagan Teki wrote:
> > > > > Some display panels would come up with a non-DSI output, those
> > > > > can have an option to connect the DSI host by means of interface
> > > > > bridge converter.
> > > > >
> > > > > This DSI to non-DSI interface bridge converter would requires
> > > > > DSI Host to handle drm bridge functionalities in order to DSI
> > > > > Host to Interface bridge.
> > > >
> > > > In order to do this you would need to use the DRM bridge API...
> > >
> > > Sorry, which bridge API do you mean?
> >
> > Any variant of of_drm_find_bridge, and drm_bridge_attach. Just like
> > we're doing in sun4i_rgb.c
>
> Yes, we have drm_bridge_attach in bind and bridge_function.attach
> calls in this patch and of_drm_find_bridge in sun6i_mipi_dsi_attach.
> Not sure which API's I've missed.
>
> >
> > > > > This patch convert the existing to a drm bridge driver with a
> > > > > built-in encoder support for compatibility with existing
> > > > > component drivers.
> > > >
> > > > ... but changing the encoder driver to a bridge is completely
> > > > unnecessary to do so. Why did you need to make that change?
> > >
> > > Idea of this series is to convert the driver to bridge and use the
> > > latest bridge function from the v1 series.
> >
> > Ok, but it's not at all what you mention in your commit log? You don't
> > need any of that in order to support a bridge downstream.
>
> I've mentioned "Converting to bridge driver" and thought it has
> meaning of converting encoder related function to bridge functions as
> well. Not think about specific description to describe on commit
> message. Will update this.
>
> >
> > > >
> > > > > Signed-off-by: Jagan Teki
> > > > >
> > > > > ---
> > > > > Changes for v5:
> > > > > - add atomic APIs
> > > > > - find host and device variant DSI devices.
> > > > > Changes for v4, v3:
> > > > > - none
> > > > >
> > > > > drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 112
> > > > > -
> > > > > drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h | 7 ++
> > > > > 2 files changed, 96 insertions(+), 23 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
> > > > > b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
> > > > > index 43d9c9e5198d..a6a272b55f77 100644
> > > > > --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
> > > > > +++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
> > > > > @@ -21,6 +21,7 @@
> > > > >
> > > > > #include
> > > > > #include
> > > > > +#include
> > > > > #include
> > > > > #include
> > > > > #include
> > > > > @@ -713,10 +714,11 @@ static int sun6i_dsi_start(struct sun6i_dsi
> > > > > *dsi,
> > > > > return 0;
> > > > > }
> > > > >
> > > > > -static void sun6i_dsi_encoder_enable(struct drm_encoder *encoder)
> > > > > +static void sun6i_dsi_bridge_atomic_enable(struct drm_bridge *bridge,
> > > > > +struct drm_bridge_state
> > > > > *old_bridge_state)
> > > > > {
> > > > > - struct drm_display_mode *mode =
> > > > > >crtc->state->adjusted_mode;
> > > > > - struct sun6i_dsi *dsi = encoder_to_sun6i_dsi(encoder);
> > > > > + struct sun6i_dsi *dsi = bridge_to_sun6i_dsi(bridge);
> > > > > + struct drm_display_mode *mode =
> > > > > >encoder->crtc->state->adjusted_mode;
> > > > > struct mipi_dsi_device *device = dsi->device;
> > > > > union phy_configure_opts opts = { };
> > > > > struct phy_configure_opts_mipi_dphy *cfg = _dphy;
> > > > > @@ -772,6 +774,9 @@ static void sun6i_dsi_encoder_enable(struct
> > > > > drm_encoder *encoder)
> > > > > if (dsi->panel)
> > > > > drm_panel_prepare(dsi->panel);
> > > > >
> > > > > + if (dsi->next_bridge)
> > > > > +
> > > > > dsi->next_bridge->funcs->atomic_pre_enable(dsi->next_bridge,
> > > > > old_bridge_state);
> > > > > +
> > > >
> > > > Please use the proper helpers.
> > >
> > > If we use bridge_functions we need to take atomic functions as
> > > precedence as the next bridge functions might convert atomic calls.
> >
> > We've had this discussion over and over again, but this is something
> > that needs to be documented and / or in your commit log.
> >
> > You must not deviate from the standard (and expected) behavior without
> > any kind of justification.
>
> Not exactly sure about what you mean, sorry. All these atomic bridge
> functions are already documented if I'm not wrong and Laurent have
> patches to switch the normal functions to atomic. Not sure what else
> need to document here and need justification for it if the driver is
> converting to bridge.
>
> >
> > > >
> > > > > /*
> > > > >* FIXME: This should be
[PATCH v8 2/8] drm/ingenic: Add support for JZ4780 and HDMI output
From: Paul Boddie
Add support for the LCD controller present on JZ4780 SoCs.
This SoC uses 8-byte descriptors which extend the current
4-byte descriptors used for other Ingenic SoCs.
Tested on MIPS Creator CI20 board.
Signed-off-by: Paul Boddie
Signed-off-by: Ezequiel Garcia
Signed-off-by: H. Nikolaus Schaller
---
drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 53 +++
drivers/gpu/drm/ingenic/ingenic-drm.h | 38
2 files changed, 91 insertions(+)
diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
index 0bb590c3910d9..34089bc6e0fcd 100644
--- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
+++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
@@ -6,6 +6,7 @@
#include "ingenic-drm.h"
+#include
#include
#include
#include
@@ -49,6 +50,11 @@ struct ingenic_dma_hwdesc {
u32 addr;
u32 id;
u32 cmd;
+ /* extended hw descriptor for jz4780 */
+ u32 offsize;
+ u32 pagewidth;
+ u32 cpos;
+ u32 dessize;
} __aligned(16);
struct ingenic_dma_hwdescs {
@@ -60,6 +66,7 @@ struct jz_soc_info {
bool needs_dev_clk;
bool has_osd;
bool map_noncoherent;
+ bool use_extended_hwdesc;
unsigned int max_width, max_height;
const u32 *formats_f0, *formats_f1;
unsigned int num_formats_f0, num_formats_f1;
@@ -446,6 +453,9 @@ static int ingenic_drm_plane_atomic_check(struct drm_plane
*plane,
if (!crtc)
return 0;
+ if (plane == >f0)
+ return -EINVAL;
+
crtc_state = drm_atomic_get_existing_crtc_state(state,
crtc);
if (WARN_ON(!crtc_state))
@@ -662,6 +672,33 @@ static void ingenic_drm_plane_atomic_update(struct
drm_plane *plane,
hwdesc->cmd = JZ_LCD_CMD_EOF_IRQ | (width * height * cpp / 4);
hwdesc->next = dma_hwdesc_addr(priv, next_id);
+ if (priv->soc_info->use_extended_hwdesc) {
+ hwdesc->cmd |= JZ_LCD_CMD_FRM_ENABLE;
+
+ /* Extended 8-byte descriptor */
+ hwdesc->cpos = 0;
+ hwdesc->offsize = 0;
+ hwdesc->pagewidth = 0;
+
+ switch (newstate->fb->format->format) {
+ case DRM_FORMAT_XRGB1555:
+ hwdesc->cpos |= JZ_LCD_CPOS_RGB555;
+ fallthrough;
+ case DRM_FORMAT_RGB565:
+ hwdesc->cpos |= JZ_LCD_CPOS_BPP_15_16;
+ break;
+ case DRM_FORMAT_XRGB:
+ hwdesc->cpos |= JZ_LCD_CPOS_BPP_18_24;
+ break;
+ }
+ hwdesc->cpos |= (JZ_LCD_CPOS_COEFFICIENT_1 <<
+JZ_LCD_CPOS_COEFFICIENT_OFFSET);
+ hwdesc->dessize =
+ (0xff << JZ_LCD_DESSIZE_ALPHA_OFFSET) |
+ FIELD_PREP(JZ_LCD_DESSIZE_HEIGHT_MASK, height -
1) |
+ FIELD_PREP(JZ_LCD_DESSIZE_WIDTH_MASK, width -
1);
+ }
+
if (drm_atomic_crtc_needs_modeset(crtc_state)) {
fourcc = newstate->fb->format->format;
@@ -693,6 +730,9 @@ static void ingenic_drm_encoder_atomic_mode_set(struct
drm_encoder *encoder,
| JZ_LCD_CFG_SPL_DISABLE | JZ_LCD_CFG_REV_DISABLE;
}
+ if (priv->soc_info->use_extended_hwdesc)
+ cfg |= JZ_LCD_CFG_DESCRIPTOR_8;
+
if (mode->flags & DRM_MODE_FLAG_NHSYNC)
cfg |= JZ_LCD_CFG_HSYNC_ACTIVE_LOW;
if (mode->flags & DRM_MODE_FLAG_NVSYNC)
@@ -1468,10 +1508,23 @@ static const struct jz_soc_info jz4770_soc_info = {
.num_formats_f0 = ARRAY_SIZE(jz4770_formats_f0),
};
+static const struct jz_soc_info jz4780_soc_info = {
+ .needs_dev_clk = true,
+ .has_osd = true,
+ .use_extended_hwdesc = true,
+ .max_width = 4096,
+ .max_height = 2048,
+ .formats_f1 = jz4770_formats_f1,
+ .num_formats_f1 = ARRAY_SIZE(jz4770_formats_f1),
+ .formats_f0 = jz4770_formats_f0,
+ .num_formats_f0 = ARRAY_SIZE(jz4770_formats_f0),
+};
+
static const struct of_device_id ingenic_drm_of_match[] = {
{ .compatible = "ingenic,jz4740-lcd", .data = _soc_info },
{ .compatible = "ingenic,jz4725b-lcd", .data = _soc_info },
{ .compatible = "ingenic,jz4770-lcd", .data = _soc_info },
+ { .compatible = "ingenic,jz4780-lcd", .data = _soc_info },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, ingenic_drm_of_match);
diff --git a/drivers/gpu/drm/ingenic/ingenic-drm.h
b/drivers/gpu/drm/ingenic/ingenic-drm.h
index 22654ac1dde1c..cb1d09b625881 100644
---
[PATCH v8 4/8] drm/ingenic: Add dw-hdmi driver for jz4780
From: Paul Boddie
A specialisation of the generic Synopsys HDMI driver is employed for
JZ4780 HDMI support. This requires a new driver, plus device tree and
configuration modifications.
Here we add Kconfig DRM_INGENIC_DW_HDMI, Makefile and driver code.
Signed-off-by: Paul Boddie
Signed-off-by: Ezequiel Garcia
Signed-off-by: H. Nikolaus Schaller
---
drivers/gpu/drm/ingenic/Kconfig | 9 ++
drivers/gpu/drm/ingenic/Makefile | 1 +
drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c | 129 ++
3 files changed, 139 insertions(+)
create mode 100644 drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c
diff --git a/drivers/gpu/drm/ingenic/Kconfig b/drivers/gpu/drm/ingenic/Kconfig
index 3b57f8be007c4..4efc709d77b0a 100644
--- a/drivers/gpu/drm/ingenic/Kconfig
+++ b/drivers/gpu/drm/ingenic/Kconfig
@@ -25,4 +25,13 @@ config DRM_INGENIC_IPU
The Image Processing Unit (IPU) will appear as a second primary plane.
+config DRM_INGENIC_DW_HDMI
+ tristate "Ingenic specific support for Synopsys DW HDMI"
+ depends on MACH_JZ4780
+ select DRM_DW_HDMI
+ help
+ Choose this option to enable Synopsys DesignWare HDMI based driver.
+ If you want to enable HDMI on Ingenic JZ4780 based SoC, you should
+ select this option..
+
endif
diff --git a/drivers/gpu/drm/ingenic/Makefile b/drivers/gpu/drm/ingenic/Makefile
index d313326bdddbb..f10cc1c5a5f22 100644
--- a/drivers/gpu/drm/ingenic/Makefile
+++ b/drivers/gpu/drm/ingenic/Makefile
@@ -1,3 +1,4 @@
obj-$(CONFIG_DRM_INGENIC) += ingenic-drm.o
ingenic-drm-y = ingenic-drm-drv.o
ingenic-drm-$(CONFIG_DRM_INGENIC_IPU) += ingenic-ipu.o
+obj-$(CONFIG_DRM_INGENIC_DW_HDMI) += ingenic-dw-hdmi.o
diff --git a/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c
b/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c
new file mode 100644
index 0..c14890d6b9826
--- /dev/null
+++ b/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2019, 2020 Paul Boddie
+ *
+ * Derived from dw_hdmi-imx.c with i.MX portions removed.
+ * Probe and remove operations derived from rcar_dw_hdmi.c.
+ */
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+static const struct dw_hdmi_mpll_config ingenic_mpll_cfg[] = {
+ { 4525, { { 0x01e0, 0x }, { 0x21e1, 0x }, { 0x41e2, 0x
} } },
+ { 9250, { { 0x0140, 0x0005 }, { 0x2141, 0x0005 }, { 0x4142, 0x0005
} } },
+ { 14850, { { 0x00a0, 0x000a }, { 0x20a1, 0x000a }, { 0x40a2, 0x000a
} } },
+ { 21600, { { 0x00a0, 0x000a }, { 0x2001, 0x000f }, { 0x4002, 0x000f
} } },
+ { ~0UL, { { 0x, 0x }, { 0x, 0x }, { 0x, 0x
} } }
+};
+
+static const struct dw_hdmi_curr_ctrl ingenic_cur_ctr[] = {
+ /*pixelclk bpp8bpp10 bpp12 */
+ { 5400, { 0x091c, 0x091c, 0x06dc } },
+ { 5840, { 0x091c, 0x06dc, 0x06dc } },
+ { 7200, { 0x06dc, 0x06dc, 0x091c } },
+ { 7425, { 0x06dc, 0x0b5c, 0x091c } },
+ { 11880, { 0x091c, 0x091c, 0x06dc } },
+ { 21600, { 0x06dc, 0x0b5c, 0x091c } },
+ { ~0UL, { 0x, 0x, 0x } },
+};
+
+/*
+ * Resistance term 133Ohm Cfg
+ * PREEMP config 0.00
+ * TX/CK level 10
+ */
+static const struct dw_hdmi_phy_config ingenic_phy_config[] = {
+ /*pixelclk symbol term vlev */
+ { 21600, 0x800d, 0x0005, 0x01ad},
+ { ~0UL, 0x, 0x, 0x}
+};
+
+static enum drm_mode_status
+ingenic_dw_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data,
+ const struct drm_display_info *info,
+ const struct drm_display_mode *mode)
+{
+ if (mode->clock < 13500)
+ return MODE_CLOCK_LOW;
+ /* FIXME: Hardware is capable of 270MHz, but setup data is missing. */
+ if (mode->clock > 216000)
+ return MODE_CLOCK_HIGH;
+
+ return MODE_OK;
+}
+
+static struct dw_hdmi_plat_data ingenic_dw_hdmi_plat_data = {
+ .mpll_cfg = ingenic_mpll_cfg,
+ .cur_ctr= ingenic_cur_ctr,
+ .phy_config = ingenic_phy_config,
+ .mode_valid = ingenic_dw_hdmi_mode_valid,
+ .output_port= 1,
+};
+
+static const struct of_device_id ingenic_dw_hdmi_dt_ids[] = {
+ { .compatible = "ingenic,jz4780-dw-hdmi" },
+ { /* Sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, ingenic_dw_hdmi_dt_ids);
+
+static int ingenic_dw_hdmi_probe(struct platform_device *pdev)
+{
+ struct dw_hdmi *hdmi;
+ struct regulator *regulator;
+ int ret;
+
+ hdmi = dw_hdmi_probe(pdev, _dw_hdmi_plat_data);
+ if (IS_ERR(hdmi))
+ return PTR_ERR(hdmi);
+
+ platform_set_drvdata(pdev, hdmi);
+
+ regulator = devm_regulator_get_optional(>dev, "hdmi-5v");
+
+ if (IS_ERR(regulator)) {
+ ret = PTR_ERR(regulator);
+
+
[PATCH v8 6/8] MIPS: DTS: CI20: Add DT nodes for HDMI setup
From: Paul Boddie
We need to hook up
* HDMI connector
* HDMI power regulator
* JZ4780_CLK_HDMI @ 27 MHz
* DDC pinmux
* HDMI and LCDC endpoint connections
Signed-off-by: Paul Boddie
Signed-off-by: H. Nikolaus Schaller
---
arch/mips/boot/dts/ingenic/ci20.dts | 83 +++--
1 file changed, 80 insertions(+), 3 deletions(-)
diff --git a/arch/mips/boot/dts/ingenic/ci20.dts
b/arch/mips/boot/dts/ingenic/ci20.dts
index b249a4f0f6b62..15cf03670693f 100644
--- a/arch/mips/boot/dts/ingenic/ci20.dts
+++ b/arch/mips/boot/dts/ingenic/ci20.dts
@@ -78,6 +78,18 @@ eth0_power: fixedregulator@0 {
enable-active-high;
};
+ hdmi_out: connector {
+ compatible = "hdmi-connector";
+ label = "HDMI OUT";
+ type = "a";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <_hdmi_out>;
+ };
+ };
+ };
+
ir: ir {
compatible = "gpio-ir-receiver";
gpios = < 3 GPIO_ACTIVE_LOW>;
@@ -102,6 +114,17 @@ otg_power: fixedregulator@2 {
gpio = < 14 GPIO_ACTIVE_LOW>;
enable-active-high;
};
+
+ hdmi_power: fixedregulator@3 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "hdmi_power";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+
+ gpio = < 25 0>;
+ enable-active-high;
+ };
};
{
@@ -114,11 +137,13 @@ {
* precision.
*/
assigned-clocks = < JZ4780_CLK_OTGPHY>, < JZ4780_CLK_RTC>,
- < JZ4780_CLK_SSIPLL>, < JZ4780_CLK_SSI>;
+ < JZ4780_CLK_SSIPLL>, < JZ4780_CLK_SSI>,
+ < JZ4780_CLK_HDMI>;
assigned-clock-parents = <0>, < JZ4780_CLK_RTCLK>,
< JZ4780_CLK_MPLL>,
-< JZ4780_CLK_SSIPLL>;
- assigned-clock-rates = <4800>, <0>, <5400>;
+< JZ4780_CLK_SSIPLL>,
+<0>;
+ assigned-clock-rates = <4800>, <0>, <5400>, <0>, <2700>;
};
{
@@ -509,6 +534,19 @@ pins_i2c4: i2c4 {
bias-disable;
};
+ pins_hdmi_ddc: hdmi_ddc {
+ function = "hdmi-ddc";
+ groups = "hdmi-ddc";
+ bias-disable;
+ };
+
+ /* switch to PF25 as gpio driving DDC_SDA low */
+ pins_hdmi_ddc_unwedge: hdmi_ddc {
+ function = "hdmi-ddc";
+ groups = "hdmi-ddc";
+ bias-disable;
+ };
+
pins_nemc: nemc {
function = "nemc";
groups = "nemc-data", "nemc-cle-ale", "nemc-rd-we",
"nemc-frd-fwe";
@@ -539,3 +577,42 @@ pins_mmc1: mmc1 {
bias-disable;
};
};
+
+ {
+ status = "okay";
+
+ pinctrl-names = "default", "unwedge";
+ pinctrl-0 = <_hdmi_ddc>;
+ pinctrl-1 = <_hdmi_ddc_unwedge>;
+
+ hdmi-5v-supply = <_power>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dw_hdmi_in: endpoint {
+ remote-endpoint = <_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dw_hdmi_out: endpoint {
+ remote-endpoint = <_con>;
+ };
+ };
+ };
+};
+
+ {
+ status = "okay";
+
+ port {
+ lcd_out: endpoint {
+ remote-endpoint = <_hdmi_in>;
+ };
+ };
+};
--
2.33.0
[PATCH v8 5/8] MIPS: DTS: jz4780: Account for Synopsys HDMI driver and LCD controllers
From: Paul Boddie
A specialisation of the generic Synopsys HDMI driver is employed for
JZ4780 HDMI support. This requires a new driver, plus device tree and
configuration modifications.
Here we add jz4780 device tree setup.
Signed-off-by: Paul Boddie
Signed-off-by: H. Nikolaus Schaller
---
arch/mips/boot/dts/ingenic/jz4780.dtsi | 40 ++
1 file changed, 40 insertions(+)
diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi
b/arch/mips/boot/dts/ingenic/jz4780.dtsi
index b0a4e2e019c36..3f9ea47a10cd2 100644
--- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
@@ -444,6 +444,46 @@ i2c4: i2c@10054000 {
status = "disabled";
};
+ hdmi: hdmi@1018 {
+ compatible = "ingenic,jz4780-dw-hdmi";
+ reg = <0x1018 0x8000>;
+ reg-io-width = <4>;
+
+ clocks = < JZ4780_CLK_AHB0>, < JZ4780_CLK_HDMI>;
+ clock-names = "iahb", "isfr";
+
+ interrupt-parent = <>;
+ interrupts = <3>;
+
+ status = "disabled";
+ };
+
+ lcdc0: lcdc0@1305 {
+ compatible = "ingenic,jz4780-lcd";
+ reg = <0x1305 0x1800>;
+
+ clocks = < JZ4780_CLK_TVE>, < JZ4780_CLK_LCD0PIXCLK>;
+ clock-names = "lcd", "lcd_pclk";
+
+ interrupt-parent = <>;
+ interrupts = <31>;
+
+ status = "disabled";
+ };
+
+ lcdc1: lcdc1@130a {
+ compatible = "ingenic,jz4780-lcd";
+ reg = <0x130a 0x1800>;
+
+ clocks = < JZ4780_CLK_TVE>, < JZ4780_CLK_LCD1PIXCLK>;
+ clock-names = "lcd", "lcd_pclk";
+
+ interrupt-parent = <>;
+ interrupts = <23>;
+
+ status = "disabled";
+ };
+
nemc: nemc@1341 {
compatible = "ingenic,jz4780-nemc", "simple-mfd";
reg = <0x1341 0x1>;
--
2.33.0
[PATCH v8 8/8] [RFC] MIPS: DTS: Ingenic: adjust register size to available registers
After getting the regmap size from the device tree we should
reduce the ranges to the really available registers. This
allows to read only existing registers from the debug fs
and makes the regmap check out-of-bounds access.
For the jz4780 we have done this already.
Suggested-for: Paul Cercueil
Signed-off-by: H. Nikolaus Schaller
---
arch/mips/boot/dts/ingenic/jz4725b.dtsi | 2 +-
arch/mips/boot/dts/ingenic/jz4740.dtsi | 2 +-
arch/mips/boot/dts/ingenic/jz4770.dtsi | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/mips/boot/dts/ingenic/jz4725b.dtsi
b/arch/mips/boot/dts/ingenic/jz4725b.dtsi
index 0c6a5a4266f43..e9e48022f6316 100644
--- a/arch/mips/boot/dts/ingenic/jz4725b.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4725b.dtsi
@@ -321,7 +321,7 @@ udc: usb@1304 {
lcd: lcd-controller@1305 {
compatible = "ingenic,jz4725b-lcd";
- reg = <0x1305 0x1000>;
+ reg = <0x1305 0x130>; /* tbc */
interrupt-parent = <>;
interrupts = <31>;
diff --git a/arch/mips/boot/dts/ingenic/jz4740.dtsi
b/arch/mips/boot/dts/ingenic/jz4740.dtsi
index 772542e1f266a..7f76cba03a089 100644
--- a/arch/mips/boot/dts/ingenic/jz4740.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4740.dtsi
@@ -323,7 +323,7 @@ udc: usb@1304 {
lcd: lcd-controller@1305 {
compatible = "ingenic,jz4740-lcd";
- reg = <0x1305 0x1000>;
+ reg = <0x1305 0x60>; /* LCDCMD1+4 */
interrupt-parent = <>;
interrupts = <30>;
diff --git a/arch/mips/boot/dts/ingenic/jz4770.dtsi
b/arch/mips/boot/dts/ingenic/jz4770.dtsi
index dfe74328ae5dc..bda0a3a86ed5f 100644
--- a/arch/mips/boot/dts/ingenic/jz4770.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4770.dtsi
@@ -399,7 +399,7 @@ gpu: gpu@1304 {
lcd: lcd-controller@1305 {
compatible = "ingenic,jz4770-lcd";
- reg = <0x1305 0x300>;
+ reg = <0x1305 0x130>; /* tbc */
interrupt-parent = <>;
interrupts = <31>;
--
2.33.0
[PATCH v8 3/8] dt-bindings: display: Add ingenic, jz4780-dw-hdmi DT Schema
From: Sam Ravnborg
Add DT bindings for the hdmi driver for the Ingenic JZ4780 SoC.
Based on .txt binding from Zubair Lutfullah Kakakhel
We also add generic ddc-i2c-bus to synopsys,dw-hdmi.yaml
Signed-off-by: Sam Ravnborg
Signed-off-by: H. Nikolaus Schaller
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
---
.../display/bridge/ingenic,jz4780-hdmi.yaml | 76 +++
.../display/bridge/synopsys,dw-hdmi.yaml | 3 +
2 files changed, 79 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/ingenic,jz4780-hdmi.yaml
diff --git
a/Documentation/devicetree/bindings/display/bridge/ingenic,jz4780-hdmi.yaml
b/Documentation/devicetree/bindings/display/bridge/ingenic,jz4780-hdmi.yaml
new file mode 100644
index 0..190ca4521b1d0
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/ingenic,jz4780-hdmi.yaml
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bridge/ingenic,jz4780-hdmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Bindings for Ingenic JZ4780 HDMI Transmitter
+
+maintainers:
+ - H. Nikolaus Schaller
+
+description: |
+ The HDMI Transmitter in the Ingenic JZ4780 is a Synopsys DesignWare HDMI 1.4
+ TX controller IP with accompanying PHY IP.
+
+allOf:
+ - $ref: bridge/synopsys,dw-hdmi.yaml#
+
+properties:
+ compatible:
+const: ingenic,jz4780-dw-hdmi
+
+ reg-io-width:
+const: 4
+
+ clocks:
+maxItems: 2
+
+ hdmi-5v-supply:
+description: Optional regulator to provide +5V at the connector
+
+ ports:
+$ref: /schemas/graph.yaml#/properties/ports
+
+required:
+- compatible
+- clocks
+- clock-names
+- ports
+- reg-io-width
+
+unevaluatedPropertes: false
+
+examples:
+ - |
+#include
+
+hdmi: hdmi@1018 {
+compatible = "ingenic,jz4780-dw-hdmi";
+reg = <0x1018 0x8000>;
+reg-io-width = <4>;
+ddc-i2c-bus = <>;
+interrupt-parent = <>;
+interrupts = <3>;
+clocks = < JZ4780_CLK_AHB0>, < JZ4780_CLK_HDMI>;
+clock-names = "iahb", "isfr";
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+hdmi_in: port@0 {
+reg = <0>;
+dw_hdmi_in: endpoint {
+remote-endpoint = <_lcd_out>;
+};
+};
+hdmi_out: port@1 {
+reg = <1>;
+dw_hdmi_out: endpoint {
+remote-endpoint = <_con>;
+};
+};
+};
+};
+
+...
diff --git
a/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml
b/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml
index 9be44a682e67a..9cbeabaee0968 100644
--- a/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml
+++ b/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml
@@ -50,6 +50,9 @@ properties:
interrupts:
maxItems: 1
+ ddc-i2c-bus:
+description: An I2C interface if the internal DDC I2C driver is not to be
used
+
additionalProperties: true
...
--
2.33.0
[PATCH v8 7/8] MIPS: defconfig: CI20: configure for DRM_DW_HDMI_JZ4780
Enable CONFIG options as modules. Signed-off-by: Ezequiel Garcia Signed-off-by: H. Nikolaus Schaller --- arch/mips/configs/ci20_defconfig | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/mips/configs/ci20_defconfig b/arch/mips/configs/ci20_defconfig index ab7ebb0668340..cc69b215854ea 100644 --- a/arch/mips/configs/ci20_defconfig +++ b/arch/mips/configs/ci20_defconfig @@ -98,7 +98,13 @@ CONFIG_RC_DEVICES=y CONFIG_IR_GPIO_CIR=m CONFIG_IR_GPIO_TX=m CONFIG_MEDIA_SUPPORT=m +CONFIG_DRM=m +CONFIG_DRM_INGENIC=m +CONFIG_DRM_INGENIC_DW_HDMI=m +CONFIG_DRM_DISPLAY_CONNECTOR=m # CONFIG_VGA_CONSOLE is not set +CONFIG_FB=y +CONFIG_FRAMEBUFFER_CONSOLE=y # CONFIG_HID is not set CONFIG_USB=y CONFIG_USB_STORAGE=y -- 2.33.0
[PATCH v8 1/8] drm/ingenic: prepare ingenic drm for later addition of JZ4780
This changes the way the regmap is allocated to prepare for the
later addition of the JZ4780 which has more registers and bits
than the others.
Therefore we make the regmap as big as the reg property in
the device tree tells.
Suggested-by: Paul Cercueil
Signed-off-by: H. Nikolaus Schaller
---
drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
index 462bc0f35f1bf..0bb590c3910d9 100644
--- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
+++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
@@ -173,7 +173,6 @@ static const struct regmap_config ingenic_drm_regmap_config
= {
.val_bits = 32,
.reg_stride = 4,
- .max_register = JZ_REG_LCD_SIZE1,
.writeable_reg = ingenic_drm_writeable_reg,
};
@@ -1011,6 +1010,8 @@ static int ingenic_drm_bind(struct device *dev, bool
has_components)
struct ingenic_drm_bridge *ib;
struct drm_device *drm;
void __iomem *base;
+ struct resource *res;
+ struct regmap_config regmap_config;
long parent_rate;
unsigned int i, clone_mask = 0;
int ret, irq;
@@ -1056,14 +1057,16 @@ static int ingenic_drm_bind(struct device *dev, bool
has_components)
drm->mode_config.funcs = _drm_mode_config_funcs;
drm->mode_config.helper_private = _drm_mode_config_helpers;
- base = devm_platform_ioremap_resource(pdev, 0);
+ base = devm_platform_get_and_ioremap_resource(pdev, 0, );
if (IS_ERR(base)) {
dev_err(dev, "Failed to get memory resource\n");
return PTR_ERR(base);
}
+ regmap_config = ingenic_drm_regmap_config;
+ regmap_config.max_register = res->end - res->start;
priv->map = devm_regmap_init_mmio(dev, base,
- _drm_regmap_config);
+ _config);
if (IS_ERR(priv->map)) {
dev_err(dev, "Failed to create regmap\n");
return PTR_ERR(priv->map);
--
2.33.0
[PATCH v8 0/8] MIPS: JZ4780 and CI20 HDMI
PATCH V8 2021-11-23 19:14:00: - fix a bad editing result from patch 2/8 (found by p...@crapouillou.net) PATCH V7 2021-11-23 18:46:23: - changed gpio polarity of hdmi_power to 0 (suggested by p...@crapouillou.net) - fixed LCD1 irq number (bug found by p...@crapouillou.net) - removed "- 4" for calculating max_register (suggested by p...@crapouillou.net) - use unevaluatedPropertes instead of additionalProperties (suggested by r...@kernel.org) - moved and renamed ingenic,jz4780-hdmi.yaml (suggested by r...@kernel.org) - adjusted assigned-clocks changes to upstream which added some for SSI (by h...@goldelico.com) - rebased and tested with v5.16-rc2 + patch set drm/ingenic by p...@crapouillou.net (by h...@goldelico.com) PATCH V6 2021-11-10 20:43:33: - changed CONFIG_DRM_INGENIC_DW_HDMI to "m" (by h...@goldelico.com) - made ingenic-dw-hdmi an independent platform driver which can be compiled as module and removed error patch fixes for IPU (suggested by p...@crapouillou.net) - moved assigned-clocks from jz4780.dtsi to ci20.dts (suggested by p...@crapouillou.net) - fixed reg property in jz4780.dtsi to cover all registers incl. gamma and vee (by h...@goldelico.com) - added a base patch to calculate regmap size from DTS reg property (requested by p...@crapouillou.net) - restored resetting all bits except one in LCDOSDC (requested by p...@crapouillou.net) - clarified setting of cpos (suggested by p...@crapouillou.net) - moved bindings definition for ddc-i2c-bus (suggested by p...@crapouillou.net) - simplified mask definitions for JZ_LCD_DESSIZE (requested by p...@crapouillou.net) - removed setting alpha premultiplication (suggested by p...@crapouillou.net) - removed some comments (suggested by p...@crapouillou.net) PATCH V5 2021-10-05 14:28:44: - dropped mode_fixup and timings support in dw-hdmi as it is no longer needed in this V5 (by h...@goldelico.com) - dropped "drm/ingenic: add some jz4780 specific features" (stimulated by p...@crapouillou.net) - fixed typo in commit subject: "synopsis" -> "synopsys" (by h...@goldelico.com) - swapped clocks in jz4780.dtsi to match synopsys,dw-hdmi.yaml (by h...@goldelico.com) - improved, simplified, fixed, dtbschecked ingenic-jz4780-hdmi.yaml and made dependent of bridge/synopsys,dw-hdmi.yaml (based on suggestions by max...@cerno.tech) - fixed binding vs. driver use of hdmi-5v regulator (suggested by max...@cerno.tech) - dropped "drm/bridge: synopsis: Fix to properly handle HPD" - was a no longer needed workaround for a previous version (suggested by max...@cerno.tech) PATCH V4 2021-09-27 18:44:38: - fix setting output_port = 1 (issue found by p...@crapouillou.net) - ci20.dts: convert to use hdmi-connector (by h...@goldelico.com) - add a hdmi-regulator to control +5V power (by h...@goldelico.com) - added a fix to dw-hdmi to call drm_kms_helper_hotplug_event on plugin event detection (by h...@goldelico.com) - always allocate extended descriptor but initialize only for jz4780 (by h...@goldelico.com) - updated to work on top of "[PATCH v3 0/6] drm/ingenic: Various improvements v3" (by p...@crapouillou.net) - rebased to v5.13-rc3 PATCH V3 2021-08-08 07:10:50: This series adds HDMI support for JZ4780 and CI20 board (and fixes one IPU related issue in registration error path) - [patch 1/8] switched from mode_fixup to atomic_check (suggested by robert.f...@linaro.org) - the call to the dw-hdmi specialization is still called mode_fixup - [patch 3/8] diverse fixes for ingenic-drm-drv (suggested by p...@crapouillou.net) - factor out some non-HDMI features of the jz4780 into a separate patch - multiple fixes around max height - do not change regmap config but a copy on stack - define some constants - factor out fixing of drm_init error path for IPU into separate patch - use FIELD_PREP() - [patch 8/8] conversion to component framework dropped (suggested by laurent.pinch...@ideasonboard.com and p...@crapouillou.net) PATCH V2 2021-08-05 16:08:05: - code and commit messages revisited for checkpatch warnings - rebased on v5.14-rc4 - include (failed, hence RFC 8/8) attempt to convert to component framework (was suggested by Paul Cercueil a while ago) This series adds HDMI support for JZ4780 and CI20 board H. Nikolaus Schaller (3): drm/ingenic: prepare ingenic drm for later addition of JZ4780 MIPS: defconfig: CI20: configure for DRM_DW_HDMI_JZ4780 [RFC] MIPS: DTS: Ingenic: adjust register size to available registers Paul Boddie (4): drm/ingenic: Add support for JZ4780 and HDMI output drm/ingenic: Add dw-hdmi driver for jz4780 MIPS: DTS: jz4780: Account for Synopsys HDMI driver and LCD controllers MIPS: DTS: CI20: Add DT nodes for HDMI setup Sam Ravnborg (1): dt-bindings: display: Add ingenic,jz4780-dw-hdmi DT Schema .../display/bridge/ingenic,jz4780-hdmi.yaml | 76 +++ .../display/bridge/synopsys,dw-hdmi.yaml | 3 + arch/mips/boot/dts/ingenic/ci20.dts | 83 ++-
Re: [PATCH v7 2/8] drm/ingenic: Add support for JZ4780 and HDMI output
> Am 23.11.2021 um 19:06 schrieb Paul Cercueil :
>
> Hi Nikolaus,
>
> Le mar., nov. 23 2021 at 18:46:17 +0100, H. Nikolaus Schaller
> a écrit :
>> From: Paul Boddie
>> Add support for the LCD controller present on JZ4780 SoCs.
>> This SoC uses 8-byte descriptors which extend the current
>> 4-byte descriptors used for other Ingenic SoCs.
>> Tested on MIPS Creator CI20 board.
>> Signed-off-by: Paul Boddie
>> Signed-off-by: Ezequiel Garcia
>> Signed-off-by: H. Nikolaus Schaller
>> ---
>> drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 55 ++-
>> drivers/gpu/drm/ingenic/ingenic-drm.h | 38
>> 2 files changed, 92 insertions(+), 1 deletion(-)
>> diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
>> b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
>> index 0bb590c3910d9..5ff97a4bbcfe5 100644
>> --- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
>> +++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
>> @@ -6,6 +6,7 @@
>> #include "ingenic-drm.h"
>> +#include
>> #include
>> #include
>> #include
>> @@ -49,6 +50,11 @@ struct ingenic_dma_hwdesc {
>> u32 addr;
>> u32 id;
>> u32 cmd;
>> +/* extended hw descriptor for jz4780 */
>> +u32 offsize;
>> +u32 pagewidth;
>> +u32 cpos;
>> +u32 dessize;
>> } __aligned(16);
>> struct ingenic_dma_hwdescs {
>> @@ -60,6 +66,7 @@ struct jz_soc_info {
>> bool needs_dev_clk;
>> bool has_osd;
>> bool map_noncoherent;
>> +bool use_extended_hwdesc;
>> unsigned int max_width, max_height;
>> const u32 *formats_f0, *formats_f1;
>> unsigned int num_formats_f0, num_formats_f1;
>> @@ -446,6 +453,9 @@ static int ingenic_drm_plane_atomic_check(struct
>> drm_plane *plane,
>> if (!crtc)
>> return 0;
>> +if (plane == >f0)
>> +return -EINVAL;
>> +
>> crtc_state = drm_atomic_get_existing_crtc_state(state,
>> crtc);
>> if (WARN_ON(!crtc_state))
>> @@ -662,6 +672,33 @@ static void ingenic_drm_plane_atomic_update(struct
>> drm_plane *plane,
>> hwdesc->cmd = JZ_LCD_CMD_EOF_IRQ | (width * height * cpp / 4);
>> hwdesc->next = dma_hwdesc_addr(priv, next_id);
>> +if (priv->soc_info->use_extended_hwdesc) {
>> +hwdesc->cmd |= JZ_LCD_CMD_FRM_ENABLE;
>> +
>> +/* Extended 8-byte descriptor */
>> +hwdesc->cpos = 0;
>> +hwdesc->offsize = 0;
>> +hwdesc->pagewidth = 0;
>> +
>> +switch (newstate->fb->format->format) {
>> +case DRM_FORMAT_XRGB1555:
>> +hwdesc->cpos |= JZ_LCD_CPOS_RGB555;
>> +fallthrough;
>> +case DRM_FORMAT_RGB565:
>> +hwdesc->cpos |= JZ_LCD_CPOS_BPP_15_16;
>> +break;
>> +case DRM_FORMAT_XRGB:
>> +hwdesc->cpos |= JZ_LCD_CPOS_BPP_18_24;
>> +break;
>> +}
>> +hwdesc->cpos |= (JZ_LCD_CPOS_COEFFICIENT_1 <<
>> + JZ_LCD_CPOS_COEFFICIENT_OFFSET);
>> +hwdesc->dessize =
>> +(0xff << JZ_LCD_DESSIZE_ALPHA_OFFSET) |
>> +FIELD_PREP(JZ_LCD_DESSIZE_HEIGHT_MASK, height -
>> 1) |
>> +FIELD_PREP(JZ_LCD_DESSIZE_WIDTH_MASK, width -
>> 1);
>> +}
>> +
>> if (drm_atomic_crtc_needs_modeset(crtc_state)) {
>> fourcc = newstate->fb->format->format;
>> @@ -693,6 +730,9 @@ static void ingenic_drm_encoder_atomic_mode_set(struct
>> drm_encoder *encoder,
>> | JZ_LCD_CFG_SPL_DISABLE | JZ_LCD_CFG_REV_DISABLE;
>> }
>> +if (priv->soc_info->use_extended_hwdesc)
>> +cfg |= JZ_LCD_CFG_DESCRIPTOR_8;
>> +
>> if (mode->flags & DRM_MODE_FLAG_NHSYNC)
>> cfg |= JZ_LCD_CFG_HSYNC_ACTIVE_LOW;
>> if (mode->flags & DRM_MODE_FLAG_NVSYNC)
>> @@ -1064,7 +1104,7 @@ static int ingenic_drm_bind(struct device *dev, bool
>> has_components)
>> }
>> regmap_config = ingenic_drm_regmap_config;
>> -regmap_config.max_register = res->end - res->start;
>> +regmap_config.max_register = res->end - res->start - 4;
>
> I think this is wrong :)
Oops, that is a side-effect of my patch series editing tool.
It sometimes reverts changes of a previous commit if both
affect the same file. Sorry for that and I should fix it...
I'll send v8.
BR and thanks,
Nikolaus
>
> Cheers,
> -Paul
>
>> priv->map = devm_regmap_init_mmio(dev, base,
>>_config);
>> if (IS_ERR(priv->map)) {
>> @@ -1468,10 +1508,23 @@ static const struct jz_soc_info jz4770_soc_info = {
>> .num_formats_f0 = ARRAY_SIZE(jz4770_formats_f0),
>> };
>> +static const
Re: [PATCH v7 2/8] drm/ingenic: Add support for JZ4780 and HDMI output
Hi Nikolaus,
Le mar., nov. 23 2021 at 18:46:17 +0100, H. Nikolaus Schaller
a écrit :
From: Paul Boddie
Add support for the LCD controller present on JZ4780 SoCs.
This SoC uses 8-byte descriptors which extend the current
4-byte descriptors used for other Ingenic SoCs.
Tested on MIPS Creator CI20 board.
Signed-off-by: Paul Boddie
Signed-off-by: Ezequiel Garcia
Signed-off-by: H. Nikolaus Schaller
---
drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 55
++-
drivers/gpu/drm/ingenic/ingenic-drm.h | 38
2 files changed, 92 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
index 0bb590c3910d9..5ff97a4bbcfe5 100644
--- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
+++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
@@ -6,6 +6,7 @@
#include "ingenic-drm.h"
+#include
#include
#include
#include
@@ -49,6 +50,11 @@ struct ingenic_dma_hwdesc {
u32 addr;
u32 id;
u32 cmd;
+ /* extended hw descriptor for jz4780 */
+ u32 offsize;
+ u32 pagewidth;
+ u32 cpos;
+ u32 dessize;
} __aligned(16);
struct ingenic_dma_hwdescs {
@@ -60,6 +66,7 @@ struct jz_soc_info {
bool needs_dev_clk;
bool has_osd;
bool map_noncoherent;
+ bool use_extended_hwdesc;
unsigned int max_width, max_height;
const u32 *formats_f0, *formats_f1;
unsigned int num_formats_f0, num_formats_f1;
@@ -446,6 +453,9 @@ static int ingenic_drm_plane_atomic_check(struct
drm_plane *plane,
if (!crtc)
return 0;
+ if (plane == >f0)
+ return -EINVAL;
+
crtc_state = drm_atomic_get_existing_crtc_state(state,
crtc);
if (WARN_ON(!crtc_state))
@@ -662,6 +672,33 @@ static void
ingenic_drm_plane_atomic_update(struct drm_plane *plane,
hwdesc->cmd = JZ_LCD_CMD_EOF_IRQ | (width * height * cpp / 4);
hwdesc->next = dma_hwdesc_addr(priv, next_id);
+ if (priv->soc_info->use_extended_hwdesc) {
+ hwdesc->cmd |= JZ_LCD_CMD_FRM_ENABLE;
+
+ /* Extended 8-byte descriptor */
+ hwdesc->cpos = 0;
+ hwdesc->offsize = 0;
+ hwdesc->pagewidth = 0;
+
+ switch (newstate->fb->format->format) {
+ case DRM_FORMAT_XRGB1555:
+ hwdesc->cpos |= JZ_LCD_CPOS_RGB555;
+ fallthrough;
+ case DRM_FORMAT_RGB565:
+ hwdesc->cpos |= JZ_LCD_CPOS_BPP_15_16;
+ break;
+ case DRM_FORMAT_XRGB:
+ hwdesc->cpos |= JZ_LCD_CPOS_BPP_18_24;
+ break;
+ }
+ hwdesc->cpos |= (JZ_LCD_CPOS_COEFFICIENT_1 <<
+JZ_LCD_CPOS_COEFFICIENT_OFFSET);
+ hwdesc->dessize =
+ (0xff << JZ_LCD_DESSIZE_ALPHA_OFFSET) |
+ FIELD_PREP(JZ_LCD_DESSIZE_HEIGHT_MASK, height -
1) |
+ FIELD_PREP(JZ_LCD_DESSIZE_WIDTH_MASK, width -
1);
+ }
+
if (drm_atomic_crtc_needs_modeset(crtc_state)) {
fourcc = newstate->fb->format->format;
@@ -693,6 +730,9 @@ static void
ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder,
| JZ_LCD_CFG_SPL_DISABLE | JZ_LCD_CFG_REV_DISABLE;
}
+ if (priv->soc_info->use_extended_hwdesc)
+ cfg |= JZ_LCD_CFG_DESCRIPTOR_8;
+
if (mode->flags & DRM_MODE_FLAG_NHSYNC)
cfg |= JZ_LCD_CFG_HSYNC_ACTIVE_LOW;
if (mode->flags & DRM_MODE_FLAG_NVSYNC)
@@ -1064,7 +1104,7 @@ static int ingenic_drm_bind(struct device *dev,
bool has_components)
}
regmap_config = ingenic_drm_regmap_config;
- regmap_config.max_register = res->end - res->start;
+ regmap_config.max_register = res->end - res->start - 4;
I think this is wrong :)
Cheers,
-Paul
priv->map = devm_regmap_init_mmio(dev, base,
_config);
if (IS_ERR(priv->map)) {
@@ -1468,10 +1508,23 @@ static const struct jz_soc_info
jz4770_soc_info = {
.num_formats_f0 = ARRAY_SIZE(jz4770_formats_f0),
};
+static const struct jz_soc_info jz4780_soc_info = {
+ .needs_dev_clk = true,
+ .has_osd = true,
+ .use_extended_hwdesc = true,
+ .max_width = 4096,
+ .max_height = 2048,
+ .formats_f1 = jz4770_formats_f1,
+ .num_formats_f1 = ARRAY_SIZE(jz4770_formats_f1),
+ .formats_f0 = jz4770_formats_f0,
+ .num_formats_f0 = ARRAY_SIZE(jz4770_formats_f0),
+};
+
static
Re: [PATCH 3/3] drm/i915/gt: Improve "race-to-idle" at low frequencies
On 11/17/2021 2:49 PM, Vinay Belgaumkar wrote:
From: Chris Wilson
While the power consumption is proportional to the frequency, there is
also a static draw for active gates. The longer we are able to powergate
(rc6), the lower the static draw. Thus there is a sweetspot in the
frequency/power curve where we run at higher frequency in order to sleep
longer, aka race-to-idle. This is more evident at lower frequencies, so
let's look to bump the frequency if we think we will benefit by sleeping
longer at the higher frequency and so conserving power.
Signed-off-by: Chris Wilson
Cc: Vinay Belgaumkar
Cc: Tvrtko Ursulin
Data collected does show some power savings.
Reviewed-by: Vinay Belgaumkar
---
drivers/gpu/drm/i915/gt/intel_rps.c | 31 -
1 file changed, 26 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 3675ac93ded0..6af3231982af 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -63,6 +63,22 @@ static void set(struct intel_uncore *uncore, i915_reg_t reg,
u32 val)
intel_uncore_write_fw(uncore, reg, val);
}
+static bool race_to_idle(struct intel_rps *rps, u64 busy, u64 dt)
+{
+ unsigned int this = rps->cur_freq;
+ unsigned int next = rps->cur_freq + 1;
+ u64 next_dt = next * max(busy, dt);
+
+ /*
+* Compare estimated time spent in rc6 at the next power bin. If
+* we expect to sleep longer than the estimated increased power
+* cost of running at a higher frequency, it will be reduced power
+* consumption overall.
+*/
+ return (((next_dt - this * busy) >> 10) * this * this >
+ ((next_dt - next * busy) >> 10) * next * next);
+}
+
static void rps_timer(struct timer_list *t)
{
struct intel_rps *rps = from_timer(rps, t, timer);
@@ -133,7 +149,7 @@ static void rps_timer(struct timer_list *t)
if (!max_busy[i])
break;
- busy += div_u64(max_busy[i], 1 << i);
+ busy += max_busy[i] >> i;
}
GT_TRACE(rps_to_gt(rps),
"busy:%lld [%d%%], max:[%lld, %lld, %lld],
interval:%d\n",
@@ -141,13 +157,18 @@ static void rps_timer(struct timer_list *t)
max_busy[0], max_busy[1], max_busy[2],
rps->pm_interval);
- if (100 * busy > rps->power.up_threshold * dt &&
- rps->cur_freq < rps->max_freq_softlimit) {
+ if (rps->cur_freq < rps->max_freq_softlimit &&
+ race_to_idle(rps, max_busy[0], dt)) {
+ rps->pm_iir |= GEN6_PM_RP_UP_THRESHOLD;
+ rps->pm_interval = 1;
+ schedule_work(>work);
+ } else if (rps->cur_freq < rps->max_freq_softlimit &&
+ 100 * busy > rps->power.up_threshold * dt) {
rps->pm_iir |= GEN6_PM_RP_UP_THRESHOLD;
rps->pm_interval = 1;
schedule_work(>work);
- } else if (100 * busy < rps->power.down_threshold * dt &&
- rps->cur_freq > rps->min_freq_softlimit) {
+ } else if (rps->cur_freq > rps->min_freq_softlimit &&
+ 100 * busy < rps->power.down_threshold * dt) {
rps->pm_iir |= GEN6_PM_RP_DOWN_THRESHOLD;
rps->pm_interval = 1;
schedule_work(>work);
Re: [PATCH 2/3] drm/i915/gt: Compare average group occupancy for RPS evaluation
On 11/17/2021 2:49 PM, Vinay Belgaumkar wrote:
From: Chris Wilson
Currently, we inspect each engine individually and measure the occupancy
of that engine over the last evaluation interval. If that exceeds our
busyness thresholds, we decide to increase the GPU frequency. However,
under a load balancer, we should consider the occupancy of entire engine
groups, as work may be spread out across the group. In doing so, we
prefer wide over fast, power consumption is approximately proportional to
the square of the frequency. However, since the load balancer is greedy,
the first idle engine gets all the work, and preferrentially reuses the
last active engine, under light loads all work is assigned to one
engine, and so that engine appears very busy. But if the work happened
to overlap slightly, the workload would spread across multiple engines,
reducing each individual engine's runtime, and so reducing the rps
contribution, keeping the frequency low. Instead, when considering the
contribution, consider the contribution over the entire engine group
(capacity).
Signed-off-by: Chris Wilson
Cc: Vinay Belgaumkar
Cc: Tvrtko Ursulin
Reviewed-by: Vinay Belgaumkar
---
drivers/gpu/drm/i915/gt/intel_rps.c | 48 -
1 file changed, 34 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 07ff7ba7b2b7..3675ac93ded0 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -7,6 +7,7 @@
#include "i915_drv.h"
#include "intel_breadcrumbs.h"
+#include "intel_engine_pm.h"
#include "intel_gt.h"
#include "intel_gt_clock_utils.h"
#include "intel_gt_irq.h"
@@ -65,26 +66,45 @@ static void set(struct intel_uncore *uncore, i915_reg_t
reg, u32 val)
static void rps_timer(struct timer_list *t)
{
struct intel_rps *rps = from_timer(rps, t, timer);
- struct intel_engine_cs *engine;
- ktime_t dt, last, timestamp;
- enum intel_engine_id id;
+ struct intel_gt *gt = rps_to_gt(rps);
+ ktime_t dt, last, timestamp = 0;
s64 max_busy[3] = {};
+ int i, j;
- timestamp = 0;
- for_each_engine(engine, rps_to_gt(rps), id) {
- s64 busy;
- int i;
+ /* Compare average occupancy over each engine group */
+ for (i = 0; i < ARRAY_SIZE(gt->engine_class); i++) {
+ s64 busy = 0;
+ int count = 0;
+
+ for (j = 0; j < ARRAY_SIZE(gt->engine_class[i]); j++) {
+ struct intel_engine_cs *engine;
- dt = intel_engine_get_busy_time(engine, );
- last = engine->stats.rps;
- engine->stats.rps = dt;
+ engine = gt->engine_class[i][j];
+ if (!engine)
+ continue;
- busy = ktime_to_ns(ktime_sub(dt, last));
- for (i = 0; i < ARRAY_SIZE(max_busy); i++) {
- if (busy > max_busy[i])
- swap(busy, max_busy[i]);
+ dt = intel_engine_get_busy_time(engine, );
+ last = engine->stats.rps;
+ engine->stats.rps = dt;
+
+ if (!intel_engine_pm_is_awake(engine))
+ continue;
+
+ busy += ktime_to_ns(ktime_sub(dt, last));
+ count++;
+ }
+
+ if (count > 1)
+ busy = div_u64(busy, count);
+ if (busy <= max_busy[ARRAY_SIZE(max_busy) - 1])
+ continue;
+
+ for (j = 0; j < ARRAY_SIZE(max_busy); j++) {
+ if (busy > max_busy[j])
+ swap(busy, max_busy[j]);
}
}
+
last = rps->pm_timestamp;
rps->pm_timestamp = timestamp;
[PATCH v7 7/8] MIPS: defconfig: CI20: configure for DRM_DW_HDMI_JZ4780
Enable CONFIG options as modules. Signed-off-by: Ezequiel Garcia Signed-off-by: H. Nikolaus Schaller --- arch/mips/configs/ci20_defconfig | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/mips/configs/ci20_defconfig b/arch/mips/configs/ci20_defconfig index ab7ebb0668340..cc69b215854ea 100644 --- a/arch/mips/configs/ci20_defconfig +++ b/arch/mips/configs/ci20_defconfig @@ -98,7 +98,13 @@ CONFIG_RC_DEVICES=y CONFIG_IR_GPIO_CIR=m CONFIG_IR_GPIO_TX=m CONFIG_MEDIA_SUPPORT=m +CONFIG_DRM=m +CONFIG_DRM_INGENIC=m +CONFIG_DRM_INGENIC_DW_HDMI=m +CONFIG_DRM_DISPLAY_CONNECTOR=m # CONFIG_VGA_CONSOLE is not set +CONFIG_FB=y +CONFIG_FRAMEBUFFER_CONSOLE=y # CONFIG_HID is not set CONFIG_USB=y CONFIG_USB_STORAGE=y -- 2.33.0
[PATCH v7 8/8] [RFC] MIPS: DTS: Ingenic: adjust register size to available registers
After getting the regmap size from the device tree we should
reduce the ranges to the really available registers. This
allows to read only existing registers from the debug fs
and makes the regmap check out-of-bounds access.
For the jz4780 we have done this already.
Suggested-for: Paul Cercueil
Signed-off-by: H. Nikolaus Schaller
---
arch/mips/boot/dts/ingenic/jz4725b.dtsi | 2 +-
arch/mips/boot/dts/ingenic/jz4740.dtsi | 2 +-
arch/mips/boot/dts/ingenic/jz4770.dtsi | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/mips/boot/dts/ingenic/jz4725b.dtsi
b/arch/mips/boot/dts/ingenic/jz4725b.dtsi
index 0c6a5a4266f43..e9e48022f6316 100644
--- a/arch/mips/boot/dts/ingenic/jz4725b.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4725b.dtsi
@@ -321,7 +321,7 @@ udc: usb@1304 {
lcd: lcd-controller@1305 {
compatible = "ingenic,jz4725b-lcd";
- reg = <0x1305 0x1000>;
+ reg = <0x1305 0x130>; /* tbc */
interrupt-parent = <>;
interrupts = <31>;
diff --git a/arch/mips/boot/dts/ingenic/jz4740.dtsi
b/arch/mips/boot/dts/ingenic/jz4740.dtsi
index 772542e1f266a..7f76cba03a089 100644
--- a/arch/mips/boot/dts/ingenic/jz4740.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4740.dtsi
@@ -323,7 +323,7 @@ udc: usb@1304 {
lcd: lcd-controller@1305 {
compatible = "ingenic,jz4740-lcd";
- reg = <0x1305 0x1000>;
+ reg = <0x1305 0x60>; /* LCDCMD1+4 */
interrupt-parent = <>;
interrupts = <30>;
diff --git a/arch/mips/boot/dts/ingenic/jz4770.dtsi
b/arch/mips/boot/dts/ingenic/jz4770.dtsi
index dfe74328ae5dc..bda0a3a86ed5f 100644
--- a/arch/mips/boot/dts/ingenic/jz4770.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4770.dtsi
@@ -399,7 +399,7 @@ gpu: gpu@1304 {
lcd: lcd-controller@1305 {
compatible = "ingenic,jz4770-lcd";
- reg = <0x1305 0x300>;
+ reg = <0x1305 0x130>; /* tbc */
interrupt-parent = <>;
interrupts = <31>;
--
2.33.0
[PATCH v7 2/8] drm/ingenic: Add support for JZ4780 and HDMI output
From: Paul Boddie
Add support for the LCD controller present on JZ4780 SoCs.
This SoC uses 8-byte descriptors which extend the current
4-byte descriptors used for other Ingenic SoCs.
Tested on MIPS Creator CI20 board.
Signed-off-by: Paul Boddie
Signed-off-by: Ezequiel Garcia
Signed-off-by: H. Nikolaus Schaller
---
drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 55 ++-
drivers/gpu/drm/ingenic/ingenic-drm.h | 38
2 files changed, 92 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
index 0bb590c3910d9..5ff97a4bbcfe5 100644
--- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
+++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
@@ -6,6 +6,7 @@
#include "ingenic-drm.h"
+#include
#include
#include
#include
@@ -49,6 +50,11 @@ struct ingenic_dma_hwdesc {
u32 addr;
u32 id;
u32 cmd;
+ /* extended hw descriptor for jz4780 */
+ u32 offsize;
+ u32 pagewidth;
+ u32 cpos;
+ u32 dessize;
} __aligned(16);
struct ingenic_dma_hwdescs {
@@ -60,6 +66,7 @@ struct jz_soc_info {
bool needs_dev_clk;
bool has_osd;
bool map_noncoherent;
+ bool use_extended_hwdesc;
unsigned int max_width, max_height;
const u32 *formats_f0, *formats_f1;
unsigned int num_formats_f0, num_formats_f1;
@@ -446,6 +453,9 @@ static int ingenic_drm_plane_atomic_check(struct drm_plane
*plane,
if (!crtc)
return 0;
+ if (plane == >f0)
+ return -EINVAL;
+
crtc_state = drm_atomic_get_existing_crtc_state(state,
crtc);
if (WARN_ON(!crtc_state))
@@ -662,6 +672,33 @@ static void ingenic_drm_plane_atomic_update(struct
drm_plane *plane,
hwdesc->cmd = JZ_LCD_CMD_EOF_IRQ | (width * height * cpp / 4);
hwdesc->next = dma_hwdesc_addr(priv, next_id);
+ if (priv->soc_info->use_extended_hwdesc) {
+ hwdesc->cmd |= JZ_LCD_CMD_FRM_ENABLE;
+
+ /* Extended 8-byte descriptor */
+ hwdesc->cpos = 0;
+ hwdesc->offsize = 0;
+ hwdesc->pagewidth = 0;
+
+ switch (newstate->fb->format->format) {
+ case DRM_FORMAT_XRGB1555:
+ hwdesc->cpos |= JZ_LCD_CPOS_RGB555;
+ fallthrough;
+ case DRM_FORMAT_RGB565:
+ hwdesc->cpos |= JZ_LCD_CPOS_BPP_15_16;
+ break;
+ case DRM_FORMAT_XRGB:
+ hwdesc->cpos |= JZ_LCD_CPOS_BPP_18_24;
+ break;
+ }
+ hwdesc->cpos |= (JZ_LCD_CPOS_COEFFICIENT_1 <<
+JZ_LCD_CPOS_COEFFICIENT_OFFSET);
+ hwdesc->dessize =
+ (0xff << JZ_LCD_DESSIZE_ALPHA_OFFSET) |
+ FIELD_PREP(JZ_LCD_DESSIZE_HEIGHT_MASK, height -
1) |
+ FIELD_PREP(JZ_LCD_DESSIZE_WIDTH_MASK, width -
1);
+ }
+
if (drm_atomic_crtc_needs_modeset(crtc_state)) {
fourcc = newstate->fb->format->format;
@@ -693,6 +730,9 @@ static void ingenic_drm_encoder_atomic_mode_set(struct
drm_encoder *encoder,
| JZ_LCD_CFG_SPL_DISABLE | JZ_LCD_CFG_REV_DISABLE;
}
+ if (priv->soc_info->use_extended_hwdesc)
+ cfg |= JZ_LCD_CFG_DESCRIPTOR_8;
+
if (mode->flags & DRM_MODE_FLAG_NHSYNC)
cfg |= JZ_LCD_CFG_HSYNC_ACTIVE_LOW;
if (mode->flags & DRM_MODE_FLAG_NVSYNC)
@@ -1064,7 +1104,7 @@ static int ingenic_drm_bind(struct device *dev, bool
has_components)
}
regmap_config = ingenic_drm_regmap_config;
- regmap_config.max_register = res->end - res->start;
+ regmap_config.max_register = res->end - res->start - 4;
priv->map = devm_regmap_init_mmio(dev, base,
_config);
if (IS_ERR(priv->map)) {
@@ -1468,10 +1508,23 @@ static const struct jz_soc_info jz4770_soc_info = {
.num_formats_f0 = ARRAY_SIZE(jz4770_formats_f0),
};
+static const struct jz_soc_info jz4780_soc_info = {
+ .needs_dev_clk = true,
+ .has_osd = true,
+ .use_extended_hwdesc = true,
+ .max_width = 4096,
+ .max_height = 2048,
+ .formats_f1 = jz4770_formats_f1,
+ .num_formats_f1 = ARRAY_SIZE(jz4770_formats_f1),
+ .formats_f0 = jz4770_formats_f0,
+ .num_formats_f0 = ARRAY_SIZE(jz4770_formats_f0),
+};
+
static const struct of_device_id ingenic_drm_of_match[] = {
{ .compatible = "ingenic,jz4740-lcd", .data = _soc_info },
{
[PATCH v7 3/8] dt-bindings: display: Add ingenic, jz4780-dw-hdmi DT Schema
From: Sam Ravnborg
Add DT bindings for the hdmi driver for the Ingenic JZ4780 SoC.
Based on .txt binding from Zubair Lutfullah Kakakhel
We also add generic ddc-i2c-bus to synopsys,dw-hdmi.yaml
Signed-off-by: Sam Ravnborg
Signed-off-by: H. Nikolaus Schaller
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
---
.../display/bridge/ingenic,jz4780-hdmi.yaml | 76 +++
.../display/bridge/synopsys,dw-hdmi.yaml | 3 +
2 files changed, 79 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/ingenic,jz4780-hdmi.yaml
diff --git
a/Documentation/devicetree/bindings/display/bridge/ingenic,jz4780-hdmi.yaml
b/Documentation/devicetree/bindings/display/bridge/ingenic,jz4780-hdmi.yaml
new file mode 100644
index 0..190ca4521b1d0
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/ingenic,jz4780-hdmi.yaml
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bridge/ingenic,jz4780-hdmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Bindings for Ingenic JZ4780 HDMI Transmitter
+
+maintainers:
+ - H. Nikolaus Schaller
+
+description: |
+ The HDMI Transmitter in the Ingenic JZ4780 is a Synopsys DesignWare HDMI 1.4
+ TX controller IP with accompanying PHY IP.
+
+allOf:
+ - $ref: bridge/synopsys,dw-hdmi.yaml#
+
+properties:
+ compatible:
+const: ingenic,jz4780-dw-hdmi
+
+ reg-io-width:
+const: 4
+
+ clocks:
+maxItems: 2
+
+ hdmi-5v-supply:
+description: Optional regulator to provide +5V at the connector
+
+ ports:
+$ref: /schemas/graph.yaml#/properties/ports
+
+required:
+- compatible
+- clocks
+- clock-names
+- ports
+- reg-io-width
+
+unevaluatedPropertes: false
+
+examples:
+ - |
+#include
+
+hdmi: hdmi@1018 {
+compatible = "ingenic,jz4780-dw-hdmi";
+reg = <0x1018 0x8000>;
+reg-io-width = <4>;
+ddc-i2c-bus = <>;
+interrupt-parent = <>;
+interrupts = <3>;
+clocks = < JZ4780_CLK_AHB0>, < JZ4780_CLK_HDMI>;
+clock-names = "iahb", "isfr";
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+hdmi_in: port@0 {
+reg = <0>;
+dw_hdmi_in: endpoint {
+remote-endpoint = <_lcd_out>;
+};
+};
+hdmi_out: port@1 {
+reg = <1>;
+dw_hdmi_out: endpoint {
+remote-endpoint = <_con>;
+};
+};
+};
+};
+
+...
diff --git
a/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml
b/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml
index 9be44a682e67a..9cbeabaee0968 100644
--- a/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml
+++ b/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml
@@ -50,6 +50,9 @@ properties:
interrupts:
maxItems: 1
+ ddc-i2c-bus:
+description: An I2C interface if the internal DDC I2C driver is not to be
used
+
additionalProperties: true
...
--
2.33.0
[PATCH v7 6/8] MIPS: DTS: CI20: Add DT nodes for HDMI setup
From: Paul Boddie
We need to hook up
* HDMI connector
* HDMI power regulator
* JZ4780_CLK_HDMI @ 27 MHz
* DDC pinmux
* HDMI and LCDC endpoint connections
Signed-off-by: Paul Boddie
Signed-off-by: H. Nikolaus Schaller
---
arch/mips/boot/dts/ingenic/ci20.dts | 83 +++--
1 file changed, 80 insertions(+), 3 deletions(-)
diff --git a/arch/mips/boot/dts/ingenic/ci20.dts
b/arch/mips/boot/dts/ingenic/ci20.dts
index b249a4f0f6b62..15cf03670693f 100644
--- a/arch/mips/boot/dts/ingenic/ci20.dts
+++ b/arch/mips/boot/dts/ingenic/ci20.dts
@@ -78,6 +78,18 @@ eth0_power: fixedregulator@0 {
enable-active-high;
};
+ hdmi_out: connector {
+ compatible = "hdmi-connector";
+ label = "HDMI OUT";
+ type = "a";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <_hdmi_out>;
+ };
+ };
+ };
+
ir: ir {
compatible = "gpio-ir-receiver";
gpios = < 3 GPIO_ACTIVE_LOW>;
@@ -102,6 +114,17 @@ otg_power: fixedregulator@2 {
gpio = < 14 GPIO_ACTIVE_LOW>;
enable-active-high;
};
+
+ hdmi_power: fixedregulator@3 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "hdmi_power";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+
+ gpio = < 25 0>;
+ enable-active-high;
+ };
};
{
@@ -114,11 +137,13 @@ {
* precision.
*/
assigned-clocks = < JZ4780_CLK_OTGPHY>, < JZ4780_CLK_RTC>,
- < JZ4780_CLK_SSIPLL>, < JZ4780_CLK_SSI>;
+ < JZ4780_CLK_SSIPLL>, < JZ4780_CLK_SSI>,
+ < JZ4780_CLK_HDMI>;
assigned-clock-parents = <0>, < JZ4780_CLK_RTCLK>,
< JZ4780_CLK_MPLL>,
-< JZ4780_CLK_SSIPLL>;
- assigned-clock-rates = <4800>, <0>, <5400>;
+< JZ4780_CLK_SSIPLL>,
+<0>;
+ assigned-clock-rates = <4800>, <0>, <5400>, <0>, <2700>;
};
{
@@ -509,6 +534,19 @@ pins_i2c4: i2c4 {
bias-disable;
};
+ pins_hdmi_ddc: hdmi_ddc {
+ function = "hdmi-ddc";
+ groups = "hdmi-ddc";
+ bias-disable;
+ };
+
+ /* switch to PF25 as gpio driving DDC_SDA low */
+ pins_hdmi_ddc_unwedge: hdmi_ddc {
+ function = "hdmi-ddc";
+ groups = "hdmi-ddc";
+ bias-disable;
+ };
+
pins_nemc: nemc {
function = "nemc";
groups = "nemc-data", "nemc-cle-ale", "nemc-rd-we",
"nemc-frd-fwe";
@@ -539,3 +577,42 @@ pins_mmc1: mmc1 {
bias-disable;
};
};
+
+ {
+ status = "okay";
+
+ pinctrl-names = "default", "unwedge";
+ pinctrl-0 = <_hdmi_ddc>;
+ pinctrl-1 = <_hdmi_ddc_unwedge>;
+
+ hdmi-5v-supply = <_power>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dw_hdmi_in: endpoint {
+ remote-endpoint = <_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dw_hdmi_out: endpoint {
+ remote-endpoint = <_con>;
+ };
+ };
+ };
+};
+
+ {
+ status = "okay";
+
+ port {
+ lcd_out: endpoint {
+ remote-endpoint = <_hdmi_in>;
+ };
+ };
+};
--
2.33.0
[PATCH v7 5/8] MIPS: DTS: jz4780: Account for Synopsys HDMI driver and LCD controllers
From: Paul Boddie
A specialisation of the generic Synopsys HDMI driver is employed for
JZ4780 HDMI support. This requires a new driver, plus device tree and
configuration modifications.
Here we add jz4780 device tree setup.
Signed-off-by: Paul Boddie
Signed-off-by: H. Nikolaus Schaller
---
arch/mips/boot/dts/ingenic/jz4780.dtsi | 40 ++
1 file changed, 40 insertions(+)
diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi
b/arch/mips/boot/dts/ingenic/jz4780.dtsi
index b0a4e2e019c36..3f9ea47a10cd2 100644
--- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
@@ -444,6 +444,46 @@ i2c4: i2c@10054000 {
status = "disabled";
};
+ hdmi: hdmi@1018 {
+ compatible = "ingenic,jz4780-dw-hdmi";
+ reg = <0x1018 0x8000>;
+ reg-io-width = <4>;
+
+ clocks = < JZ4780_CLK_AHB0>, < JZ4780_CLK_HDMI>;
+ clock-names = "iahb", "isfr";
+
+ interrupt-parent = <>;
+ interrupts = <3>;
+
+ status = "disabled";
+ };
+
+ lcdc0: lcdc0@1305 {
+ compatible = "ingenic,jz4780-lcd";
+ reg = <0x1305 0x1800>;
+
+ clocks = < JZ4780_CLK_TVE>, < JZ4780_CLK_LCD0PIXCLK>;
+ clock-names = "lcd", "lcd_pclk";
+
+ interrupt-parent = <>;
+ interrupts = <31>;
+
+ status = "disabled";
+ };
+
+ lcdc1: lcdc1@130a {
+ compatible = "ingenic,jz4780-lcd";
+ reg = <0x130a 0x1800>;
+
+ clocks = < JZ4780_CLK_TVE>, < JZ4780_CLK_LCD1PIXCLK>;
+ clock-names = "lcd", "lcd_pclk";
+
+ interrupt-parent = <>;
+ interrupts = <23>;
+
+ status = "disabled";
+ };
+
nemc: nemc@1341 {
compatible = "ingenic,jz4780-nemc", "simple-mfd";
reg = <0x1341 0x1>;
--
2.33.0
[PATCH v7 4/8] drm/ingenic: Add dw-hdmi driver for jz4780
From: Paul Boddie
A specialisation of the generic Synopsys HDMI driver is employed for
JZ4780 HDMI support. This requires a new driver, plus device tree and
configuration modifications.
Here we add Kconfig DRM_INGENIC_DW_HDMI, Makefile and driver code.
Signed-off-by: Paul Boddie
Signed-off-by: Ezequiel Garcia
Signed-off-by: H. Nikolaus Schaller
---
drivers/gpu/drm/ingenic/Kconfig | 9 ++
drivers/gpu/drm/ingenic/Makefile | 1 +
drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c | 129 ++
3 files changed, 139 insertions(+)
create mode 100644 drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c
diff --git a/drivers/gpu/drm/ingenic/Kconfig b/drivers/gpu/drm/ingenic/Kconfig
index 3b57f8be007c4..4efc709d77b0a 100644
--- a/drivers/gpu/drm/ingenic/Kconfig
+++ b/drivers/gpu/drm/ingenic/Kconfig
@@ -25,4 +25,13 @@ config DRM_INGENIC_IPU
The Image Processing Unit (IPU) will appear as a second primary plane.
+config DRM_INGENIC_DW_HDMI
+ tristate "Ingenic specific support for Synopsys DW HDMI"
+ depends on MACH_JZ4780
+ select DRM_DW_HDMI
+ help
+ Choose this option to enable Synopsys DesignWare HDMI based driver.
+ If you want to enable HDMI on Ingenic JZ4780 based SoC, you should
+ select this option..
+
endif
diff --git a/drivers/gpu/drm/ingenic/Makefile b/drivers/gpu/drm/ingenic/Makefile
index d313326bdddbb..f10cc1c5a5f22 100644
--- a/drivers/gpu/drm/ingenic/Makefile
+++ b/drivers/gpu/drm/ingenic/Makefile
@@ -1,3 +1,4 @@
obj-$(CONFIG_DRM_INGENIC) += ingenic-drm.o
ingenic-drm-y = ingenic-drm-drv.o
ingenic-drm-$(CONFIG_DRM_INGENIC_IPU) += ingenic-ipu.o
+obj-$(CONFIG_DRM_INGENIC_DW_HDMI) += ingenic-dw-hdmi.o
diff --git a/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c
b/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c
new file mode 100644
index 0..c14890d6b9826
--- /dev/null
+++ b/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2019, 2020 Paul Boddie
+ *
+ * Derived from dw_hdmi-imx.c with i.MX portions removed.
+ * Probe and remove operations derived from rcar_dw_hdmi.c.
+ */
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+static const struct dw_hdmi_mpll_config ingenic_mpll_cfg[] = {
+ { 4525, { { 0x01e0, 0x }, { 0x21e1, 0x }, { 0x41e2, 0x
} } },
+ { 9250, { { 0x0140, 0x0005 }, { 0x2141, 0x0005 }, { 0x4142, 0x0005
} } },
+ { 14850, { { 0x00a0, 0x000a }, { 0x20a1, 0x000a }, { 0x40a2, 0x000a
} } },
+ { 21600, { { 0x00a0, 0x000a }, { 0x2001, 0x000f }, { 0x4002, 0x000f
} } },
+ { ~0UL, { { 0x, 0x }, { 0x, 0x }, { 0x, 0x
} } }
+};
+
+static const struct dw_hdmi_curr_ctrl ingenic_cur_ctr[] = {
+ /*pixelclk bpp8bpp10 bpp12 */
+ { 5400, { 0x091c, 0x091c, 0x06dc } },
+ { 5840, { 0x091c, 0x06dc, 0x06dc } },
+ { 7200, { 0x06dc, 0x06dc, 0x091c } },
+ { 7425, { 0x06dc, 0x0b5c, 0x091c } },
+ { 11880, { 0x091c, 0x091c, 0x06dc } },
+ { 21600, { 0x06dc, 0x0b5c, 0x091c } },
+ { ~0UL, { 0x, 0x, 0x } },
+};
+
+/*
+ * Resistance term 133Ohm Cfg
+ * PREEMP config 0.00
+ * TX/CK level 10
+ */
+static const struct dw_hdmi_phy_config ingenic_phy_config[] = {
+ /*pixelclk symbol term vlev */
+ { 21600, 0x800d, 0x0005, 0x01ad},
+ { ~0UL, 0x, 0x, 0x}
+};
+
+static enum drm_mode_status
+ingenic_dw_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data,
+ const struct drm_display_info *info,
+ const struct drm_display_mode *mode)
+{
+ if (mode->clock < 13500)
+ return MODE_CLOCK_LOW;
+ /* FIXME: Hardware is capable of 270MHz, but setup data is missing. */
+ if (mode->clock > 216000)
+ return MODE_CLOCK_HIGH;
+
+ return MODE_OK;
+}
+
+static struct dw_hdmi_plat_data ingenic_dw_hdmi_plat_data = {
+ .mpll_cfg = ingenic_mpll_cfg,
+ .cur_ctr= ingenic_cur_ctr,
+ .phy_config = ingenic_phy_config,
+ .mode_valid = ingenic_dw_hdmi_mode_valid,
+ .output_port= 1,
+};
+
+static const struct of_device_id ingenic_dw_hdmi_dt_ids[] = {
+ { .compatible = "ingenic,jz4780-dw-hdmi" },
+ { /* Sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, ingenic_dw_hdmi_dt_ids);
+
+static int ingenic_dw_hdmi_probe(struct platform_device *pdev)
+{
+ struct dw_hdmi *hdmi;
+ struct regulator *regulator;
+ int ret;
+
+ hdmi = dw_hdmi_probe(pdev, _dw_hdmi_plat_data);
+ if (IS_ERR(hdmi))
+ return PTR_ERR(hdmi);
+
+ platform_set_drvdata(pdev, hdmi);
+
+ regulator = devm_regulator_get_optional(>dev, "hdmi-5v");
+
+ if (IS_ERR(regulator)) {
+ ret = PTR_ERR(regulator);
+
+
[PATCH v7 0/8] MIPS: JZ4780 and CI20 HDMI
PATCH V7 2021-11-23 18:46:23: - changed gpio polarity of hdmi_power to 0 (suggested by p...@crapouillou.net) - fixed LCD1 irq number (bug found by p...@crapouillou.net) - removed "- 4" for calculating max_register (suggested by p...@crapouillou.net) - use unevaluatedPropertes instead of additionalProperties (suggested by r...@kernel.org) - moved and renamed ingenic,jz4780-hdmi.yaml (suggested by r...@kernel.org) - adjusted assigned-clocks changes to upstream which added some for SSI (by h...@goldelico.com) - rebased and tested with v5.16-rc2 + patch set drm/ingenic by p...@crapouillou.net (by h...@goldelico.com) PATCH V6 2021-11-10 20:43:33: - changed CONFIG_DRM_INGENIC_DW_HDMI to "m" (by h...@goldelico.com) - made ingenic-dw-hdmi an independent platform driver which can be compiled as module and removed error patch fixes for IPU (suggested by p...@crapouillou.net) - moved assigned-clocks from jz4780.dtsi to ci20.dts (suggested by p...@crapouillou.net) - fixed reg property in jz4780.dtsi to cover all registers incl. gamma and vee (by h...@goldelico.com) - added a base patch to calculate regmap size from DTS reg property (requested by p...@crapouillou.net) - restored resetting all bits except one in LCDOSDC (requested by p...@crapouillou.net) - clarified setting of cpos (suggested by p...@crapouillou.net) - moved bindings definition for ddc-i2c-bus (suggested by p...@crapouillou.net) - simplified mask definitions for JZ_LCD_DESSIZE (requested by p...@crapouillou.net) - removed setting alpha premultiplication (suggested by p...@crapouillou.net) - removed some comments (suggested by p...@crapouillou.net) PATCH V5 2021-10-05 14:28:44: - dropped mode_fixup and timings support in dw-hdmi as it is no longer needed in this V5 (by h...@goldelico.com) - dropped "drm/ingenic: add some jz4780 specific features" (stimulated by p...@crapouillou.net) - fixed typo in commit subject: "synopsis" -> "synopsys" (by h...@goldelico.com) - swapped clocks in jz4780.dtsi to match synopsys,dw-hdmi.yaml (by h...@goldelico.com) - improved, simplified, fixed, dtbschecked ingenic-jz4780-hdmi.yaml and made dependent of bridge/synopsys,dw-hdmi.yaml (based on suggestions by max...@cerno.tech) - fixed binding vs. driver use of hdmi-5v regulator (suggested by max...@cerno.tech) - dropped "drm/bridge: synopsis: Fix to properly handle HPD" - was a no longer needed workaround for a previous version (suggested by max...@cerno.tech) PATCH V4 2021-09-27 18:44:38: - fix setting output_port = 1 (issue found by p...@crapouillou.net) - ci20.dts: convert to use hdmi-connector (by h...@goldelico.com) - add a hdmi-regulator to control +5V power (by h...@goldelico.com) - added a fix to dw-hdmi to call drm_kms_helper_hotplug_event on plugin event detection (by h...@goldelico.com) - always allocate extended descriptor but initialize only for jz4780 (by h...@goldelico.com) - updated to work on top of "[PATCH v3 0/6] drm/ingenic: Various improvements v3" (by p...@crapouillou.net) - rebased to v5.13-rc3 PATCH V3 2021-08-08 07:10:50: This series adds HDMI support for JZ4780 and CI20 board (and fixes one IPU related issue in registration error path) - [patch 1/8] switched from mode_fixup to atomic_check (suggested by robert.f...@linaro.org) - the call to the dw-hdmi specialization is still called mode_fixup - [patch 3/8] diverse fixes for ingenic-drm-drv (suggested by p...@crapouillou.net) - factor out some non-HDMI features of the jz4780 into a separate patch - multiple fixes around max height - do not change regmap config but a copy on stack - define some constants - factor out fixing of drm_init error path for IPU into separate patch - use FIELD_PREP() - [patch 8/8] conversion to component framework dropped (suggested by laurent.pinch...@ideasonboard.com and p...@crapouillou.net) PATCH V2 2021-08-05 16:08:05: - code and commit messages revisited for checkpatch warnings - rebased on v5.14-rc4 - include (failed, hence RFC 8/8) attempt to convert to component framework (was suggested by Paul Cercueil a while ago) This series adds HDMI support for JZ4780 and CI20 board H. Nikolaus Schaller (3): drm/ingenic: prepare ingenic drm for later addition of JZ4780 MIPS: defconfig: CI20: configure for DRM_DW_HDMI_JZ4780 [RFC] MIPS: DTS: Ingenic: adjust register size to available registers Paul Boddie (4): drm/ingenic: Add support for JZ4780 and HDMI output drm/ingenic: Add dw-hdmi driver for jz4780 MIPS: DTS: jz4780: Account for Synopsys HDMI driver and LCD controllers MIPS: DTS: CI20: Add DT nodes for HDMI setup Sam Ravnborg (1): dt-bindings: display: Add ingenic,jz4780-dw-hdmi DT Schema .../display/bridge/ingenic,jz4780-hdmi.yaml | 76 +++ .../display/bridge/synopsys,dw-hdmi.yaml | 3 + arch/mips/boot/dts/ingenic/ci20.dts | 83 ++- arch/mips/boot/dts/ingenic/jz4725b.dtsi | 2 +- arch/mips/boot/dts/ingenic/jz4740.dtsi| 2 +-
[PATCH v7 1/8] drm/ingenic: prepare ingenic drm for later addition of JZ4780
This changes the way the regmap is allocated to prepare for the
later addition of the JZ4780 which has more registers and bits
than the others.
Therefore we make the regmap as big as the reg property in
the device tree tells.
Suggested-by: Paul Cercueil
Signed-off-by: H. Nikolaus Schaller
---
drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
index 462bc0f35f1bf..0bb590c3910d9 100644
--- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
+++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
@@ -173,7 +173,6 @@ static const struct regmap_config ingenic_drm_regmap_config
= {
.val_bits = 32,
.reg_stride = 4,
- .max_register = JZ_REG_LCD_SIZE1,
.writeable_reg = ingenic_drm_writeable_reg,
};
@@ -1011,6 +1010,8 @@ static int ingenic_drm_bind(struct device *dev, bool
has_components)
struct ingenic_drm_bridge *ib;
struct drm_device *drm;
void __iomem *base;
+ struct resource *res;
+ struct regmap_config regmap_config;
long parent_rate;
unsigned int i, clone_mask = 0;
int ret, irq;
@@ -1056,14 +1057,16 @@ static int ingenic_drm_bind(struct device *dev, bool
has_components)
drm->mode_config.funcs = _drm_mode_config_funcs;
drm->mode_config.helper_private = _drm_mode_config_helpers;
- base = devm_platform_ioremap_resource(pdev, 0);
+ base = devm_platform_get_and_ioremap_resource(pdev, 0, );
if (IS_ERR(base)) {
dev_err(dev, "Failed to get memory resource\n");
return PTR_ERR(base);
}
+ regmap_config = ingenic_drm_regmap_config;
+ regmap_config.max_register = res->end - res->start;
priv->map = devm_regmap_init_mmio(dev, base,
- _drm_regmap_config);
+ _config);
if (IS_ERR(priv->map)) {
dev_err(dev, "Failed to create regmap\n");
return PTR_ERR(priv->map);
--
2.33.0
[PATCH] drm/doc: Fix TTM acronym
The TTM acronym is defined for the first time in the documentation as "Translation Table Maps". Afterwards, "Translation Table Manager" is used as definition. Fix the first definition to avoid confusion. Signed-off-by: José Expósito --- Documentation/gpu/drm-mm.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/gpu/drm-mm.rst b/Documentation/gpu/drm-mm.rst index e0538083a2c0..198bcc1affa1 100644 --- a/Documentation/gpu/drm-mm.rst +++ b/Documentation/gpu/drm-mm.rst @@ -8,7 +8,7 @@ the very dynamic nature of many of that data, managing graphics memory efficiently is thus crucial for the graphics stack and plays a central role in the DRM infrastructure. -The DRM core includes two memory managers, namely Translation Table Maps +The DRM core includes two memory managers, namely Translation Table Manager (TTM) and Graphics Execution Manager (GEM). TTM was the first DRM memory manager to be developed and tried to be a one-size-fits-them all solution. It provides a single userspace API to accommodate the need of -- 2.25.1
[PATCH] drm: rcar-du: do not restart rcar-du groups on gen3
Restarting a display unit group can cause a visible flicker on the display.
Particularly when a LVDS display is connected to a Salvator board and an
HDMI display is (re)connected, then there will be 2 visible flickers on the
LVDS display:
1. during atomic_flush (The need_restart flag is set in this case by
rcar_du_vsp_enable.):
rcar_du_crtc_atomic_flush
rcar_du_crtc_update_planes
...
...
/* Restart the group if plane sources have changed. */
if (rcrtc->group->need_restart)
rcar_du_group_restart(rcrtc->group);
2. during atomic_enable:
rcar_du_crtc_atomic_enable
rcar_du_crtc_start
rcar_du_group_start_stop(rcrtc->group, true);
To avoid flickers in all use cases, do not restart DU groups on the Gen3
SoCs at all, since it is not required any more.
Signed-off-by: Michael Rodin
---
drivers/gpu/drm/rcar-du/rcar_du_group.c | 5 -
drivers/gpu/drm/rcar-du/rcar_du_vsp.c | 2 --
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c
b/drivers/gpu/drm/rcar-du/rcar_du_group.c
index 8665a1d..ff0a1c8 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_group.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c
@@ -250,7 +250,7 @@ void rcar_du_group_start_stop(struct rcar_du_group *rgrp,
bool start)
* when the display controller will have to be restarted.
*/
if (start) {
- if (rgrp->used_crtcs++ != 0)
+ if (rgrp->used_crtcs++ != 0 && rgrp->dev->info->gen != 3)
__rcar_du_group_start_stop(rgrp, false);
__rcar_du_group_start_stop(rgrp, true);
} else {
@@ -263,6 +263,9 @@ void rcar_du_group_restart(struct rcar_du_group *rgrp)
{
rgrp->need_restart = false;
+ if (rgrp->dev->info->gen == 3)
+ return;
+
__rcar_du_group_start_stop(rgrp, false);
__rcar_du_group_start_stop(rgrp, true);
}
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
index b7fc5b0..a652c06 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
@@ -88,8 +88,6 @@ void rcar_du_vsp_enable(struct rcar_du_crtc *crtc)
* Ensure that the plane source configuration takes effect by requesting
* a restart of the group. See rcar_du_plane_atomic_update() for a more
* detailed explanation.
-*
-* TODO: Check whether this is still needed on Gen3.
*/
crtc->group->need_restart = true;
--
2.7.4
Re: [PATCH v2] i2c: tegra: Add ACPI support
Hi Akhil, Thank you for the patch! Yet something to improve: [auto build test ERROR on tegra/for-next] [also build test ERROR on v5.16-rc2 next-20211123] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Akhil-R/i2c-tegra-Add-ACPI-support/20211123-151636 base: https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git for-next config: riscv-buildonly-randconfig-r005-20211123 (https://download.01.org/0day-ci/archive/20211124/202111240017.byyz7knz-...@intel.com/config.gz) compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 49e3838145dff1ec91c2e67a2cb562775c8d2a08) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install riscv cross compiling tool for clang build # apt-get install binutils-riscv64-linux-gnu # https://github.com/0day-ci/linux/commit/dec174be801f41a9e42f4381c59c2357c25e40fb git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Akhil-R/i2c-tegra-Add-ACPI-support/20211123-151636 git checkout dec174be801f41a9e42f4381c59c2357c25e40fb # save the config file to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 ARCH=riscv If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot All errors (new ones prefixed by >>): In file included from drivers/i2c/busses/i2c-tegra.c:13: In file included from include/linux/dmaengine.h:12: In file included from include/linux/scatterlist.h:9: In file included from arch/riscv/include/asm/io.h:136: include/asm-generic/io.h:464:31: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic] val = __raw_readb(PCI_IOBASE + addr); ~~ ^ include/asm-generic/io.h:477:61: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic] val = __le16_to_cpu((__le16 __force)__raw_readw(PCI_IOBASE + addr)); ~~ ^ include/uapi/linux/byteorder/little_endian.h:36:51: note: expanded from macro '__le16_to_cpu' #define __le16_to_cpu(x) ((__force __u16)(__le16)(x)) ^ In file included from drivers/i2c/busses/i2c-tegra.c:13: In file included from include/linux/dmaengine.h:12: In file included from include/linux/scatterlist.h:9: In file included from arch/riscv/include/asm/io.h:136: include/asm-generic/io.h:490:61: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic] val = __le32_to_cpu((__le32 __force)__raw_readl(PCI_IOBASE + addr)); ~~ ^ include/uapi/linux/byteorder/little_endian.h:34:51: note: expanded from macro '__le32_to_cpu' #define __le32_to_cpu(x) ((__force __u32)(__le32)(x)) ^ In file included from drivers/i2c/busses/i2c-tegra.c:13: In file included from include/linux/dmaengine.h:12: In file included from include/linux/scatterlist.h:9: In file included from arch/riscv/include/asm/io.h:136: include/asm-generic/io.h:501:33: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic] __raw_writeb(value, PCI_IOBASE + addr); ~~ ^ include/asm-generic/io.h:511:59: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic] __raw_writew((u16 __force)cpu_to_le16(value), PCI_IOBASE + addr); ~~ ^ include/asm-generic/io.h:521:59: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic] __raw_writel((u32 __force)cpu_to_le32(value), PCI_IOBASE + addr); ~~ ^ include/asm-generic/io.h:1024:55: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic] return (port > MMIO_UPPER_LIMIT) ? NULL : PCI_IOBASE + port; ~~ ^ >> drivers/i2c/busses/i2c-tegra.c:623:16: error: implicit declaration of >> function 'acpi_has_method' [-Werror,-Wimplicit-function-declaration] if (handle && acpi_has_method(handle, "_RST")) ^ drivers/i2c/busses
Re: [PATCH 3/3] drm/i915/gt: Improve "race-to-idle" at low frequencies
On Tue, 2021-11-23 at 09:17 +, Tvrtko Ursulin wrote: > > On 22/11/2021 18:44, Rodrigo Vivi wrote: > > On Wed, Nov 17, 2021 at 02:49:55PM -0800, Vinay Belgaumkar wrote: > > > From: Chris Wilson > > > > > > While the power consumption is proportional to the frequency, > > > there is > > > also a static draw for active gates. The longer we are able to > > > powergate > > > (rc6), the lower the static draw. Thus there is a sweetspot in > > > the > > > frequency/power curve where we run at higher frequency in order > > > to sleep > > > longer, aka race-to-idle. This is more evident at lower > > > frequencies, so > > > let's look to bump the frequency if we think we will benefit by > > > sleeping > > > longer at the higher frequency and so conserving power. > > > > > > Signed-off-by: Chris Wilson > > > Cc: Vinay Belgaumkar > > > Cc: Tvrtko Ursulin > > > > Please let's not increase the complexity here, unless we have a > > very good > > and documented reason. > > > > Before trying to implement anything smart like this in the driver > > I'd like > > to see data, power and performance results in different platforms > > and with > > different workloads. > > Who has such test suite and test farm which isn't focused to > workloads > from a single customer? ;( Okay, maybe we don't need to cover the world here. But without seen any data at all it is hard to make this call. > > Regards, > > Tvrtko
Re: [PATCH v1 1/1] drm: Replace kernel.h with the necessary inclusions
On Mon, Nov 15, 2021 at 01:35:47PM +0200, Andy Shevchenko wrote: > On Wed, Nov 10, 2021 at 05:39:33PM +0100, Thomas Zimmermann wrote: > > Am 10.11.21 um 17:34 schrieb Andy Shevchenko: > > > On Wed, Nov 10, 2021 at 3:55 PM Thomas Zimmermann > > > wrote: > > > > Am 10.11.21 um 11:24 schrieb Andy Shevchenko: > > ... > > > > > > +#include > > > > > > > > I built this patch on a recent drm-misc-next, but there's no > > > > linux/container_of.h > > > > > > Thank you for trying. It's in the upstream, whenever drm-misc-next > > > switches to newer/newest upstream it will be there. I assume it will > > > happen after v5.16-rc1? > > > > Yes, we'll certainly backmerge soon after rc1 has been released. If I forget > > to add the patch then, please send a reminder. > > > > Once the necessary headers are available, > > $ git log --oneline v5.16-rc1 -- include/linux/container_of.h > e1edc277e6f6 linux/container_of.h: switch to static_assert > d2a8ebbf8192 kernel.h: split out container_of() and typeof_member() macros > > > the patch is > > Acked-by: Thomas Zimmermann > > Thanks! Maybe I misunderstood something, I thought that DRM people may apply this, is it incorrect assumption? -- With Best Regards, Andy Shevchenko
Re: [PATCH] drm/msm/dpu: Add more of the INTF interrupt regions
On Tue, 23 Nov 2021 at 16:39, Bjorn Andersson
wrote:
>
> In addition to the other 7xxx INTF interrupt regions, SM8350 has
> additional INTF regions at 0x0ae37000, 0x0ae38000 and 0x0ae39000, define
> these. The 7xxx naming scheme of the bits are kept for consistency.
>
> Signed-off-by: Bjorn Andersson
> ---
> .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 18 ++
> .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 3 +++
> 2 files changed, 21 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> index d2b6dca487e3..a77a5eaa78ad 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> @@ -30,6 +30,9 @@
> #define MDP_AD4_INTR_STATUS_OFF0x420
> #define MDP_INTF_0_OFF_REV_7xxx 0x34000
> #define MDP_INTF_1_OFF_REV_7xxx 0x35000
> +#define MDP_INTF_2_OFF_REV_7xxx 0x36000
> +#define MDP_INTF_3_OFF_REV_7xxx 0x37000
> +#define MDP_INTF_4_OFF_REV_7xxx 0x38000
> #define MDP_INTF_5_OFF_REV_7xxx 0x39000
>
> /**
> @@ -110,6 +113,21 @@ static const struct dpu_intr_reg dpu_intr_set[] = {
> MDP_INTF_1_OFF_REV_7xxx+INTF_INTR_EN,
> MDP_INTF_1_OFF_REV_7xxx+INTF_INTR_STATUS
> },
> + {
> + MDP_INTF_2_OFF_REV_7xxx+INTF_INTR_CLEAR,
> + MDP_INTF_2_OFF_REV_7xxx+INTF_INTR_EN,
> + MDP_INTF_2_OFF_REV_7xxx+INTF_INTR_STATUS
> + },
> + {
> + MDP_INTF_3_OFF_REV_7xxx+INTF_INTR_CLEAR,
> + MDP_INTF_3_OFF_REV_7xxx+INTF_INTR_EN,
> + MDP_INTF_3_OFF_REV_7xxx+INTF_INTR_STATUS
> + },
> + {
> + MDP_INTF_4_OFF_REV_7xxx+INTF_INTR_CLEAR,
> + MDP_INTF_4_OFF_REV_7xxx+INTF_INTR_EN,
> + MDP_INTF_4_OFF_REV_7xxx+INTF_INTR_STATUS
> + },
> {
> MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_CLEAR,
> MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_EN,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> index d50e78c9f148..1ab75cccd145 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> @@ -26,6 +26,9 @@ enum dpu_hw_intr_reg {
> MDP_AD4_1_INTR,
> MDP_INTF0_7xxx_INTR,
> MDP_INTF1_7xxx_INTR,
> + MDP_INTF2_7xxx_INTR,
> + MDP_INTF3_7xxx_INTR,
> + MDP_INTF4_7xxx_INTR,
> MDP_INTF5_7xxx_INTR,
> MDP_INTR_MAX,
> };
Reviewed-by: Robert Foss
[Bug 211807] [drm:drm_dp_mst_dpcd_read] *ERROR* mstb 000000004e6288dd port 3: DPCD read on addr 0x60 for 1 bytes NAKed
https://bugzilla.kernel.org/show_bug.cgi?id=211807 --- Comment #16 from zwer...@mail.de --- (In reply to Alex Deucher from comment #13) > (In reply to zwerg12 from comment #12) > > As mentioned before, I get the same error with a monitor connected with DP > > to a Lenovo ThinkPad USB-C Dock Gen2. My Laptop has an Intel i7 10510U no > > additional graphics card. I am using Debian testing with the provided > kernel. > > > > > > During this my notebook monitor is blinking. > > This setup worked for around four weeks when suddenly these errors > occurred. > > > Can you bisect? I have never done it yet. But as soon as I am at home I can try. (In reply to Michel Dänzer from comment #15) > (In reply to Daan from comment #14) > > I also had this in my logs yesterday, right before my system locked > > completely (had to do a hard reset). > > That's probably coincidence. I get these messages on a regular basis, > without any bad behaviour. Sometimes when I get this message there is no bad behavior but sometimes I also have to do a hard reset. Without the docking station I never had to make a hard reset. -- You may reply to this email to add a comment. You are receiving this mail because: You are watching the assignee of the bug.
Re: [PATCH 4/4] drm/msm/a6xx: Capture gmu log in devcoredump
On 11/23/2021 12:36 AM, Rob Clark wrote:
On Mon, Nov 22, 2021 at 10:26 AM Rob Clark wrote:
On Thu, Nov 18, 2021 at 2:21 AM Akhil P Oommen wrote:
Capture gmu log in coredump to enhance debugging.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 41 +
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +-
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 ++
3 files changed, 44 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
index 7501849..9fa3fa6 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
@@ -42,6 +42,8 @@ struct a6xx_gpu_state {
struct a6xx_gpu_state_obj *cx_debugbus;
int nr_cx_debugbus;
+ struct msm_gpu_state_bo *gmu_log;
+
struct list_head objs;
};
@@ -800,6 +802,30 @@ static void a6xx_get_gmu_registers(struct msm_gpu *gpu,
_state->gmu_registers[2], false);
}
+static void a6xx_get_gmu_log(struct msm_gpu *gpu,
+ struct a6xx_gpu_state *a6xx_state)
+{
+ struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
+ struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
+ struct a6xx_gmu *gmu = _gpu->gmu;
+ struct msm_gpu_state_bo *gmu_log;
+
+ gmu_log = state_kcalloc(a6xx_state,
+ 1, sizeof(*a6xx_state->gmu_log));
+ if (!gmu_log)
+ return;
+
+ gmu_log->iova = gmu->log.iova;
+ gmu_log->size = gmu->log.size;
+ gmu_log->data = kvzalloc(gmu_log->size, GFP_KERNEL);
+ if (!gmu_log->data)
+ return;
+
+ memcpy(gmu_log->data, gmu->log.virt, gmu->log.size);
+
+ a6xx_state->gmu_log = gmu_log;
+}
+
#define A6XX_GBIF_REGLIST_SIZE 1
static void a6xx_get_registers(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state,
@@ -937,6 +963,8 @@ struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu
*gpu)
a6xx_get_gmu_registers(gpu, a6xx_state);
+ a6xx_get_gmu_log(gpu, a6xx_state);
+
/* If GX isn't on the rest of the data isn't going to be accessible */
if (!a6xx_gmu_gx_is_on(_gpu->gmu))
return _state->base;
@@ -978,6 +1006,9 @@ static void a6xx_gpu_state_destroy(struct kref *kref)
struct a6xx_gpu_state *a6xx_state = container_of(state,
struct a6xx_gpu_state, base);
+ if (a6xx_state->gmu_log && a6xx_state->gmu_log->data)
+ kvfree(a6xx_state->gmu_log->data);
+
list_for_each_entry_safe(obj, tmp, _state->objs, node)
kfree(obj);
@@ -1191,6 +1222,16 @@ void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state
*state,
adreno_show(gpu, state, p);
+ drm_puts(p, "gmu-log:\n");
+ if (a6xx_state->gmu_log) {
+ struct msm_gpu_state_bo *gmu_log = a6xx_state->gmu_log;
+
+ drm_printf(p, "iova: 0x%016llx\n", gmu_log->iova);
+ drm_printf(p, "size: %d\n", gmu_log->size);
fwiw, that wants to be:
+ drm_printf(p, "size: %zu\n", gmu_log->size);
with that fixed, r-b
Hmm, actually, I seem to be getting an empty log.. is special gmu fw,
or non-fused device needed for this to work?
BR,
-R
No, there is no special fw. I tested this on 7c3 and it worked for me.
a618/a630 has an old version of gmu firmware which is pretty different
from the newer ones. Let me check.
-Akhil.
BR,
-R
+ adreno_show_object(p, _log->data, gmu_log->size,
+ _log->encoded);
+ }
+
drm_puts(p, "registers:\n");
for (i = 0; i < a6xx_state->nr_registers; i++) {
struct a6xx_gpu_state_obj *obj = _state->registers[i];
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 7486652..7d1ff20 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -630,7 +630,7 @@ static char *adreno_gpu_ascii85_encode(u32 *src, size_t len)
}
/* len is expected to be in bytes */
-static void adreno_show_object(struct drm_printer *p, void **ptr, int len,
+void adreno_show_object(struct drm_printer *p, void **ptr, int len,
bool *encoded)
{
if (!*ptr || !len)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 225c277..6762308 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -306,6 +306,8 @@ void adreno_gpu_state_destroy(struct msm_gpu_state *state);
int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state);
int adreno_gpu_state_put(struct msm_gpu_state *state);
+void adreno_show_object(struct drm_printer *p, void **ptr, int len,
+ bool *encoded);
/*
* Common helper function to initialize the default address
[PATCH] drm/msm/dpu: Add more of the INTF interrupt regions
In addition to the other 7xxx INTF interrupt regions, SM8350 has
additional INTF regions at 0x0ae37000, 0x0ae38000 and 0x0ae39000, define
these. The 7xxx naming scheme of the bits are kept for consistency.
Signed-off-by: Bjorn Andersson
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 18 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 3 +++
2 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
index d2b6dca487e3..a77a5eaa78ad 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
@@ -30,6 +30,9 @@
#define MDP_AD4_INTR_STATUS_OFF0x420
#define MDP_INTF_0_OFF_REV_7xxx 0x34000
#define MDP_INTF_1_OFF_REV_7xxx 0x35000
+#define MDP_INTF_2_OFF_REV_7xxx 0x36000
+#define MDP_INTF_3_OFF_REV_7xxx 0x37000
+#define MDP_INTF_4_OFF_REV_7xxx 0x38000
#define MDP_INTF_5_OFF_REV_7xxx 0x39000
/**
@@ -110,6 +113,21 @@ static const struct dpu_intr_reg dpu_intr_set[] = {
MDP_INTF_1_OFF_REV_7xxx+INTF_INTR_EN,
MDP_INTF_1_OFF_REV_7xxx+INTF_INTR_STATUS
},
+ {
+ MDP_INTF_2_OFF_REV_7xxx+INTF_INTR_CLEAR,
+ MDP_INTF_2_OFF_REV_7xxx+INTF_INTR_EN,
+ MDP_INTF_2_OFF_REV_7xxx+INTF_INTR_STATUS
+ },
+ {
+ MDP_INTF_3_OFF_REV_7xxx+INTF_INTR_CLEAR,
+ MDP_INTF_3_OFF_REV_7xxx+INTF_INTR_EN,
+ MDP_INTF_3_OFF_REV_7xxx+INTF_INTR_STATUS
+ },
+ {
+ MDP_INTF_4_OFF_REV_7xxx+INTF_INTR_CLEAR,
+ MDP_INTF_4_OFF_REV_7xxx+INTF_INTR_EN,
+ MDP_INTF_4_OFF_REV_7xxx+INTF_INTR_STATUS
+ },
{
MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_CLEAR,
MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_EN,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
index d50e78c9f148..1ab75cccd145 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
@@ -26,6 +26,9 @@ enum dpu_hw_intr_reg {
MDP_AD4_1_INTR,
MDP_INTF0_7xxx_INTR,
MDP_INTF1_7xxx_INTR,
+ MDP_INTF2_7xxx_INTR,
+ MDP_INTF3_7xxx_INTR,
+ MDP_INTF4_7xxx_INTR,
MDP_INTF5_7xxx_INTR,
MDP_INTR_MAX,
};
--
2.33.1
Re: [PATCH] drm/bridge: megachips: Ensure both bridges are probed before registration
Hey Martyn, On Tue, 16 Nov 2021 at 13:28, Martyn Welch wrote: > > In the configuration used by the b850v3, the STDP2690 is used to read EDID > data whilst it's the STDP4028 which can detect when monitors are connected. > > This can result in problems at boot with monitors connected when the > STDP4028 is probed first, a monitor is detected and an attempt is made to > read the EDID data before the STDP2690 has probed: > > [3.795721] Unable to handle kernel NULL pointer dereference at virtual > address 0018 > [3.803845] pgd = (ptrval) > [3.806581] [0018] *pgd= > [3.810180] Internal error: Oops: 5 [#1] SMP ARM > [3.814813] Modules linked in: > [3.817879] CPU: 0 PID: 64 Comm: kworker/u4:1 Not tainted 5.15.0 #1 > [3.824161] Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree) > [3.830705] Workqueue: events_unbound deferred_probe_work_func > [3.836565] PC is at stdp2690_get_edid+0x44/0x19c > [3.841286] LR is at ge_b850v3_lvds_get_modes+0x2c/0x5c > [3.846526] pc : [<805eae10>]lr : [<805eb138>]psr: 8013 > [3.852802] sp : 81c359d0 ip : 7dbb550b fp : 81c35a1c > [3.858037] r10: 81c73840 r9 : 81c73894 r8 : 816d9800 > [3.863270] r7 : r6 : 81c34000 r5 : r4 : 810c35f0 > [3.869808] r3 : 80e3e294 r2 : 0080 r1 : 0cc0 r0 : 81401180 > [3.876349] Flags: Nzcv IRQs on FIQs on Mode SVC_32 ISA ARM Segment > none > [3.883499] Control: 10c5387d Table: 1000404a DAC: 0051 > [3.889254] Register r0 information: slab kmem_cache start 81401180 > pointer offset 0 > [3.897034] Register r1 information: non-paged memory > [3.902097] Register r2 information: non-paged memory > [3.907160] Register r3 information: non-slab/vmalloc memory > [3.912832] Register r4 information: non-slab/vmalloc memory > [3.918503] Register r5 information: NULL pointer > [3.923217] Register r6 information: non-slab/vmalloc memory > [3.928887] Register r7 information: NULL pointer > [3.933601] Register r8 information: slab kmalloc-1k start 816d9800 > pointer offset 0 size 1024 > [3.942244] Register r9 information: slab kmalloc-2k start 81c73800 > pointer offset 148 size 2048 > [3.951058] Register r10 information: slab kmalloc-2k start 81c73800 > pointer offset 64 size 2048 > [3.959873] Register r11 information: non-slab/vmalloc memory > [3.965632] Register r12 information: non-paged memory > [3.970781] Process kworker/u4:1 (pid: 64, stack limit = 0x(ptrval)) > [3.977148] Stack: (0x81c359d0 to 0x81c36000) > [3.981517] 59c0: 80b2b668 80b2b5bc > 02e2 034e > [3.989712] 59e0: 81c35a8c 816d98e8 81c35a14 7dbb550b 805bfcd0 810c35f0 > 81c73840 824addc0 > [3.997906] 5a00: 1000 816d9800 81c73894 81c73840 81c35a34 81c35a20 > 805eb138 805eadd8 > [4.006099] 5a20: 810c35f0 0045 81c35adc 81c35a38 80594188 805eb118 > 80d7c788 80dd1848 > [4.014292] 5a40: 81c35a50 80dca950 811194d3 80dca7c4 80dca944 > 80dca91c 816d9800 > [4.022485] 5a60: 81c34000 81c760a8 816d9800 80c58c98 810c35f0 816d98e8 > 1000 1000 > [4.030678] 5a80: 8017712c 81c6 0002 0001 > > [4.038870] 5aa0: 816d9900 816d9900 7dbb550b 805c700c 0008 > 826282c8 826282c8 > [4.047062] 5ac0: 1000 81e1ce40 1000 0002 81c35bf4 81c35ae0 > 805d9694 80593fc0 > [4.055255] 5ae0: 8017a970 80179ad8 0179 81c35bcc 81c35b00 > 80177108 8017a950 > [4.063447] 5b00: 81c35b10 81c34000 81004fd8 81010a38 > 0059 > [4.071639] 5b20: 816d98d4 81fbb718 0013 826282c8 8017a940 81c35b40 > 81134448 0400 > [4.079831] 5b40: 0178 e063b9c1 c249 0040 > 0008 > [4.088024] 5b60: 82628300 82628380 81c34000 > 81fbb700 82628340 > [4.096216] 5b80: 826283c0 1000 0010 816d9800 826282c0 > 801766f8 > [4.104408] 5ba0: 81004fd8 0049 0001 > 80dcf940 80178de4 > [4.112601] 5bc0: 81c35c0c 7dbb550b 80178de4 81fbb700 0010 0010 > 810c35f4 81e1ce40 > [4.120793] 5be0: 81c40908 000c 81c35c64 81c35bf8 805a7f18 805d94a0 > 81c35c3c 816d9800 > [4.128985] 5c00: 0010 81c34000 81c35c2c 81c35c18 8012fce0 805be90c > 81c35c3c 81c35c28 > [4.137178] 5c20: 805be90c 80173210 81fbb600 81fbb6b4 81c35c5c 7dbb550b > 81c35c64 81fbb700 > [4.145370] 5c40: 816d9800 0010 810c35f4 81e1ce40 81c40908 000c > 81c35c84 81c35c68 > [4.153565] 5c60: 805a8c78 805a7ed0 816d9800 81fbb700 0010 > 81c35cac 81c35c88 > [4.161758] 5c80: 805a8dc4 805a8b68 816d9800 816d9800 > 8179f810 810c42d0 > [4.169950] 5ca0: 81c35ccc 81c35cb0 805e47b0 805a8d18 824aa240 81e1ea80 > 81c40908 81126b60 > [4.178144] 5cc0: 81c35d14 81c35cd0
Re: [RFC v2 01/22] drm: RFC for Plane Color Hardware Pipeline
On 2021-09-06 17:38, Uma Shankar wrote: > This is a RFC proposal for plane color hardware blocks. > It exposes the property interface to userspace and calls > out the details or interfaces created and the intended > purpose. > > Credits: Ville Syrjälä > Signed-off-by: Uma Shankar > --- > Documentation/gpu/rfc/drm_color_pipeline.rst | 167 +++ > 1 file changed, 167 insertions(+) > create mode 100644 Documentation/gpu/rfc/drm_color_pipeline.rst > > diff --git a/Documentation/gpu/rfc/drm_color_pipeline.rst > b/Documentation/gpu/rfc/drm_color_pipeline.rst > new file mode 100644 > index ..0d1ca858783b > --- /dev/null > +++ b/Documentation/gpu/rfc/drm_color_pipeline.rst > @@ -0,0 +1,167 @@ > +== > +Display Color Pipeline: Proposed DRM Properties > +== > + > +This is how a typical display color hardware pipeline looks like: > + +---+ > + |RAM| > + | +--++-++-+ | > + | | FB 1 || FB 2 || FB N| | > + | +--++-++-+ | > + +---+ > + | Plane Color Hardware Block | > + ++ > + | +---v-+ +---v---+ +---v--+ | > + | | Plane A | | Plane B | | Plane N | | > + | | DeGamma | | Degamma | | Degamma | | > + | +---+-+ +---+---+ +---+--+ | > + | | | || > + | +---v-+ +---v---+ +---v--+ | > + | |Plane A | | Plane B | | Plane N | | > + | |CSC/CTM | | CSC/CTM | | CSC/CTM | | > + | +---+-+ ++--+ ++-+ | > + | | | | | > + | +---v-+ +v--+ +v-+ | > + | | Plane A | | Plane B | | Plane N | | > + | | Gamma | | Gamma | | Gamma| | > + | +---+-+ ++--+ ++-+ | > + | | | | | > + ++ > ++--v--v---v---| > +|| || > +|| Pipe Blender|| > ++++ > +||| > +|+---v--+ | > +|| Pipe DeGamma| | > +|| | | > +|+---+--+ | > +||Pipe Color | > +|+---v--+ Hardware| > +|| Pipe CSC/CTM| | > +|| | | > +|+---+--+ | > +||| > +|+---v--+ | > +|| Pipe Gamma | | > +|| | | > +|+---+--+ | > +||| > ++-+ > + | > + v > + Pipe Output > + This diagram defines what happens before and after the blending space but did where does scaling fit into it? Scaling can look different when performed in linear or non-linear space so I think it is important to define where in the pipeline it sits. In my view scaling would happen between plane degamma and plane CSC. Harry > +Proposal is to have below properties for a plane: > + > +* Plane Degamma or Pre-Curve: > + * This will be used to linearize the input framebuffer data. > + * It will apply the reverse of the color transfer function. > + * It can be a degamma curve or OETF for HDR. > + * This linear data can be further acted on by the following > + * color hardware blocks in the display hardware pipeline > + > +UAPI Name: PLANE_DEGAMMA_MODE > +Description: Enum property with values as blob_id's which advertizes the > + possible degamma modes and lut ranges supported by the platform. > + This allows userspace to query and get the plane degamma color > + caps and choose the appropriate degamma mode and create lut values > + accordingly. > + > +UAPI Name: PLANE_DEGAMMA_LUT > +Description: Blob property which allows a userspace to provide LUT values > + to apply degamma curve using the h/w plane degamma processing > + engine, thereby making the content as linear for further color > + processing. Userspace gets the size of LUT and precision etc > + from PLANE_DEGAMA_MODE_PROPERTY > + > +* Plane CTM > + * This is a Property to program the color transformation matrix. > + * This can be used to perform a color space conversion like > + *
Re: [RFC v2 05/22] drm/i915/xelpd: Define Degamma Lut range struct for HDR planes
On 2021-11-12 03:37, Pekka Paalanen wrote:
> On Thu, 11 Nov 2021 21:58:35 +
> "Shankar, Uma" wrote:
>
>>> -Original Message-
>>> From: Harry Wentland
>>> Sent: Friday, November 12, 2021 2:41 AM
>>> To: Shankar, Uma ; Ville Syrjälä
>>>
>>> Cc: intel-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org;
>>> ppaala...@gmail.com; brian.star...@arm.com; sebast...@sebastianwick.net;
>>> shashank.sha...@amd.com
>>> Subject: Re: [RFC v2 05/22] drm/i915/xelpd: Define Degamma Lut range struct
>>> for
>>> HDR planes
>>>
>>>
>>>
>>> On 2021-11-11 15:42, Shankar, Uma wrote:
> -Original Message-
> From: Ville Syrjälä
> Sent: Thursday, November 11, 2021 10:13 PM
> To: Harry Wentland
> Cc: Shankar, Uma ;
> intel-...@lists.freedesktop.org; dri- de...@lists.freedesktop.org;
> ppaala...@gmail.com; brian.star...@arm.com;
> sebast...@sebastianwick.net; shashank.sha...@amd.com
> Subject: Re: [RFC v2 05/22] drm/i915/xelpd: Define Degamma Lut range
> struct for HDR planes
>
> On Thu, Nov 11, 2021 at 10:17:17AM -0500, Harry Wentland wrote:
>>
>>
>> On 2021-09-06 17:38, Uma Shankar wrote:
>>> Define the structure with XE_LPD degamma lut ranges. HDR and SDR
>>> planes have different capabilities, implemented respective
>>> structure for the HDR planes.
>>>
>>> Signed-off-by: Uma Shankar
>>> ---
>>> drivers/gpu/drm/i915/display/intel_color.c | 52
>>> ++
>>> 1 file changed, 52 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
>>> b/drivers/gpu/drm/i915/display/intel_color.c
>>> index afcb4bf3826c..6403bd74324b 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_color.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_color.c
>>> @@ -2092,6 +2092,58 @@ static void icl_read_luts(struct
>>> intel_crtc_state
> *crtc_state)
>>> }
>>> }
>>>
>>> + /* FIXME input bpc? */
>>> +__maybe_unused
>>> +static const struct drm_color_lut_range d13_degamma_hdr[] = {
>>> + /* segment 1 */
>>> + {
>>> + .flags = (DRM_MODE_LUT_GAMMA |
>>> + DRM_MODE_LUT_REFLECT_NEGATIVE |
>>> + DRM_MODE_LUT_INTERPOLATE |
>>> + DRM_MODE_LUT_NON_DECREASING),
>>> + .count = 128,
>>> + .input_bpc = 24, .output_bpc = 16,
>>> + .start = 0, .end = (1 << 24) - 1,
>>> + .min = 0, .max = (1 << 24) - 1,
>>> + },
>>> + /* segment 2 */
>>> + {
>>> + .flags = (DRM_MODE_LUT_GAMMA |
>>> + DRM_MODE_LUT_REFLECT_NEGATIVE |
>>> + DRM_MODE_LUT_INTERPOLATE |
>>> + DRM_MODE_LUT_REUSE_LAST |
>>> + DRM_MODE_LUT_NON_DECREASING),
>>> + .count = 1,
>>> + .input_bpc = 24, .output_bpc = 16,
>>> + .start = (1 << 24) - 1, .end = 1 << 24,
>>> + .min = 0, .max = (1 << 27) - 1,
>>> + },
>>> + /* Segment 3 */
>>> + {
>>> + .flags = (DRM_MODE_LUT_GAMMA |
>>> + DRM_MODE_LUT_REFLECT_NEGATIVE |
>>> + DRM_MODE_LUT_INTERPOLATE |
>>> + DRM_MODE_LUT_REUSE_LAST |
>>> + DRM_MODE_LUT_NON_DECREASING),
>>> + .count = 1,
>>> + .input_bpc = 24, .output_bpc = 16,
>>> + .start = 1 << 24, .end = 3 << 24,
>>> + .min = 0, .max = (1 << 27) - 1,
>>> + },
>>> + /* Segment 4 */
>>> + {
>>> + .flags = (DRM_MODE_LUT_GAMMA |
>>> + DRM_MODE_LUT_REFLECT_NEGATIVE |
>>> + DRM_MODE_LUT_INTERPOLATE |
>>> + DRM_MODE_LUT_REUSE_LAST |
>>> + DRM_MODE_LUT_NON_DECREASING),
>>> + .count = 1,
>>> + .input_bpc = 24, .output_bpc = 16,
>>> + .start = 3 << 24, .end = 7 << 24,
>>> + .min = 0, .max = (1 << 27) - 1,
>>> + },
>>> +};
>>
>> If I understand this right, userspace would need this definition in
>> order to populate the degamma blob. Should this sit in a UAPI header?
>
> Are you asking whether 'struct drm_color_lut_range` is defined in any
> userspace visible header?
>
> It seems to be in patch 2.
>
Hi Harry, Pekka and Ville,
Sorry for being a bit late on the replies, got side tracked with various
issues.
I am back on this. Apologies for delay.
> My original idea (not sure it's fully realized in this series) is to
> have a new
Re: [PATCH v2] i2c: tegra: Add ACPI support
23.11.2021 10:15, Akhil R пишет:
> Add support for ACPI based device registration so that the driver
> can be also enabled through ACPI table.
>
> Signed-off-by: Akhil R
> ---
> drivers/i2c/busses/i2c-tegra.c | 52
> --
> 1 file changed, 40 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
> index c883044..8e47889 100644
> --- a/drivers/i2c/busses/i2c-tegra.c
> +++ b/drivers/i2c/busses/i2c-tegra.c
> @@ -6,6 +6,7 @@
> * Author: Colin Cross
> */
>
> +#include
> #include
> #include
> #include
> @@ -608,6 +609,7 @@ static int tegra_i2c_wait_for_config_load(struct
> tegra_i2c_dev *i2c_dev)
> static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
> {
> u32 val, clk_divisor, clk_multiplier, tsu_thd, tlow, thigh, non_hs_mode;
> + acpi_handle handle = ACPI_HANDLE(i2c_dev->dev);
> int err;
>
> /*
> @@ -618,7 +620,11 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
>* emit a noisy warning on error, which won't stay unnoticed and
>* won't hose machine entirely.
>*/
> - err = reset_control_reset(i2c_dev->rst);
> + if (handle && acpi_has_method(handle, "_RST"))
Which SoC version doesn't have "_RST" method? If neither, then please
remove this check.
> + err = (acpi_evaluate_object(handle, "_RST", NULL, NULL));
Please remove parens around acpi_evaluate_object(). Why you added them?
> + else
> + err = reset_control_reset(i2c_dev->rst);
> +
> WARN_ON_ONCE(err);
>
> if (i2c_dev->is_dvc)
> @@ -1627,12 +1633,12 @@ static void tegra_i2c_parse_dt(struct tegra_i2c_dev
> *i2c_dev)
> bool multi_mode;
> int err;
>
> - err = of_property_read_u32(np, "clock-frequency",
> -_dev->bus_clk_rate);
> + err = device_property_read_u32(i2c_dev->dev, "clock-frequency",
> +_dev->bus_clk_rate);
> if (err)
> i2c_dev->bus_clk_rate = I2C_MAX_STANDARD_MODE_FREQ;
>
> - multi_mode = of_property_read_bool(np, "multi-master");
> + multi_mode = device_property_read_bool(i2c_dev->dev, "multi-master");
> i2c_dev->multimaster_mode = multi_mode;
>
> if (of_device_is_compatible(np, "nvidia,tegra20-i2c-dvc"))
> @@ -1642,10 +1648,25 @@ static void tegra_i2c_parse_dt(struct tegra_i2c_dev
> *i2c_dev)
> i2c_dev->is_vi = true;
> }
How are you going to differentiate the VI I2C from a non-VI? This
doesn't look right.
>
> +static int tegra_i2c_init_reset(struct tegra_i2c_dev *i2c_dev)
> +{
> + if (has_acpi_companion(i2c_dev->dev))
> + return 0;
> +
> + i2c_dev->rst = devm_reset_control_get_exclusive(i2c_dev->dev, "i2c");
> + if (IS_ERR(i2c_dev->rst))
> + return PTR_ERR(i2c_dev->rst);
> +
> + return 0;
> +}
> +
> static int tegra_i2c_init_clocks(struct tegra_i2c_dev *i2c_dev)
> {
> int err;
>
> + if (has_acpi_companion(i2c_dev->dev))
> + return 0;
> +
> i2c_dev->clocks[i2c_dev->nclocks++].id = "div-clk";
>
> if (i2c_dev->hw == _i2c_hw || i2c_dev->hw == _i2c_hw)
> @@ -1720,7 +1741,7 @@ static int tegra_i2c_probe(struct platform_device *pdev)
> init_completion(_dev->msg_complete);
> init_completion(_dev->dma_complete);
>
> - i2c_dev->hw = of_device_get_match_data(>dev);
> + i2c_dev->hw = device_get_match_data(>dev);
> i2c_dev->cont_id = pdev->id;
> i2c_dev->dev = >dev;
>
> @@ -1746,15 +1767,13 @@ static int tegra_i2c_probe(struct platform_device
> *pdev)
> if (err)
> return err;
>
> - i2c_dev->rst = devm_reset_control_get_exclusive(i2c_dev->dev, "i2c");
> - if (IS_ERR(i2c_dev->rst)) {
> - dev_err_probe(i2c_dev->dev, PTR_ERR(i2c_dev->rst),
> - "failed to get reset control\n");
> - return PTR_ERR(i2c_dev->rst);
> - }
> -
> tegra_i2c_parse_dt(i2c_dev);
>
> + err = tegra_i2c_init_reset(i2c_dev);
> + if (err)
> + return dev_err_probe(i2c_dev->dev, err,
> + "failed to get reset control\n");
This is inconsistent with tegra_i2c_init_clocks() which returns err
directly and prints error message within the function. Please move the
dev_err_probe() into tegra_i2c_init_reset() to make it consistent, like
I suggested before.
Please don't reply with a new version of the patch to the old thread,
always send a new version separately. Otherwise it's more difficult to
follow patches.
Lastly, each new version of a patch must contain changelog. I don't see
changelog here, please add it to v3 after the " ---" separator of the
commit message. Thanks!
Example:
Commit message.
Signed-off-by: Akhil R
---
drivers/i2c/busses/i2c-tegra.c | 52
--
1 file changed, 40 insertions(+), 12 deletions(-)
[PATCH 25/26] amdgpu: remove DMA-buf fence workaround
Not needed any more now we have that inside the framework.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 52 +++--
2 files changed, 6 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h
index 044b41f0bfd9..529d52a204cf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h
@@ -34,7 +34,6 @@ struct amdgpu_fpriv;
struct amdgpu_bo_list_entry {
struct ttm_validate_buffer tv;
struct amdgpu_bo_va *bo_va;
- struct dma_fence_chain *chain;
uint32_tpriority;
struct page **user_pages;
booluser_invalidated;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 92091e800022..413606d10080 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -576,14 +576,6 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
e->bo_va = amdgpu_vm_bo_find(vm, bo);
-
- if (bo->tbo.base.dma_buf && !amdgpu_bo_explicit_sync(bo)) {
- e->chain = dma_fence_chain_alloc();
- if (!e->chain) {
- r = -ENOMEM;
- goto error_validate;
- }
- }
}
amdgpu_cs_get_threshold_for_moves(p->adev, >bytes_moved_threshold,
@@ -634,13 +626,8 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
}
error_validate:
- if (r) {
- amdgpu_bo_list_for_each_entry(e, p->bo_list) {
- dma_fence_chain_free(e->chain);
- e->chain = NULL;
- }
+ if (r)
ttm_eu_backoff_reservation(>ticket, >validated);
- }
out:
return r;
}
@@ -680,17 +667,9 @@ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser
*parser, int error,
{
unsigned i;
- if (error && backoff) {
- struct amdgpu_bo_list_entry *e;
-
- amdgpu_bo_list_for_each_entry(e, parser->bo_list) {
- dma_fence_chain_free(e->chain);
- e->chain = NULL;
- }
-
+ if (error && backoff)
ttm_eu_backoff_reservation(>ticket,
>validated);
- }
for (i = 0; i < parser->num_post_deps; i++) {
drm_syncobj_put(parser->post_deps[i].syncobj);
@@ -1265,29 +1244,10 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
amdgpu_vm_move_to_lru_tail(p->adev, >vm);
- amdgpu_bo_list_for_each_entry(e, p->bo_list) {
- struct dma_resv *resv = e->tv.bo->base.resv;
- struct dma_fence_chain *chain = e->chain;
- struct dma_resv_iter cursor;
- struct dma_fence *fence;
-
- if (!chain)
- continue;
-
- /*
-* Work around dma_resv shortcommings by wrapping up the
-* submission in a dma_fence_chain and add it as exclusive
-* fence.
-*/
- dma_resv_for_each_fence(, resv,
- DMA_RESV_USAGE_WRITE,
- fence) {
- break;
- }
- dma_fence_chain_init(chain, fence, dma_fence_get(p->fence), 1);
- dma_resv_add_fence(resv, >base, DMA_RESV_USAGE_WRITE);
- e->chain = NULL;
- }
+ /* For now manually add the resulting fence as writer as well */
+ amdgpu_bo_list_for_each_entry(e, p->bo_list)
+ dma_resv_add_fence(e->tv.bo->base.resv, p->fence,
+ DMA_RESV_USAGE_WRITE);
ttm_eu_fence_buffer_objects(>ticket, >validated, p->fence);
mutex_unlock(>adev->notifier_lock);
--
2.25.1
[PATCH 22/26] dma-buf: add enum dma_resv_usage
This change adds the dma_resv_usage enum and allows us to specify why a
dma_resv object is queried for its containing fences.
Additional to that a dma_resv_usage_rw() helper function is added to aid
retrieving the fences for a read or write userspace submission.
This is then deployed to the different query functions of the dma_resv
object and all of their users.
Signed-off-by: Christian König
---
drivers/dma-buf/dma-buf.c | 3 +-
drivers/dma-buf/dma-resv.c| 33 +++---
drivers/dma-buf/st-dma-resv.c | 48
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c| 4 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 5 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c| 4 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c| 4 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c| 7 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +-
drivers/gpu/drm/drm_gem.c | 6 +-
drivers/gpu/drm/drm_gem_atomic_helper.c | 2 +-
drivers/gpu/drm/etnaviv/etnaviv_gem.c | 6 +-
drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c | 10 +-
.../gpu/drm/i915/display/intel_atomic_plane.c | 3 +-
drivers/gpu/drm/i915/gem/i915_gem_busy.c | 4 +-
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_wait.c | 6 +-
.../drm/i915/gem/selftests/i915_gem_dmabuf.c | 3 +-
drivers/gpu/drm/i915/i915_request.c | 3 +-
drivers/gpu/drm/i915/i915_sw_fence.c | 2 +-
drivers/gpu/drm/msm/msm_gem.c | 3 +-
drivers/gpu/drm/nouveau/dispnv50/wndw.c | 3 +-
drivers/gpu/drm/nouveau/nouveau_bo.c | 8 +-
drivers/gpu/drm/nouveau/nouveau_fence.c | 3 +-
drivers/gpu/drm/nouveau/nouveau_gem.c | 3 +-
drivers/gpu/drm/panfrost/panfrost_drv.c | 3 +-
drivers/gpu/drm/qxl/qxl_debugfs.c | 3 +-
drivers/gpu/drm/radeon/radeon_display.c | 3 +-
drivers/gpu/drm/radeon/radeon_gem.c | 9 +-
drivers/gpu/drm/radeon/radeon_mn.c| 4 +-
drivers/gpu/drm/radeon/radeon_sync.c | 2 +-
drivers/gpu/drm/radeon/radeon_uvd.c | 4 +-
drivers/gpu/drm/scheduler/sched_main.c| 3 +-
drivers/gpu/drm/ttm/ttm_bo.c | 18 +--
drivers/gpu/drm/vgem/vgem_fence.c | 4 +-
drivers/gpu/drm/virtio/virtgpu_ioctl.c| 5 +-
drivers/gpu/drm/vmwgfx/vmwgfx_bo.c| 4 +-
drivers/gpu/drm/vmwgfx/vmwgfx_resource.c | 4 +-
drivers/infiniband/core/umem_dmabuf.c | 3 +-
include/linux/dma-resv.h | 106 +++---
46 files changed, 244 insertions(+), 126 deletions(-)
diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c
index 602b12d7470d..528983d3ba64 100644
--- a/drivers/dma-buf/dma-buf.c
+++ b/drivers/dma-buf/dma-buf.c
@@ -1124,7 +1124,8 @@ static int __dma_buf_begin_cpu_access(struct dma_buf
*dmabuf,
long ret;
/* Wait on any implicit rendering fences */
- ret = dma_resv_wait_timeout(resv, write, true, MAX_SCHEDULE_TIMEOUT);
+ ret = dma_resv_wait_timeout(resv, dma_resv_usage_rw(write),
+ true, MAX_SCHEDULE_TIMEOUT);
if (ret < 0)
return ret;
diff --git a/drivers/dma-buf/dma-resv.c b/drivers/dma-buf/dma-resv.c
index 3b0001c5ff3a..7ef8182a4b59 100644
--- a/drivers/dma-buf/dma-resv.c
+++ b/drivers/dma-buf/dma-resv.c
@@ -473,7 +473,7 @@ static void dma_resv_iter_restart_unlocked(struct
dma_resv_iter *cursor)
cursor->seq = read_seqcount_begin(>obj->seq);
cursor->index = -1;
cursor->shared_count = 0;
- if (cursor->all_fences) {
+ if (cursor->usage >= DMA_RESV_USAGE_READ) {
cursor->fences = dma_resv_shared_list(cursor->obj);
if (cursor->fences)
cursor->shared_count = cursor->fences->shared_count;
@@ -580,7 +580,7 @@ struct dma_fence *dma_resv_iter_first(struct dma_resv_iter
*cursor)
dma_resv_assert_held(cursor->obj);
cursor->index = 0;
- if (cursor->all_fences)
+ if (cursor->usage >= DMA_RESV_USAGE_READ)
cursor->fences = dma_resv_shared_list(cursor->obj);
else
cursor->fences = NULL;
@@ -635,7 +635,7 @@ int dma_resv_copy_fences(struct dma_resv *dst, struct
dma_resv *src)
list = NULL;
excl = NULL;
- dma_resv_iter_begin(, src, true);
+ dma_resv_iter_begin(, src, DMA_RESV_USAGE_OTHER);
dma_resv_for_each_fence_unlocked(, f) {
if
[PATCH 24/26] dma-buf: wait for map to complete for static attachments
We have previously done that in the individual drivers but it is
more defensive to move that into the common code.
Dynamic attachments should wait for map operations to complete by themselves.
Signed-off-by: Christian König
---
drivers/dma-buf/dma-buf.c | 18 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 14 +-
drivers/gpu/drm/nouveau/nouveau_prime.c | 17 +
drivers/gpu/drm/radeon/radeon_prime.c | 16 +++-
4 files changed, 20 insertions(+), 45 deletions(-)
diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c
index 528983d3ba64..d3dd602c4753 100644
--- a/drivers/dma-buf/dma-buf.c
+++ b/drivers/dma-buf/dma-buf.c
@@ -660,12 +660,24 @@ static struct sg_table * __map_dma_buf(struct
dma_buf_attachment *attach,
enum dma_data_direction direction)
{
struct sg_table *sg_table;
+ signed long ret;
sg_table = attach->dmabuf->ops->map_dma_buf(attach, direction);
+ if (IS_ERR_OR_NULL(sg_table))
+ return sg_table;
+
+ if (!dma_buf_attachment_is_dynamic(attach)) {
+ ret = dma_resv_wait_timeout(attach->dmabuf->resv,
+ DMA_RESV_USAGE_KERNEL, true,
+ MAX_SCHEDULE_TIMEOUT);
+ if (ret < 0) {
+ attach->dmabuf->ops->unmap_dma_buf(attach, sg_table,
+ direction);
+ return ERR_PTR(ret);
+ }
+ }
- if (!IS_ERR_OR_NULL(sg_table))
- mangle_sg_table(sg_table);
-
+ mangle_sg_table(sg_table);
return sg_table;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
index ae6ab93c868b..57a7a603f987 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
@@ -105,21 +105,9 @@ static int amdgpu_dma_buf_pin(struct dma_buf_attachment
*attach)
{
struct drm_gem_object *obj = attach->dmabuf->priv;
struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
- int r;
/* pin buffer into GTT */
- r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
- if (r)
- return r;
-
- if (bo->tbo.moving) {
- r = dma_fence_wait(bo->tbo.moving, true);
- if (r) {
- amdgpu_bo_unpin(bo);
- return r;
- }
- }
- return 0;
+ return amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
}
/**
diff --git a/drivers/gpu/drm/nouveau/nouveau_prime.c
b/drivers/gpu/drm/nouveau/nouveau_prime.c
index 60019d0532fc..347488685f74 100644
--- a/drivers/gpu/drm/nouveau/nouveau_prime.c
+++ b/drivers/gpu/drm/nouveau/nouveau_prime.c
@@ -93,22 +93,7 @@ int nouveau_gem_prime_pin(struct drm_gem_object *obj)
if (ret)
return -EINVAL;
- ret = ttm_bo_reserve(>bo, false, false, NULL);
- if (ret)
- goto error;
-
- if (nvbo->bo.moving)
- ret = dma_fence_wait(nvbo->bo.moving, true);
-
- ttm_bo_unreserve(>bo);
- if (ret)
- goto error;
-
- return ret;
-
-error:
- nouveau_bo_unpin(nvbo);
- return ret;
+ return 0;
}
void nouveau_gem_prime_unpin(struct drm_gem_object *obj)
diff --git a/drivers/gpu/drm/radeon/radeon_prime.c
b/drivers/gpu/drm/radeon/radeon_prime.c
index 4a90807351e7..42a87948e28c 100644
--- a/drivers/gpu/drm/radeon/radeon_prime.c
+++ b/drivers/gpu/drm/radeon/radeon_prime.c
@@ -77,19 +77,9 @@ int radeon_gem_prime_pin(struct drm_gem_object *obj)
/* pin buffer into GTT */
ret = radeon_bo_pin(bo, RADEON_GEM_DOMAIN_GTT, NULL);
- if (unlikely(ret))
- goto error;
-
- if (bo->tbo.moving) {
- ret = dma_fence_wait(bo->tbo.moving, false);
- if (unlikely(ret)) {
- radeon_bo_unpin(bo);
- goto error;
- }
- }
-
- bo->prime_shared_count++;
-error:
+ if (likely(ret == 0))
+ bo->prime_shared_count++;
+
radeon_bo_unreserve(bo);
return ret;
}
--
2.25.1
[PATCH 26/26] drm/ttm: remove bo->moving
This is now handled by the DMA-buf framework in the dma_resv obj.
Signed-off-by: Christian König
---
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 13 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c| 7 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c| 11 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 11 --
drivers/gpu/drm/ttm/ttm_bo.c | 10 ++
drivers/gpu/drm/ttm/ttm_bo_util.c | 7
drivers/gpu/drm/ttm/ttm_bo_vm.c | 34 +++
drivers/gpu/drm/vmwgfx/vmwgfx_resource.c | 6
include/drm/ttm/ttm_bo_api.h | 2 --
9 files changed, 40 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 0201a44ff630..a32035297995 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -2330,6 +2330,8 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info,
struct dma_fence **ef)
struct amdgpu_bo *bo = mem->bo;
uint32_t domain = mem->domain;
struct kfd_mem_attachment *attachment;
+ struct dma_resv_iter cursor;
+ struct dma_fence *fence;
total_size += amdgpu_bo_size(bo);
@@ -2344,10 +2346,13 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info,
struct dma_fence **ef)
goto validate_map_fail;
}
}
- ret = amdgpu_sync_fence(_obj, bo->tbo.moving);
- if (ret) {
- pr_debug("Memory eviction: Sync BO fence failed. Try
again\n");
- goto validate_map_fail;
+ dma_resv_for_each_fence(, bo->tbo.base.resv,
+ DMA_RESV_USAGE_KERNEL, fence) {
+ ret = amdgpu_sync_fence(_obj, fence);
+ if (ret) {
+ pr_debug("Memory eviction: Sync BO fence
failed. Try again\n");
+ goto validate_map_fail;
+ }
}
list_for_each_entry(attachment, >attachments, list) {
if (!attachment->is_mapped)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index a40ede9bccd0..3881a503a7bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -608,9 +608,8 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
if (unlikely(r))
goto fail_unreserve;
- amdgpu_bo_fence(bo, fence, false);
- dma_fence_put(bo->tbo.moving);
- bo->tbo.moving = dma_fence_get(fence);
+ dma_resv_add_fence(bo->tbo.base.resv, fence,
+ DMA_RESV_USAGE_KERNEL);
dma_fence_put(fence);
}
if (!bp->resv)
@@ -1290,7 +1289,7 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object
*bo)
r = amdgpu_fill_buffer(abo, AMDGPU_POISON, bo->base.resv, );
if (!WARN_ON(r)) {
- amdgpu_bo_fence(abo, fence, false);
+ dma_resv_add_fence(bo->base.resv, fence, DMA_RESV_USAGE_KERNEL);
dma_fence_put(fence);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
index e3fbf0f10add..31913ae86de6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
@@ -74,13 +74,12 @@ static int amdgpu_vm_cpu_update(struct
amdgpu_vm_update_params *p,
{
unsigned int i;
uint64_t value;
- int r;
+ long r;
- if (vmbo->bo.tbo.moving) {
- r = dma_fence_wait(vmbo->bo.tbo.moving, true);
- if (r)
- return r;
- }
+ r = dma_resv_wait_timeout(vmbo->bo.tbo.base.resv, DMA_RESV_USAGE_KERNEL,
+ true, MAX_SCHEDULE_TIMEOUT);
+ if (r < 0)
+ return r;
pe += (unsigned long)amdgpu_bo_kptr(>bo);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
index dbb551762805..bdb44cee19d3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
@@ -204,14 +204,19 @@ static int amdgpu_vm_sdma_update(struct
amdgpu_vm_update_params *p,
struct amdgpu_bo *bo = >bo;
enum amdgpu_ib_pool_type pool = p->immediate ? AMDGPU_IB_POOL_IMMEDIATE
: AMDGPU_IB_POOL_DELAYED;
+ struct dma_resv_iter cursor;
unsigned int i, ndw, nptes;
+ struct dma_fence *fence;
uint64_t *pte;
int r;
/* Wait for PD/PT moves to be completed */
- r = amdgpu_sync_fence(>job->sync, bo->tbo.moving);
-
[PATCH 18/26] dma-buf/drivers: make reserving a shared slot mandatory
Audit all the users of dma_resv_add_excl_fence() and make sure they
reserve a shared slot also when only trying to add an exclusive fence.
This is the next step towards handling the exclusive fence like a
shared one.
Signed-off-by: Christian König
---
drivers/dma-buf/st-dma-resv.c | 64 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c| 8 +++
drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c | 8 +--
drivers/gpu/drm/i915/gem/i915_gem_clflush.c | 3 +-
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 8 +--
.../drm/i915/gem/selftests/i915_gem_migrate.c | 5 +-
drivers/gpu/drm/i915/i915_vma.c | 6 ++
.../drm/i915/selftests/intel_memory_region.c | 7 ++
drivers/gpu/drm/lima/lima_gem.c | 10 ++-
drivers/gpu/drm/msm/msm_gem_submit.c | 18 +++---
drivers/gpu/drm/nouveau/nouveau_fence.c | 9 +--
drivers/gpu/drm/panfrost/panfrost_job.c | 4 ++
drivers/gpu/drm/ttm/ttm_bo_util.c | 12 +++-
drivers/gpu/drm/ttm/ttm_execbuf_util.c| 11 ++--
drivers/gpu/drm/v3d/v3d_gem.c | 15 +++--
drivers/gpu/drm/vgem/vgem_fence.c | 12 ++--
drivers/gpu/drm/virtio/virtgpu_gem.c | 9 +++
drivers/gpu/drm/vmwgfx/vmwgfx_bo.c| 16 +++--
18 files changed, 133 insertions(+), 92 deletions(-)
diff --git a/drivers/dma-buf/st-dma-resv.c b/drivers/dma-buf/st-dma-resv.c
index cbe999c6e7a6..f33bafc78693 100644
--- a/drivers/dma-buf/st-dma-resv.c
+++ b/drivers/dma-buf/st-dma-resv.c
@@ -75,17 +75,16 @@ static int test_signaling(void *arg, bool shared)
goto err_free;
}
- if (shared) {
- r = dma_resv_reserve_shared(, 1);
- if (r) {
- pr_err("Resv shared slot allocation failed\n");
- goto err_unlock;
- }
+ r = dma_resv_reserve_shared(, 1);
+ if (r) {
+ pr_err("Resv shared slot allocation failed\n");
+ goto err_unlock;
+ }
+ if (shared)
dma_resv_add_shared_fence(, f);
- } else {
+ else
dma_resv_add_excl_fence(, f);
- }
if (dma_resv_test_signaled(, shared)) {
pr_err("Resv unexpectedly signaled\n");
@@ -134,17 +133,16 @@ static int test_for_each(void *arg, bool shared)
goto err_free;
}
- if (shared) {
- r = dma_resv_reserve_shared(, 1);
- if (r) {
- pr_err("Resv shared slot allocation failed\n");
- goto err_unlock;
- }
+ r = dma_resv_reserve_shared(, 1);
+ if (r) {
+ pr_err("Resv shared slot allocation failed\n");
+ goto err_unlock;
+ }
+ if (shared)
dma_resv_add_shared_fence(, f);
- } else {
+ else
dma_resv_add_excl_fence(, f);
- }
r = -ENOENT;
dma_resv_for_each_fence(, , shared, fence) {
@@ -206,18 +204,17 @@ static int test_for_each_unlocked(void *arg, bool shared)
goto err_free;
}
- if (shared) {
- r = dma_resv_reserve_shared(, 1);
- if (r) {
- pr_err("Resv shared slot allocation failed\n");
- dma_resv_unlock();
- goto err_free;
- }
+ r = dma_resv_reserve_shared(, 1);
+ if (r) {
+ pr_err("Resv shared slot allocation failed\n");
+ dma_resv_unlock();
+ goto err_free;
+ }
+ if (shared)
dma_resv_add_shared_fence(, f);
- } else {
+ else
dma_resv_add_excl_fence(, f);
- }
dma_resv_unlock();
r = -ENOENT;
@@ -290,18 +287,17 @@ static int test_get_fences(void *arg, bool shared)
goto err_resv;
}
- if (shared) {
- r = dma_resv_reserve_shared(, 1);
- if (r) {
- pr_err("Resv shared slot allocation failed\n");
- dma_resv_unlock();
- goto err_resv;
- }
+ r = dma_resv_reserve_shared(, 1);
+ if (r) {
+ pr_err("Resv shared slot allocation failed\n");
+ dma_resv_unlock();
+ goto err_resv;
+ }
+ if (shared)
dma_resv_add_shared_fence(, f);
- } else {
+ else
dma_resv_add_excl_fence(, f);
- }
dma_resv_unlock();
r = dma_resv_get_fences(, shared, , );
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 4fcfc2313b8c..1becd4e7e463 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -1367,6 +1367,14 @@ void amdgpu_bo_fence(struct amdgpu_bo *bo, struct
dma_fence *fence,
[PATCH 20/26] drm/nouveau: support more than one write fence in fenv50_wndw_prepare_fb
Use dma_resv_get_singleton() here to eventually get more than one write
fence as single fence.
Signed-off-by: Christian König
---
drivers/gpu/drm/nouveau/dispnv50/wndw.c | 14 +-
1 file changed, 5 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.c
b/drivers/gpu/drm/nouveau/dispnv50/wndw.c
index 133c8736426a..b55a8a723581 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/wndw.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.c
@@ -536,8 +536,6 @@ nv50_wndw_prepare_fb(struct drm_plane *plane, struct
drm_plane_state *state)
struct nouveau_bo *nvbo;
struct nv50_head_atom *asyh;
struct nv50_wndw_ctxdma *ctxdma;
- struct dma_resv_iter cursor;
- struct dma_fence *fence;
int ret;
NV_ATOMIC(drm, "%s prepare: %p\n", plane->name, fb);
@@ -560,13 +558,11 @@ nv50_wndw_prepare_fb(struct drm_plane *plane, struct
drm_plane_state *state)
asyw->image.handle[0] = ctxdma->object.handle;
}
- dma_resv_iter_begin(, nvbo->bo.base.resv, false);
- dma_resv_for_each_fence_unlocked(, fence) {
- /* TODO: We only use the first writer here */
- asyw->state.fence = dma_fence_get(fence);
- break;
- }
- dma_resv_iter_end();
+ ret = dma_resv_get_singleton(nvbo->bo.base.resv, false,
+>state.fence);
+ if (ret)
+ return ret;
+
asyw->image.offset[0] = nvbo->offset;
if (wndw->func->prepare) {
--
2.25.1
[PATCH 14/26] drm/amdgpu: remove excl as shared workarounds
This was added because of the now dropped shared on excl dependency.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 5 +
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 6 --
2 files changed, 1 insertion(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 0311d799a010..53e407ea4c89 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -1275,14 +1275,11 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
/*
* Work around dma_resv shortcommings by wrapping up the
* submission in a dma_fence_chain and add it as exclusive
-* fence, but first add the submission as shared fence to make
-* sure that shared fences never signal before the exclusive
-* one.
+* fence.
*/
dma_fence_chain_init(chain, dma_resv_excl_fence(resv),
dma_fence_get(p->fence), 1);
- dma_resv_add_shared_fence(resv, p->fence);
rcu_assign_pointer(resv->fence_excl, >base);
e->chain = NULL;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index a1e63ba4c54a..85d31d85c384 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -226,12 +226,6 @@ static void amdgpu_gem_object_close(struct drm_gem_object
*obj,
if (!amdgpu_vm_ready(vm))
goto out_unlock;
- fence = dma_resv_excl_fence(bo->tbo.base.resv);
- if (fence) {
- amdgpu_bo_fence(bo, fence, true);
- fence = NULL;
- }
-
r = amdgpu_vm_clear_freed(adev, vm, );
if (r || !fence)
goto out_unlock;
--
2.25.1
[PATCH 19/26] drm: support more than one write fence in drm_gem_plane_helper_prepare_fb
Use dma_resv_get_singleton() here to eventually get more than one write
fence as single fence.
Signed-off-by: Christian König
---
drivers/gpu/drm/drm_gem_atomic_helper.c | 18 +++---
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/drm_gem_atomic_helper.c
b/drivers/gpu/drm/drm_gem_atomic_helper.c
index c3189afe10cb..9338ddb7edff 100644
--- a/drivers/gpu/drm/drm_gem_atomic_helper.c
+++ b/drivers/gpu/drm/drm_gem_atomic_helper.c
@@ -143,25 +143,21 @@
*/
int drm_gem_plane_helper_prepare_fb(struct drm_plane *plane, struct
drm_plane_state *state)
{
- struct dma_resv_iter cursor;
struct drm_gem_object *obj;
struct dma_fence *fence;
+ int ret;
if (!state->fb)
return 0;
obj = drm_gem_fb_get_obj(state->fb, 0);
- dma_resv_iter_begin(, obj->resv, false);
- dma_resv_for_each_fence_unlocked(, fence) {
- /* TODO: Currently there should be only one write fence, so this
-* here works fine. But drm_atomic_set_fence_for_plane() should
-* be changed to be able to handle more fences in general for
-* multiple BOs per fb anyway. */
- dma_fence_get(fence);
- break;
- }
- dma_resv_iter_end();
+ ret = dma_resv_get_singleton(obj->resv, false, );
+ if (ret)
+ return ret;
+ /* TODO: drm_atomic_set_fence_for_plane() should be changed to be able
+* to handle more fences in general for multiple BOs per fb.
+*/
drm_atomic_set_fence_for_plane(state, fence);
return 0;
}
--
2.25.1
[PATCH 17/26] dma-buf: drop the DAG approach for the dma_resv object
So far we had the approach of using a directed acyclic
graph with the dma_resv obj.
This turned out to have many downsides, especially it means
that every single driver and user of this interface needs
to be aware of this restriction when adding fences. If the
rules for the DAG are not followed then we end up with
potential hard to debug memory corruption, information
leaks or even elephant big security holes because we allow
userspace to access freed up memory.
Since we already took a step back from that by always
looking at all fences we now go a step further and stop
dropping the shared fences when a new exclusive one is
added.
Signed-off-by: Christian König
---
drivers/dma-buf/dma-resv.c | 14 +-
1 file changed, 1 insertion(+), 13 deletions(-)
diff --git a/drivers/dma-buf/dma-resv.c b/drivers/dma-buf/dma-resv.c
index 539b9b1df640..3b0001c5ff3a 100644
--- a/drivers/dma-buf/dma-resv.c
+++ b/drivers/dma-buf/dma-resv.c
@@ -411,29 +411,17 @@ EXPORT_SYMBOL(dma_resv_replace_fences);
void dma_resv_add_excl_fence(struct dma_resv *obj, struct dma_fence *fence)
{
struct dma_fence *old_fence = dma_resv_excl_fence(obj);
- struct dma_resv_list *old;
- u32 i = 0;
dma_resv_assert_held(obj);
- old = dma_resv_shared_list(obj);
- if (old)
- i = old->shared_count;
-
dma_fence_get(fence);
write_seqcount_begin(>seq);
/* write_seqcount_begin provides the necessary memory barrier */
RCU_INIT_POINTER(obj->fence_excl, fence);
- if (old)
- old->shared_count = 0;
+ dma_resv_list_prune(dma_resv_shared_list(obj), obj);
write_seqcount_end(>seq);
- /* inplace update, no shared fences */
- while (i--)
- dma_fence_put(rcu_dereference_protected(old->shared[i],
- dma_resv_held(obj)));
-
dma_fence_put(old_fence);
}
EXPORT_SYMBOL(dma_resv_add_excl_fence);
--
2.25.1
[PATCH 21/26] drm/amdgpu: use dma_resv_get_singleton in amdgpu_pasid_free_cb
Makes the code a bit more simpler.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 23 +++
1 file changed, 3 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
index be48487e2ca7..888d97143177 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
@@ -107,36 +107,19 @@ static void amdgpu_pasid_free_cb(struct dma_fence *fence,
void amdgpu_pasid_free_delayed(struct dma_resv *resv,
u32 pasid)
{
- struct dma_fence *fence, **fences;
struct amdgpu_pasid_cb *cb;
- unsigned count;
+ struct dma_fence *fence;
int r;
- r = dma_resv_get_fences(resv, true, , );
+ r = dma_resv_get_singleton(resv, true, );
if (r)
goto fallback;
- if (count == 0) {
+ if (!fence) {
amdgpu_pasid_free(pasid);
return;
}
- if (count == 1) {
- fence = fences[0];
- kfree(fences);
- } else {
- uint64_t context = dma_fence_context_alloc(1);
- struct dma_fence_array *array;
-
- array = dma_fence_array_create(count, fences, context,
- 1, false);
- if (!array) {
- kfree(fences);
- goto fallback;
- }
- fence = >base;
- }
-
cb = kmalloc(sizeof(*cb), GFP_KERNEL);
if (!cb) {
/* Last resort when we are OOM */
--
2.25.1
[PATCH 23/26] dma-buf: specify usage while adding fences to dma_resv obj
Instead of distingting between shared and exclusive fences specify
the fence usage while adding fences.
Rework all drivers to use this interface instead and deprecate the old one.
Signed-off-by: Christian König
---
drivers/dma-buf/dma-resv.c| 389 --
drivers/dma-buf/st-dma-resv.c | 109 ++---
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 6 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c| 6 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c| 6 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c| 4 +-
drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 2 +-
drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c | 12 +-
drivers/gpu/drm/i915/gem/i915_gem_busy.c | 13 +-
drivers/gpu/drm/i915/gem/i915_gem_clflush.c | 5 +-
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 4 +-
.../drm/i915/gem/selftests/i915_gem_migrate.c | 2 +-
drivers/gpu/drm/i915/i915_vma.c | 10 +-
.../drm/i915/selftests/intel_memory_region.c | 2 +-
drivers/gpu/drm/lima/lima_gem.c | 4 +-
drivers/gpu/drm/msm/msm_gem_submit.c | 4 +-
drivers/gpu/drm/nouveau/nouveau_bo.c | 9 +-
drivers/gpu/drm/nouveau/nouveau_fence.c | 2 +-
drivers/gpu/drm/panfrost/panfrost_job.c | 2 +-
drivers/gpu/drm/qxl/qxl_release.c | 5 +-
drivers/gpu/drm/radeon/radeon_object.c| 6 +-
drivers/gpu/drm/radeon/radeon_vm.c| 2 +-
drivers/gpu/drm/ttm/ttm_bo.c | 6 +-
drivers/gpu/drm/ttm/ttm_bo_util.c | 7 +-
drivers/gpu/drm/ttm/ttm_execbuf_util.c| 10 +-
drivers/gpu/drm/v3d/v3d_gem.c | 6 +-
drivers/gpu/drm/vc4/vc4_gem.c | 4 +-
drivers/gpu/drm/vgem/vgem_fence.c | 11 +-
drivers/gpu/drm/virtio/virtgpu_gem.c | 5 +-
drivers/gpu/drm/vmwgfx/vmwgfx_bo.c| 5 +-
include/linux/dma-resv.h | 88 ++--
31 files changed, 312 insertions(+), 434 deletions(-)
diff --git a/drivers/dma-buf/dma-resv.c b/drivers/dma-buf/dma-resv.c
index 7ef8182a4b59..c1e5372bac6f 100644
--- a/drivers/dma-buf/dma-resv.c
+++ b/drivers/dma-buf/dma-resv.c
@@ -44,12 +44,12 @@
/**
* DOC: Reservation Object Overview
*
- * The reservation object provides a mechanism to manage shared and
- * exclusive fences associated with a buffer. A reservation object
- * can have attached one exclusive fence (normally associated with
- * write operations) or N shared fences (read operations). The RCU
- * mechanism is used to protect read access to fences from locked
- * write-side updates.
+ * The reservation object provides a mechanism to manage a container of
+ * dma_fence object associated with a resource. A reservation object
+ * can have any number of fences attaches to it. Each fence carring an usage
+ * parameter determining how the operation represented by the fence is using
the
+ * resource. The RCU mechanism is used to protect read access to fences from
+ * locked write-side updates.
*
* See struct dma_resv for more details.
*/
@@ -57,36 +57,80 @@
DEFINE_WD_CLASS(reservation_ww_class);
EXPORT_SYMBOL(reservation_ww_class);
+/* Mask for the lower fence pointer bits */
+#define DMA_RESV_LIST_MASK 0x3
+
/**
- * struct dma_resv_list - a list of shared fences
+ * struct dma_resv_list - an array of fences
* @rcu: for internal use
- * @shared_count: table of shared fences
- * @shared_max: for growing shared fence table
- * @shared: shared fence table
+ * @num_fences: table of fences
+ * @max_fences: for growing fence table
+ * @table: fence table
*/
struct dma_resv_list {
struct rcu_head rcu;
- u32 shared_count, shared_max;
- struct dma_fence __rcu *shared[];
+ u32 num_fences, max_fences;
+ struct dma_fence __rcu *table[];
};
+/**
+ * dma_resv_list_entry - extract fence and usage from a list entry
+ * @list: the list to extract and entry from
+ * @index: which entry we want
+ * @check: lockdep check that the access is allowed
+ * @fence: the resulting fence
+ * @usage: the resulting usage
+ *
+ * Extract the fence and usage flags from an RCU protected entry in the list.
+ */
+static void dma_resv_list_entry(struct dma_resv_list *list, unsigned int index,
+ bool check, struct dma_fence **fence,
+ enum dma_resv_usage *usage)
+{
+ long tmp;
+
+ tmp = (long)rcu_dereference_check(list->table[index], check);
+ *fence = (struct dma_fence *)(tmp & ~DMA_RESV_LIST_MASK);
+ if (usage)
+ *usage = tmp & DMA_RESV_LIST_MASK;
+}
+
+/**
+ * dma_resv_list_set - set fence and usage at a specific index
+ * @list: the list to modify
+ * @index: where to make the change
+ * @fence: the fence to set
+ * @usage: the usage to set
+ *
+ * Set the fence and usage flags at the specific index in the list.
+ */
+static void dma_resv_list_set(struct dma_resv_list *list,
+
[PATCH 11/26] drm/nouveau: stop using dma_resv_excl_fence
Instead use the new dma_resv_get_singleton function.
Signed-off-by: Christian König
---
drivers/gpu/drm/nouveau/nouveau_bo.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c
b/drivers/gpu/drm/nouveau/nouveau_bo.c
index fa73fe57f97b..74f8652d2bd3 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -959,7 +959,14 @@ nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
{
struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
struct drm_device *dev = drm->dev;
- struct dma_fence *fence = dma_resv_excl_fence(bo->base.resv);
+ struct dma_fence *fence;
+ int ret;
+
+ /* TODO: This is actually a memory management dependency */
+ ret = dma_resv_get_singleton(bo->base.resv, false, );
+ if (ret)
+ dma_resv_wait_timeout(bo->base.resv, false, false,
+ MAX_SCHEDULE_TIMEOUT);
nv10_bo_put_tile_region(dev, *old_tile, fence);
*old_tile = new_tile;
--
2.25.1
[PATCH 16/26] dma-buf: finally make dma_resv_excl_fence private
Drivers should never touch this directly.
Signed-off-by: Christian König
---
drivers/dma-buf/dma-resv.c | 17 +
include/linux/dma-resv.h | 17 -
2 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/drivers/dma-buf/dma-resv.c b/drivers/dma-buf/dma-resv.c
index f91ca023b550..539b9b1df640 100644
--- a/drivers/dma-buf/dma-resv.c
+++ b/drivers/dma-buf/dma-resv.c
@@ -175,6 +175,23 @@ void dma_resv_fini(struct dma_resv *obj)
}
EXPORT_SYMBOL(dma_resv_fini);
+/**
+ * dma_resv_excl_fence - return the object's exclusive fence
+ * @obj: the reservation object
+ *
+ * Returns the exclusive fence (if any). Caller must either hold the objects
+ * through dma_resv_lock() or the RCU read side lock through rcu_read_lock(),
+ * or one of the variants of each
+ *
+ * RETURNS
+ * The exclusive fence or NULL
+ */
+static inline struct dma_fence *
+dma_resv_excl_fence(struct dma_resv *obj)
+{
+ return rcu_dereference_check(obj->fence_excl, dma_resv_held(obj));
+}
+
/**
* dma_resv_shared_list - get the reservation object's shared fence list
* @obj: the reservation object
diff --git a/include/linux/dma-resv.h b/include/linux/dma-resv.h
index 082f77b7bc63..062571c04bca 100644
--- a/include/linux/dma-resv.h
+++ b/include/linux/dma-resv.h
@@ -412,23 +412,6 @@ static inline void dma_resv_unlock(struct dma_resv *obj)
ww_mutex_unlock(>lock);
}
-/**
- * dma_resv_excl_fence - return the object's exclusive fence
- * @obj: the reservation object
- *
- * Returns the exclusive fence (if any). Caller must either hold the objects
- * through dma_resv_lock() or the RCU read side lock through rcu_read_lock(),
- * or one of the variants of each
- *
- * RETURNS
- * The exclusive fence or NULL
- */
-static inline struct dma_fence *
-dma_resv_excl_fence(struct dma_resv *obj)
-{
- return rcu_dereference_check(obj->fence_excl, dma_resv_held(obj));
-}
-
void dma_resv_init(struct dma_resv *obj);
void dma_resv_fini(struct dma_resv *obj);
int dma_resv_reserve_shared(struct dma_resv *obj, unsigned int num_fences);
--
2.25.1
[PATCH 15/26] drm/amdgpu: use dma_resv_for_each_fence for CS workaround
Get the write fence using dma_resv_for_each_fence instead of accessing
it manually.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 53e407ea4c89..7facd614e50a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -1268,6 +1268,8 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
amdgpu_bo_list_for_each_entry(e, p->bo_list) {
struct dma_resv *resv = e->tv.bo->base.resv;
struct dma_fence_chain *chain = e->chain;
+ struct dma_resv_iter cursor;
+ struct dma_fence *fence;
if (!chain)
continue;
@@ -1277,9 +1279,10 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
* submission in a dma_fence_chain and add it as exclusive
* fence.
*/
- dma_fence_chain_init(chain, dma_resv_excl_fence(resv),
-dma_fence_get(p->fence), 1);
-
+ dma_resv_for_each_fence(, resv, false, fence) {
+ break;
+ }
+ dma_fence_chain_init(chain, fence, dma_fence_get(p->fence), 1);
rcu_assign_pointer(resv->fence_excl, >base);
e->chain = NULL;
}
--
2.25.1
[PATCH 10/26] drm/etnaviv: stop using dma_resv_excl_fence
We can get the excl fence together with the shared ones as well.
Signed-off-by: Christian König
---
drivers/gpu/drm/etnaviv/etnaviv_gem.h| 1 -
drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c | 14 +-
drivers/gpu/drm/etnaviv/etnaviv_sched.c | 10 --
3 files changed, 5 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem.h
b/drivers/gpu/drm/etnaviv/etnaviv_gem.h
index 98e60df882b6..f596d743baa3 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gem.h
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gem.h
@@ -80,7 +80,6 @@ struct etnaviv_gem_submit_bo {
u64 va;
struct etnaviv_gem_object *obj;
struct etnaviv_vram_mapping *mapping;
- struct dma_fence *excl;
unsigned int nr_shared;
struct dma_fence **shared;
};
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c
b/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c
index 64c90ff348f2..4286dc93fdaa 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c
@@ -188,15 +188,11 @@ static int submit_fence_sync(struct etnaviv_gem_submit
*submit)
if (submit->flags & ETNA_SUBMIT_NO_IMPLICIT)
continue;
- if (bo->flags & ETNA_SUBMIT_BO_WRITE) {
- ret = dma_resv_get_fences(robj, true, >nr_shared,
- >shared);
- if (ret)
- return ret;
- } else {
- bo->excl = dma_fence_get(dma_resv_excl_fence(robj));
- }
-
+ ret = dma_resv_get_fences(robj,
+ !!(bo->flags & ETNA_SUBMIT_BO_WRITE),
+ >nr_shared, >shared);
+ if (ret)
+ return ret;
}
return ret;
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_sched.c
b/drivers/gpu/drm/etnaviv/etnaviv_sched.c
index 180bb633d5c5..8c038a363d15 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_sched.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_sched.c
@@ -39,16 +39,6 @@ etnaviv_sched_dependency(struct drm_sched_job *sched_job,
struct etnaviv_gem_submit_bo *bo = >bos[i];
int j;
- if (bo->excl) {
- fence = bo->excl;
- bo->excl = NULL;
-
- if (!dma_fence_is_signaled(fence))
- return fence;
-
- dma_fence_put(fence);
- }
-
for (j = 0; j < bo->nr_shared; j++) {
if (!bo->shared[j])
continue;
--
2.25.1
[PATCH 09/26] RDMA: use dma_resv_wait() instead of extracting the fence
Use dma_resv_wait() instead of extracting the exclusive fence and
waiting on it manually.
Signed-off-by: Christian König
---
drivers/infiniband/core/umem_dmabuf.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/infiniband/core/umem_dmabuf.c
b/drivers/infiniband/core/umem_dmabuf.c
index f0760741f281..d32cd7538835 100644
--- a/drivers/infiniband/core/umem_dmabuf.c
+++ b/drivers/infiniband/core/umem_dmabuf.c
@@ -16,7 +16,6 @@ int ib_umem_dmabuf_map_pages(struct ib_umem_dmabuf
*umem_dmabuf)
{
struct sg_table *sgt;
struct scatterlist *sg;
- struct dma_fence *fence;
unsigned long start, end, cur = 0;
unsigned int nmap = 0;
int i;
@@ -68,11 +67,8 @@ int ib_umem_dmabuf_map_pages(struct ib_umem_dmabuf
*umem_dmabuf)
* may be not up-to-date. Wait for the exporter to finish
* the migration.
*/
- fence = dma_resv_excl_fence(umem_dmabuf->attach->dmabuf->resv);
- if (fence)
- return dma_fence_wait(fence, false);
-
- return 0;
+ return dma_resv_wait_timeout(umem_dmabuf->attach->dmabuf->resv, false,
+false, MAX_SCHEDULE_TIMEOUT);
}
EXPORT_SYMBOL(ib_umem_dmabuf_map_pages);
--
2.25.1
